2 * Platform driver for the Realtek RTL8366 ethernet switch
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
27 #include <linux/debugfs.h>
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
132 RTL8366_PORT_UNKNOWN | \
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
139 RTL8366_PORT_UNKNOWN)
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
149 struct rtl8366s_vlanconfig {
160 struct rtl8366s_vlan4kentry {
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
172 "EtherStatsUnderSizePkts ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
214 struct dentry *debugfs_root;
222 static inline struct rtl8366_smi *sw_to_rtl8366(struct switch_dev *sw)
224 return container_of(sw, struct rtl8366_smi, dev);
227 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
229 ndelay(RTL8366_SMI_CLK_DELAY);
232 static void rtl8366_smi_start(struct rtl8366_smi *smi)
234 unsigned int sda = smi->pdata->gpio_sda;
235 unsigned int sck = smi->pdata->gpio_sck;
238 * Set GPIO pins to output mode, with initial state:
241 gpio_direction_output(sck, 0);
242 gpio_direction_output(sda, 1);
243 rtl8366_smi_clk_delay(smi);
245 /* CLK 1: 0 -> 1, 1 -> 0 */
246 gpio_set_value(sck, 1);
247 rtl8366_smi_clk_delay(smi);
248 gpio_set_value(sck, 0);
249 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 1);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 0);
255 rtl8366_smi_clk_delay(smi);
256 gpio_set_value(sck, 0);
257 rtl8366_smi_clk_delay(smi);
258 gpio_set_value(sda, 1);
261 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
263 unsigned int sda = smi->pdata->gpio_sda;
264 unsigned int sck = smi->pdata->gpio_sck;
266 rtl8366_smi_clk_delay(smi);
267 gpio_set_value(sda, 0);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sda, 1);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
273 rtl8366_smi_clk_delay(smi);
274 gpio_set_value(sck, 0);
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 1);
279 rtl8366_smi_clk_delay(smi);
280 gpio_set_value(sck, 0);
281 rtl8366_smi_clk_delay(smi);
282 gpio_set_value(sck, 1);
284 /* set GPIO pins to input mode */
285 gpio_direction_input(sda);
286 gpio_direction_input(sck);
289 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
291 unsigned int sda = smi->pdata->gpio_sda;
292 unsigned int sck = smi->pdata->gpio_sck;
294 for (; len > 0; len--) {
295 rtl8366_smi_clk_delay(smi);
298 if ( data & ( 1 << (len - 1)) )
299 gpio_set_value(sda, 1);
301 gpio_set_value(sda, 0);
302 rtl8366_smi_clk_delay(smi);
305 gpio_set_value(sck, 1);
306 rtl8366_smi_clk_delay(smi);
307 gpio_set_value(sck, 0);
311 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
313 unsigned int sda = smi->pdata->gpio_sda;
314 unsigned int sck = smi->pdata->gpio_sck;
316 gpio_direction_input(sda);
318 for (*data = 0; len > 0; len--) {
321 rtl8366_smi_clk_delay(smi);
324 gpio_set_value(sck, 1);
325 rtl8366_smi_clk_delay(smi);
326 u = gpio_get_value(sda);
327 gpio_set_value(sck, 0);
329 *data |= (u << (len - 1));
332 gpio_direction_output(sda, 0);
335 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
343 rtl8366_smi_read_bits(smi, 1, &ack);
347 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
354 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
356 rtl8366_smi_write_bits(smi, data, 8);
357 return rtl8366_smi_wait_for_ack(smi);
360 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
365 rtl8366_smi_read_bits(smi, 8, &t);
369 rtl8366_smi_write_bits(smi, 0x00, 1);
374 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
379 rtl8366_smi_read_bits(smi, 8, &t);
383 rtl8366_smi_write_bits(smi, 0x01, 1);
388 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
395 spin_lock_irqsave(&smi->lock, flags);
397 rtl8366_smi_start(smi);
399 /* send READ command */
400 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
405 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
410 ret = rtl8366_smi_write_byte(smi, addr >> 8);
415 rtl8366_smi_read_byte0(smi, &lo);
416 /* read DATA[15:8] */
417 rtl8366_smi_read_byte1(smi, &hi);
419 *data = ((u32) lo) | (((u32) hi) << 8);
424 rtl8366_smi_stop(smi);
425 spin_unlock_irqrestore(&smi->lock, flags);
430 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
435 spin_lock_irqsave(&smi->lock, flags);
437 rtl8366_smi_start(smi);
439 /* send WRITE command */
440 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
445 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
450 ret = rtl8366_smi_write_byte(smi, addr >> 8);
454 /* write DATA[7:0] */
455 ret = rtl8366_smi_write_byte(smi, data & 0xff);
459 /* write DATA[15:8] */
460 ret = rtl8366_smi_write_byte(smi, data >> 8);
467 rtl8366_smi_stop(smi);
468 spin_unlock_irqrestore(&smi->lock, flags);
473 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
474 u32 phy_no, u32 page, u32 addr, u32 *data)
479 if (phy_no > RTL8366S_PHY_NO_MAX)
482 if (page > RTL8366S_PHY_PAGE_MAX)
485 if (addr > RTL8366S_PHY_ADDR_MAX)
488 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
489 RTL8366S_PHY_CTRL_READ);
493 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
494 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
495 (addr & RTL8366S_PHY_REG_MASK);
497 ret = rtl8366_smi_write_reg(smi, reg, 0);
501 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
508 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
509 u32 phy_no, u32 page, u32 addr, u32 data)
514 if (phy_no > RTL8366S_PHY_NO_MAX)
517 if (page > RTL8366S_PHY_PAGE_MAX)
520 if (addr > RTL8366S_PHY_ADDR_MAX)
523 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
524 RTL8366S_PHY_CTRL_WRITE);
528 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
529 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
530 (addr & RTL8366S_PHY_REG_MASK);
532 ret = rtl8366_smi_write_reg(smi, reg, data);
539 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
540 int port, unsigned long long *val)
544 u32 addr, data, regoffset;
547 /* address offset to MIBs counter */
548 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
549 2, 2, 2, 2, 2, 2, 2, 2, 2,
550 2, 2, 4, 2, 2, 2, 2, 2, 2,
553 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
557 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
559 while (i < counter) {
560 regoffset += mibLength[i];
564 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
567 /* writing access counter address first */
568 /* then ASIC will prepare 64bits counter wait for being retrived */
569 data = 0;/* writing data will be discard by ASIC */
570 err = rtl8366_smi_write_reg(smi, addr, data);
574 /* read MIB control register */
575 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
579 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
582 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
586 addr = addr + mibLength[counter] - 1;
587 i = mibLength[counter];
590 err = rtl8366_smi_read_reg(smi, addr, &data);
594 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
604 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
605 struct rtl8366s_vlan4kentry *vlan4k)
611 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
614 if (vid >= RTL8366_NUM_VIDS)
617 tableaddr = (u16 *)vlan4k;
621 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
625 /* write table access control word */
626 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
627 RTL8366S_TABLE_VLAN_READ_CTRL);
631 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
638 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
649 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
650 const struct rtl8366s_vlan4kentry *vlan4k)
656 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
657 vlan4k->member > RTL8366_PORT_ALL ||
658 vlan4k->untag > RTL8366_PORT_ALL ||
659 vlan4k->fid > RTL8366S_FIDMAX)
662 tableaddr = (u16 *)vlan4k;
666 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
674 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
677 /* write table access control word */
678 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
679 RTL8366S_TABLE_VLAN_WRITE_CTRL);
686 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
687 struct rtl8366s_vlanconfig *vlanmc)
694 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
696 if (index >= RTL8366_NUM_VLANS)
699 tableaddr = (u16 *)vlanmc;
701 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
703 err = rtl8366_smi_read_reg(smi, addr, &data);
710 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
712 err = rtl8366_smi_read_reg(smi, addr, &data);
721 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
722 const struct rtl8366s_vlanconfig
730 if (index >= RTL8366_NUM_VLANS ||
731 vlanmc->vid >= RTL8366_NUM_VIDS ||
732 vlanmc->priority > RTL8366S_PRIORITYMAX ||
733 vlanmc->member > RTL8366_PORT_ALL ||
734 vlanmc->untag > RTL8366_PORT_ALL ||
735 vlanmc->fid > RTL8366S_FIDMAX)
738 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
741 tableaddr = (u16 *)vlanmc;
744 err = rtl8366_smi_write_reg(smi, addr, data);
748 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
753 err = rtl8366_smi_write_reg(smi, addr, data);
760 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
767 /* bits mapping to port vlan control register of port n */
768 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
769 0xF000, 0x000F, 0x00F0 };
770 /* bits offset to port vlan control register of port n */
771 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
772 /* address offset to port vlan control register of port n */
773 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
775 if (port >= RTL8366_NUM_PORTS)
778 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
780 err = rtl8366_smi_read_reg(smi, addr, &data);
784 *val = (data & bits[port]) >> bitoffset[port];
790 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
795 struct rtl8366s_vlanconfig vlanmc;
797 err = rtl8366_get_port_vlan_index(smi, port, &index);
801 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
809 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
818 /* bits mapping to port vlan control register of port n */
819 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
820 0xF000, 0x000F, 0x00F0 };
821 /* bits offset to port vlan control register of port n */
822 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
823 /* address offset to port vlan control register of port n */
824 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
826 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
829 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
831 bits = bitmasks[port];
833 data = (index << bitOff[port]) & bits;
835 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
839 vlan_data &= ~(vlan_data & bits);
842 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
849 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
853 struct rtl8366s_vlanconfig vlanmc;
854 struct rtl8366s_vlan4kentry vlan4k;
856 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
861 /* Updating the 4K entry; lookup it and change the port member set */
862 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
863 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
864 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
865 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
867 /* For the 16 entries more work needs to be done. First see if such
868 VID is already there and change it */
869 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
870 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
872 /* Try to find an existing vid and update port member set */
873 if (val == vlanmc.vid) {
874 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
875 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
877 /* Now update PVID register settings */
878 rtl8366_set_port_vlan_index(smi, port, i);
884 /* PVID could not be found from vlan table. Replace unused (one that
885 has no member ports) with new one */
886 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
887 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
889 /* See if this vlan member configuration is unused. It is
890 unused if member set contains no ports or CPU port only */
891 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
894 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
895 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
898 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
900 /* Now update PVID register settings */
901 rtl8366_set_port_vlan_index(smi, port, i);
907 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
913 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
916 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
918 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
920 data |= RTL8366_CHIP_CTRL_VLAN;
922 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
925 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
928 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
934 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
937 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
940 struct rtl8366s_vlan4kentry vlan4k;
941 struct rtl8366s_vlanconfig vlanmc;
943 /* clear 16 VLAN member configuration */
944 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
950 if (rtl8366s_set_vlan_member_config(smi, i, &vlanmc) != 0)
954 /* Set a default VLAN with vid 1 to 4K table for all ports */
956 vlan4k.member = RTL8366_PORT_ALL;
957 vlan4k.untag = RTL8366_PORT_ALL;
959 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4k) != 0)
962 /* Set all ports PVID to default VLAN */
963 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
964 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
972 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
974 file->private_data = inode->i_private;
978 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
979 char __user *user_buf,
980 size_t count, loff_t *ppos)
983 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
984 char *buf = smi->buf;
986 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
987 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
989 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
992 for (i = 0; i < 33; ++i) {
994 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
996 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
997 unsigned long long counter = 0;
999 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
1000 len += snprintf(buf + len, sizeof(smi->buf) - len,
1003 len += snprintf(buf + len, sizeof(smi->buf) - len,
1006 if (j != RTL8366_NUM_PORTS - 1) {
1007 if (counter < 100000)
1008 len += snprintf(buf + len,
1009 sizeof(smi->buf) - len,
1012 len += snprintf(buf + len, sizeof(smi->buf) - len,
1016 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1019 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1021 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1024 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1025 char __user *user_buf,
1026 size_t count, loff_t *ppos)
1029 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1030 char *buf = smi->buf;
1032 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN Member Config:\n");
1033 len += snprintf(buf + len, sizeof(smi->buf) - len,
1034 "\t id \t vid \t prio \t member \t untag \t fid "
1037 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1038 struct rtl8366s_vlanconfig vlanmc;
1040 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1042 len += snprintf(buf + len, sizeof(smi->buf) - len,
1043 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1044 "\t", i, vlanmc.vid, vlanmc.priority,
1045 vlanmc.member, vlanmc.untag, vlanmc.fid);
1047 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1049 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1051 len += snprintf(buf + len,
1052 sizeof(smi->buf) - len,
1056 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1059 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1062 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1063 char __user *user_buf,
1064 size_t count, loff_t *ppos)
1066 u32 t, reg = g_dbg_reg;
1068 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1069 char *buf = smi->buf;
1071 memset(buf, '\0', sizeof(smi->buf));
1073 err = rtl8366_smi_read_reg(smi, reg, &t);
1075 len += snprintf(buf, sizeof(smi->buf),
1076 "Read failed (reg: 0x%04x)\n", reg);
1077 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1080 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1083 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1086 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1087 const char __user *user_buf,
1088 size_t count, loff_t *ppos)
1091 u32 reg = g_dbg_reg;
1094 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1095 char *buf = smi->buf;
1097 len = min(count, sizeof(smi->buf) - 1);
1098 if (copy_from_user(buf, user_buf, len)) {
1099 dev_err(&smi->pdev->dev, "copy from user failed\n");
1104 if (len > 0 && buf[len - 1] == '\n')
1105 buf[len - 1] = '\0';
1108 if (strict_strtoul(buf, 16, &data)) {
1109 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1111 err = rtl8366_smi_write_reg(smi, reg, data);
1113 dev_err(&smi->pdev->dev,
1114 "writing reg 0x%04x val 0x%04lx failed\n",
1122 static const struct file_operations fops_rtl8366_regs = {
1123 .read = rtl8366_read_debugfs_reg,
1124 .write = rtl8366_write_debugfs_reg,
1125 .open = rtl8366_debugfs_open,
1126 .owner = THIS_MODULE
1129 static const struct file_operations fops_rtl8366_vlan = {
1130 .read = rtl8366_read_debugfs_vlan,
1131 .open = rtl8366_debugfs_open,
1132 .owner = THIS_MODULE
1135 static const struct file_operations fops_rtl8366_mibs = {
1136 .read = rtl8366_read_debugfs_mibs,
1137 .open = rtl8366_debugfs_open,
1138 .owner = THIS_MODULE
1141 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1143 struct dentry *node;
1144 struct dentry *root;
1146 if (!smi->debugfs_root)
1147 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1149 if (!smi->debugfs_root) {
1150 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1153 root = smi->debugfs_root;
1155 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1157 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1161 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1162 &fops_rtl8366_regs);
1164 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1168 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1169 &fops_rtl8366_vlan);
1171 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1176 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1177 &fops_rtl8366_mibs);
1179 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1185 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1187 if (smi->debugfs_root) {
1188 debugfs_remove_recursive(smi->debugfs_root);
1189 smi->debugfs_root = NULL;
1194 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1195 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1198 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1199 const struct switch_attr *attr,
1200 struct switch_val *val)
1203 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1205 if (val->value.i == 1) {
1206 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1208 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1214 static int rtl8366_get_vlan(struct switch_dev *dev,
1215 const struct switch_attr *attr,
1216 struct switch_val *val)
1219 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1221 if (attr->ofs == 1) {
1222 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1224 if (data & RTL8366_CHIP_CTRL_VLAN)
1228 } else if (attr->ofs == 2) {
1229 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1240 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1241 const struct switch_attr *attr,
1242 struct switch_val *val)
1245 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1246 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1248 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1253 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1254 const struct switch_attr *attr,
1255 struct switch_val *val)
1258 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1260 if (val->value.i >= 6)
1263 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1265 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1266 data |= val->value.i;
1268 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1273 static int rtl8366_set_vlan(struct switch_dev *dev,
1274 const struct switch_attr *attr,
1275 struct switch_val *val)
1277 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1280 return rtl8366_vlan_set_vlan(smi, val->value.i);
1282 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1285 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1286 const struct switch_attr *attr,
1287 struct switch_val *val)
1289 u32 len = 0, data = 0;
1290 int speed, duplex, link, txpause, rxpause, nway;
1291 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1292 char *buf = smi->buf;
1294 if (val->port_vlan >= RTL8366_NUM_PORTS)
1297 memset(buf, '\0', sizeof(smi->buf));
1298 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1299 (val->port_vlan >> 1),
1302 if (val->port_vlan & 0x1)
1305 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1306 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1307 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1308 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1309 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1310 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1312 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d: ",
1316 len += snprintf(buf + len, sizeof(smi->buf) - len,
1317 "Link UP, Speed: ");
1319 len += snprintf(buf + len, sizeof(smi->buf) - len,
1320 "Link DOWN, Speed: ");
1323 len += snprintf(buf + len, sizeof(smi->buf) - len, "10Base-TX ");
1324 else if (speed == 1)
1325 len += snprintf(buf + len, sizeof(smi->buf) - len, "100Base-TX ");
1326 else if (speed == 2)
1327 len += snprintf(buf + len, sizeof(smi->buf) - len, "1000Base-TX ");
1330 len += snprintf(buf + len, sizeof(smi->buf) - len, "Full-Duplex, ");
1332 len += snprintf(buf + len, sizeof(smi->buf) - len, "Half-Duplex, ");
1335 len += snprintf(buf + len, sizeof(smi->buf) - len, "TX-Pause ");
1337 len += snprintf(buf + len, sizeof(smi->buf) - len, "RX-Pause ");
1339 len += snprintf(buf + len, sizeof(smi->buf) - len, "nway ");
1347 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1348 const struct switch_attr *attr,
1349 struct switch_val *val)
1353 struct rtl8366s_vlanconfig vlanmc;
1354 struct rtl8366s_vlan4kentry vlan4k;
1355 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1356 char *buf = smi->buf;
1358 if (val->port_vlan >= RTL8366_NUM_PORTS)
1361 memset(buf, '\0', sizeof(smi->buf));
1363 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1364 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1366 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1369 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1371 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1372 index == val->port_vlan)
1373 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d", i);
1375 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1377 len += snprintf(buf + len, sizeof(smi->buf) - len,
1378 "\t\t vid \t prio \t member \t untag \t fid\n");
1379 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1380 len += snprintf(buf + len, sizeof(smi->buf) - len,
1381 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1382 vlanmc.vid, vlanmc.priority, vlanmc.member,
1383 vlanmc.untag, vlanmc.fid);
1384 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1385 len += snprintf(buf + len, sizeof(smi->buf) - len,
1386 "%d \t \t 0x%04x \t 0x%04x \t %d",
1387 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1395 static int rtl8366_set_port_led(struct switch_dev *dev,
1396 const struct switch_attr *attr,
1397 struct switch_val *val)
1400 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1401 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1402 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1405 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1406 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1407 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1408 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1410 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1411 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1412 (val->value.i << (val->port_vlan * 4));
1413 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1419 static int rtl8366_get_port_led(struct switch_dev *dev,
1420 const struct switch_attr *attr,
1421 struct switch_val *val)
1424 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1425 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1428 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1429 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1434 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1435 const struct switch_attr *attr,
1436 struct switch_val *val)
1439 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1440 if (val->port_vlan >= RTL8366_NUM_PORTS)
1443 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1444 data |= (1 << (val->port_vlan + 3));
1445 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1450 static int rtl8366_get_port_mib(struct switch_dev *dev,
1451 const struct switch_attr *attr,
1452 struct switch_val *val)
1455 unsigned long long counter = 0;
1456 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1457 char *buf = smi->buf;
1459 if (val->port_vlan >= RTL8366_NUM_PORTS)
1462 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d MIB counters\n",
1464 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1466 len += snprintf(buf + len, sizeof(smi->buf) - len,
1467 "%d:%s\t", i, MIBCOUNTERS[i]);
1468 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1469 len += snprintf(buf + len, sizeof(smi->buf) - len,
1470 "[%llu]\n", counter);
1472 len += snprintf(buf + len, sizeof(smi->buf) - len,
1481 static int rtl8366_get_ports(struct switch_dev *dev,
1482 struct switch_val *val)
1484 struct rtl8366s_vlanconfig vlanmc;
1485 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1486 struct switch_port *port;
1489 if (val->port_vlan >= RTL8366_NUM_VLANS)
1492 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1494 port = &val->value.ports[0];
1496 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1497 if (!(vlanmc.member & BIT(i)))
1501 port->flags = (vlanmc.untag & BIT(i)) ?
1502 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1509 static int rtl8366_set_ports(struct switch_dev *dev,
1510 struct switch_val *val)
1512 struct rtl8366s_vlanconfig vlanmc;
1513 struct rtl8366s_vlan4kentry vlan4k;
1514 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1515 struct switch_port *port;
1518 if (val->port_vlan >= RTL8366_NUM_VLANS)
1521 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1522 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1527 port = &val->value.ports[0];
1528 for (i = 0; i < val->len; i++, port++) {
1529 vlanmc.member |= BIT(port->id);
1531 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1532 vlanmc.untag |= BIT(port->id);
1535 vlan4k.member = vlanmc.member;
1536 vlan4k.untag = vlanmc.untag;
1538 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1539 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1543 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1545 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1546 return rtl8366_get_vlan_port_pvid(smi, port, val);
1549 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1551 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1552 return rtl8366_set_vlan_port_pvid(smi, port, val);
1555 static int rtl8366_reset_switch(struct switch_dev *dev)
1557 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1561 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1562 RTL8366_CHIP_CTRL_RESET_HW);
1565 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1568 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1570 } while (--timeout);
1573 printk("Timeout waiting for the switch to reset\n");
1577 return rtl8366s_reset_vlan(smi);
1580 static struct switch_attr rtl8366_globals[] = {
1582 .type = SWITCH_TYPE_INT,
1583 .name = "enable_vlan",
1584 .description = "Enable VLAN mode",
1585 .set = rtl8366_set_vlan,
1586 .get = rtl8366_get_vlan,
1591 .type = SWITCH_TYPE_INT,
1592 .name = "enable_vlan4k",
1593 .description = "Enable VLAN 4K mode",
1594 .set = rtl8366_set_vlan,
1595 .get = rtl8366_get_vlan,
1600 .type = SWITCH_TYPE_INT,
1601 .name = "reset_mibs",
1602 .description = "Reset all MIB counters",
1603 .set = rtl8366_global_reset_mibs,
1608 .type = SWITCH_TYPE_INT,
1609 .name = "blinkrate",
1610 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1611 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1612 .set = rtl8366_global_set_blinkrate,
1613 .get = rtl8366_global_get_blinkrate,
1618 static struct switch_attr rtl8366_port[] = {
1620 .type = SWITCH_TYPE_STRING,
1622 .description = "Get port link information",
1625 .get = rtl8366_attr_get_port_link
1628 .type = SWITCH_TYPE_INT,
1629 .name = "reset_mib",
1630 .description = "Reset single port MIB counters",
1632 .set = rtl8366_reset_port_mibs,
1636 .type = SWITCH_TYPE_STRING,
1638 .description = "Get MIB counters for port",
1641 .get = rtl8366_get_port_mib
1644 .type = SWITCH_TYPE_INT,
1646 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1648 .set = rtl8366_set_port_led,
1649 .get = rtl8366_get_port_led
1653 static struct switch_attr rtl8366_vlan[] = {
1655 .type = SWITCH_TYPE_STRING,
1657 .description = "Get vlan information",
1660 .get = rtl8366_attr_get_vlan_info
1666 static struct switch_dev rtldev = {
1668 .cpu_port = RTL8366_PORT_NUM_CPU,
1669 .ports = RTL8366_NUM_PORTS,
1670 .vlans = RTL8366_NUM_VLANS,
1672 .attr = rtl8366_globals,
1673 .n_attr = ARRAY_SIZE(rtl8366_globals),
1676 .attr = rtl8366_port,
1677 .n_attr = ARRAY_SIZE(rtl8366_port),
1680 .attr = rtl8366_vlan,
1681 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1684 .get_vlan_ports = rtl8366_get_ports,
1685 .set_vlan_ports = rtl8366_set_ports,
1686 .get_port_pvid = rtl8366_get_port_pvid,
1687 .set_port_pvid = rtl8366_set_port_pvid,
1688 .reset_switch = rtl8366_reset_switch,
1691 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1693 struct switch_dev *dev = &smi->dev;
1696 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1698 dev->devname = dev_name(&smi->pdev->dev);
1700 err = register_switch(dev, NULL);
1702 dev_err(&smi->pdev->dev, "switch registration failed\n");
1707 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1709 unregister_switch(&smi->dev);
1712 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1714 struct rtl8366_smi *smi = bus->priv;
1718 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1725 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1728 struct rtl8366_smi *smi = bus->priv;
1732 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1734 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1739 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1744 smi->mii_bus = mdiobus_alloc();
1745 if (smi->mii_bus == NULL) {
1750 spin_lock_init(&smi->lock);
1751 smi->mii_bus->priv = (void *) smi;
1752 smi->mii_bus->name = "rtl8366-smi";
1753 smi->mii_bus->read = rtl8366_smi_mii_read;
1754 smi->mii_bus->write = rtl8366_smi_mii_write;
1755 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1756 dev_name(&smi->pdev->dev));
1757 smi->mii_bus->parent = &smi->pdev->dev;
1758 smi->mii_bus->phy_mask = ~(0x1f);
1759 smi->mii_bus->irq = smi->mii_irq;
1760 for (i = 0; i < PHY_MAX_ADDR; i++)
1761 smi->mii_irq[i] = PHY_POLL;
1763 ret = mdiobus_register(smi->mii_bus);
1770 mdiobus_free(smi->mii_bus);
1775 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1777 mdiobus_unregister(smi->mii_bus);
1778 mdiobus_free(smi->mii_bus);
1781 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1783 return (bus->read == rtl8366_smi_mii_read &&
1784 bus->write == rtl8366_smi_mii_write);
1787 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1793 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1795 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1800 case RTL8366S_CHIP_ID_8366:
1803 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1807 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1810 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1814 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1815 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1817 rtl8366_debugfs_init(smi);
1822 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1824 static int rtl8366_smi_version_printed;
1825 struct rtl8366_smi_platform_data *pdata;
1826 struct rtl8366_smi *smi;
1829 if (!rtl8366_smi_version_printed++)
1830 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1831 " version " RTL8366_SMI_DRIVER_VER"\n");
1833 pdata = pdev->dev.platform_data;
1835 dev_err(&pdev->dev, "no platform data specified\n");
1840 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1842 dev_err(&pdev->dev, "no memory for private data\n");
1847 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1849 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1850 pdata->gpio_sda, err);
1854 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1856 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1857 pdata->gpio_sck, err);
1863 spin_lock_init(&smi->lock);
1865 platform_set_drvdata(pdev, smi);
1867 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1868 pdata->gpio_sda, pdata->gpio_sck);
1870 err = rtl8366_smi_setup(smi);
1872 goto err_clear_drvdata;
1874 err = rtl8366_smi_mii_init(smi);
1876 goto err_clear_drvdata;
1878 err = rtl8366_smi_switch_init(smi);
1880 goto err_mii_cleanup;
1885 rtl8366_smi_mii_cleanup(smi);
1887 platform_set_drvdata(pdev, NULL);
1888 gpio_free(pdata->gpio_sck);
1890 gpio_free(pdata->gpio_sda);
1897 int rtl8366_phy_config_init(struct phy_device *phydev)
1899 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1905 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1910 static struct phy_driver rtl8366_smi_phy_driver = {
1911 .phy_id = 0x001cc960,
1912 .name = "Realtek RTL8366",
1913 .phy_id_mask = 0x1ffffff0,
1914 .features = PHY_GBIT_FEATURES,
1915 .config_aneg = rtl8366_phy_config_aneg,
1916 .config_init = rtl8366_phy_config_init,
1917 .read_status = genphy_read_status,
1919 .owner = THIS_MODULE,
1923 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1925 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1928 struct rtl8366_smi_platform_data *pdata;
1930 pdata = pdev->dev.platform_data;
1932 rtl8366_smi_switch_cleanup(smi);
1933 rtl8366_debugfs_remove(smi);
1934 rtl8366_smi_mii_cleanup(smi);
1935 platform_set_drvdata(pdev, NULL);
1936 gpio_free(pdata->gpio_sck);
1937 gpio_free(pdata->gpio_sda);
1944 static struct platform_driver rtl8366_smi_driver = {
1946 .name = RTL8366_SMI_DRIVER_NAME,
1947 .owner = THIS_MODULE,
1949 .probe = rtl8366_smi_probe,
1950 .remove = __devexit_p(rtl8366_smi_remove),
1953 static int __init rtl8366_smi_init(void)
1956 ret = platform_driver_register(&rtl8366_smi_driver);
1960 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1962 goto err_platform_unregister;
1966 err_platform_unregister:
1967 platform_driver_unregister(&rtl8366_smi_driver);
1970 module_init(rtl8366_smi_init);
1972 static void __exit rtl8366_smi_exit(void)
1974 phy_driver_unregister(&rtl8366_smi_phy_driver);
1975 platform_driver_unregister(&rtl8366_smi_driver);
1977 module_exit(rtl8366_smi_exit);
1979 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1980 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1981 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1982 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1983 MODULE_LICENSE("GPL v2");
1984 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);