target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/cache.h>
  15 #include "ag71xx.h"
  16
  17 #define AG71XX_DEFAULT_MSG_ENABLE       \
  18         ( NETIF_MSG_DRV                 \
  19         | NETIF_MSG_PROBE               \
  20         | NETIF_MSG_LINK                \
  21         | NETIF_MSG_TIMER               \
  22         | NETIF_MSG_IFDOWN              \
  23         | NETIF_MSG_IFUP                \
  24         | NETIF_MSG_RX_ERR              \
  25         | NETIF_MSG_TX_ERR )
  26
  27 static int ag71xx_msg_level = -1;
  28
  29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  31
  32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  33 {
  34         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  35                 ag->dev->name,
  36                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  38                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  39
  40         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  41                 ag->dev->name,
  42                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  44                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  45 }
  46
  47 static void ag71xx_dump_regs(struct ag71xx *ag)
  48 {
  49         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  50                 ag->dev->name,
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  55                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  56         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  57                 ag->dev->name,
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  60                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  61         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  62                 ag->dev->name,
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  65                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  66         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  67                 ag->dev->name,
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  70                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  71 }
  72
  73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  74 {
  75         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  76                 ag->dev->name, label, intr,
  77                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  78                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  79                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  80                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  81                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  82                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  83 }
  84
  85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  86 {
  87         kfree(ring->buf);
  88
  89         if (ring->descs_cpu)
  90                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  91                                   ring->descs_cpu, ring->descs_dma);
  92 }
  93
  94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  95 {
  96         int err;
  97         int i;
  98
  99         ring->desc_size = sizeof(struct ag71xx_desc);
 100         if (ring->desc_size % cache_line_size()) {
 101                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 102                         ring, ring->desc_size,
 103                         roundup(ring->desc_size, cache_line_size()));
 104                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 105         }
 106
 107         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 108                                              &ring->descs_dma, GFP_ATOMIC);
 109         if (!ring->descs_cpu) {
 110                 err = -ENOMEM;
 111                 goto err;
 112         }
 113
 114         ring->size = size;
 115
 116         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 117         if (!ring->buf) {
 118                 err = -ENOMEM;
 119                 goto err;
 120         }
 121
 122         for (i = 0; i < size; i++) {
 123                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
 124                 DBG("ag71xx: ring %p, desc %d at %p\n",
 125                         ring, i, ring->buf[i].desc);
 126         }
 127
 128         return 0;
 129
 130  err:
 131         return err;
 132 }
 133
 134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 135 {
 136         struct ag71xx_ring *ring = &ag->tx_ring;
 137         struct net_device *dev = ag->dev;
 138
 139         while (ring->curr != ring->dirty) {
 140                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 141
 142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 143                         ring->buf[i].desc->ctrl = 0;
 144                         dev->stats.tx_errors++;
 145                 }
 146
 147                 if (ring->buf[i].skb)
 148                         dev_kfree_skb_any(ring->buf[i].skb);
 149
 150                 ring->buf[i].skb = NULL;
 151
 152                 ring->dirty++;
 153         }
 154
 155         /* flush descriptors */
 156         wmb();
 157
 158 }
 159
 160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 161 {
 162         struct ag71xx_ring *ring = &ag->tx_ring;
 163         int i;
 164
 165         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 166                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 167                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 168
 169                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 170                 ring->buf[i].skb = NULL;
 171         }
 172
 173         /* flush descriptors */
 174         wmb();
 175
 176         ring->curr = 0;
 177         ring->dirty = 0;
 178 }
 179
 180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 181 {
 182         struct ag71xx_ring *ring = &ag->rx_ring;
 183         int i;
 184
 185         if (!ring->buf)
 186                 return;
 187
 188         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 189                 if (ring->buf[i].skb)
 190                         kfree_skb(ring->buf[i].skb);
 191
 192 }
 193
 194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 195 {
 196         struct ag71xx_ring *ring = &ag->rx_ring;
 197         unsigned int i;
 198         int ret;
 199
 200         ret = 0;
 201         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 202                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 203                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 204
 205                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 206                         ring->buf[i].desc,
 207                         ring->buf[i].desc->next);
 208         }
 209
 210         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 211                 struct sk_buff *skb;
 212
 213                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
 214                 if (!skb) {
 215                         ret = -ENOMEM;
 216                         break;
 217                 }
 218
 219                 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
 220                                 DMA_FROM_DEVICE);
 221
 222                 skb->dev = ag->dev;
 223                 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 224
 225                 ring->buf[i].skb = skb;
 226                 ring->buf[i].desc->data = virt_to_phys(skb->data);
 227                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 228         }
 229
 230         /* flush descriptors */
 231         wmb();
 232
 233         ring->curr = 0;
 234         ring->dirty = 0;
 235
 236         return ret;
 237 }
 238
 239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 240 {
 241         struct ag71xx_ring *ring = &ag->rx_ring;
 242         unsigned int count;
 243
 244         count = 0;
 245         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 246                 unsigned int i;
 247
 248                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 249
 250                 if (ring->buf[i].skb == NULL) {
 251                         struct sk_buff *skb;
 252
 253                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
 254                         if (skb == NULL)
 255                                 break;
 256
 257                         dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
 258                                         DMA_FROM_DEVICE);
 259
 260                         skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 261                         skb->dev = ag->dev;
 262
 263                         ring->buf[i].skb = skb;
 264                         ring->buf[i].desc->data = virt_to_phys(skb->data);
 265                 }
 266
 267                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 268                 count++;
 269         }
 270
 271         /* flush descriptors */
 272         wmb();
 273
 274         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 275
 276         return count;
 277 }
 278
 279 static int ag71xx_rings_init(struct ag71xx *ag)
 280 {
 281         int ret;
 282
 283         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 284         if (ret)
 285                 return ret;
 286
 287         ag71xx_ring_tx_init(ag);
 288
 289         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 290         if (ret)
 291                 return ret;
 292
 293         ret = ag71xx_ring_rx_init(ag);
 294         return ret;
 295 }
 296
 297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 298 {
 299         ag71xx_ring_rx_clean(ag);
 300         ag71xx_ring_free(&ag->rx_ring);
 301
 302         ag71xx_ring_tx_clean(ag);
 303         ag71xx_ring_free(&ag->tx_ring);
 304 }
 305
 306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 307 {
 308         u32 t;
 309
 310         t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
 311           | (((u32) mac[2]) << 8) | ((u32) mac[3]);
 312
 313         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 314
 315         t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
 316         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 317 }
 318
 319 static void ag71xx_dma_reset(struct ag71xx *ag)
 320 {
 321         u32 val;
 322         int i;
 323
 324         ag71xx_dump_dma_regs(ag);
 325
 326         /* stop RX and TX */
 327         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 328         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 329
 330         /* clear descriptor addresses */
 331         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
 332         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
 333
 334         /* clear pending RX/TX interrupts */
 335         for (i = 0; i < 256; i++) {
 336                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 337                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 338         }
 339
 340         /* clear pending errors */
 341         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 342         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 343
 344         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 345         if (val)
 346                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 347                         ag->dev->name, val);
 348
 349         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 350
 351         /* mask out reserved bits */
 352         val &= ~0xff000000;
 353
 354         if (val)
 355                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 356                         ag->dev->name, val);
 357
 358         ag71xx_dump_dma_regs(ag);
 359 }
 360
 361 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 362                          MAC_CFG1_SRX | MAC_CFG1_STX)
 363
 364 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 365
 366 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 367                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 368                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 369                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 370                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 371                          FIFO_CFG4_VT)
 372
 373 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 374                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 375                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 376                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 377                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 378                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 379
 380 static void ag71xx_hw_init(struct ag71xx *ag)
 381 {
 382         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 383
 384         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 385         udelay(20);
 386
 387         ar71xx_device_stop(pdata->reset_bit);
 388         mdelay(100);
 389         ar71xx_device_start(pdata->reset_bit);
 390         mdelay(100);
 391
 392         /* setup MAC configuration registers */
 393         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 394         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 395                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 396
 397         /* setup max frame length */
 398         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 399
 400         /* setup MII interface type */
 401         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 402
 403         /* setup FIFO configuration registers */
 404         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 405         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 406         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 407         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 408         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 409
 410         ag71xx_dma_reset(ag);
 411 }
 412
 413 static void ag71xx_hw_start(struct ag71xx *ag)
 414 {
 415         /* start RX engine */
 416         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 417
 418         /* enable interrupts */
 419         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 420 }
 421
 422 static void ag71xx_hw_stop(struct ag71xx *ag)
 423 {
 424         /* disable all interrupts */
 425         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 426
 427         ag71xx_dma_reset(ag);
 428 }
 429
 430 static int ag71xx_open(struct net_device *dev)
 431 {
 432         struct ag71xx *ag = netdev_priv(dev);
 433         int ret;
 434
 435         ret = ag71xx_rings_init(ag);
 436         if (ret)
 437                 goto err;
 438
 439         napi_enable(&ag->napi);
 440
 441         netif_carrier_off(dev);
 442         ag71xx_phy_start(ag);
 443
 444         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 445         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 446
 447         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 448
 449         ag71xx_hw_start(ag);
 450
 451         netif_start_queue(dev);
 452
 453         return 0;
 454
 455  err:
 456         ag71xx_rings_cleanup(ag);
 457         return ret;
 458 }
 459
 460 static int ag71xx_stop(struct net_device *dev)
 461 {
 462         struct ag71xx *ag = netdev_priv(dev);
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&ag->lock, flags);
 466
 467         netif_stop_queue(dev);
 468
 469         ag71xx_hw_stop(ag);
 470
 471         netif_carrier_off(dev);
 472         ag71xx_phy_stop(ag);
 473
 474         napi_disable(&ag->napi);
 475         del_timer_sync(&ag->oom_timer);
 476
 477         spin_unlock_irqrestore(&ag->lock, flags);
 478
 479         ag71xx_rings_cleanup(ag);
 480
 481         return 0;
 482 }
 483
 484 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
 485 {
 486         struct ag71xx *ag = netdev_priv(dev);
 487         struct ag71xx_ring *ring = &ag->tx_ring;
 488         struct ag71xx_desc *desc;
 489         int i;
 490
 491         i = ring->curr % AG71XX_TX_RING_SIZE;
 492         desc = ring->buf[i].desc;
 493
 494         if (!ag71xx_desc_empty(desc))
 495                 goto err_drop;
 496
 497         ag71xx_add_ar8216_header(ag, skb);
 498
 499         if (skb->len <= 0) {
 500                 DBG("%s: packet len is too small\n", ag->dev->name);
 501                 goto err_drop;
 502         }
 503
 504         dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
 505
 506         ring->buf[i].skb = skb;
 507
 508         /* setup descriptor fields */
 509         desc->data = virt_to_phys(skb->data);
 510         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 511
 512         /* flush descriptor */
 513         wmb();
 514
 515         ring->curr++;
 516         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 517                 DBG("%s: tx queue full\n", ag->dev->name);
 518                 netif_stop_queue(dev);
 519         }
 520
 521         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 522
 523         /* enable TX engine */
 524         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 525
 526         dev->trans_start = jiffies;
 527
 528         return 0;
 529
 530  err_drop:
 531         dev->stats.tx_dropped++;
 532
 533         dev_kfree_skb(skb);
 534         return 0;
 535 }
 536
 537 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 538 {
 539         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
 540         struct ag71xx *ag = netdev_priv(dev);
 541         int ret;
 542
 543         switch (cmd) {
 544         case SIOCETHTOOL:
 545                 if (ag->phy_dev == NULL)
 546                         break;
 547
 548                 spin_lock_irq(&ag->lock);
 549                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 550                 spin_unlock_irq(&ag->lock);
 551                 return ret;
 552
 553         case SIOCSIFHWADDR:
 554                 if (copy_from_user
 555                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 556                         return -EFAULT;
 557                 return 0;
 558
 559         case SIOCGIFHWADDR:
 560                 if (copy_to_user
 561                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 562                         return -EFAULT;
 563                 return 0;
 564
 565         case SIOCGMIIPHY:
 566         case SIOCGMIIREG:
 567         case SIOCSMIIREG:
 568                 if (ag->phy_dev == NULL)
 569                         break;
 570
 571                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
 572
 573         default:
 574                 break;
 575         }
 576
 577         return -EOPNOTSUPP;
 578 }
 579
 580 static void ag71xx_oom_timer_handler(unsigned long data)
 581 {
 582         struct net_device *dev = (struct net_device *) data;
 583         struct ag71xx *ag = netdev_priv(dev);
 584
 585         netif_rx_schedule(dev, &ag->napi);
 586 }
 587
 588 static void ag71xx_tx_timeout(struct net_device *dev)
 589 {
 590         struct ag71xx *ag = netdev_priv(dev);
 591
 592         if (netif_msg_tx_err(ag))
 593                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 594
 595         schedule_work(&ag->restart_work);
 596 }
 597
 598 static void ag71xx_restart_work_func(struct work_struct *work)
 599 {
 600         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 601
 602         ag71xx_stop(ag->dev);
 603         ag71xx_open(ag->dev);
 604 }
 605
 606 static void ag71xx_tx_packets(struct ag71xx *ag)
 607 {
 608         struct ag71xx_ring *ring = &ag->tx_ring;
 609         unsigned int sent;
 610
 611         DBG("%s: processing TX ring\n", ag->dev->name);
 612
 613         sent = 0;
 614         while (ring->dirty != ring->curr) {
 615                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 616                 struct ag71xx_desc *desc = ring->buf[i].desc;
 617                 struct sk_buff *skb = ring->buf[i].skb;
 618
 619                 if (!ag71xx_desc_empty(desc))
 620                         break;
 621
 622                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 623
 624                 ag->dev->stats.tx_bytes += skb->len;
 625                 ag->dev->stats.tx_packets++;
 626
 627                 dev_kfree_skb_any(skb);
 628                 ring->buf[i].skb = NULL;
 629
 630                 ring->dirty++;
 631                 sent++;
 632         }
 633
 634         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 635
 636         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 637                 netif_wake_queue(ag->dev);
 638
 639 }
 640
 641 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 642 {
 643         struct net_device *dev = ag->dev;
 644         struct ag71xx_ring *ring = &ag->rx_ring;
 645         int done = 0;
 646
 647         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 648                         dev->name, limit, ring->curr, ring->dirty);
 649
 650         while (done < limit) {
 651                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 652                 struct ag71xx_desc *desc = ring->buf[i].desc;
 653                 struct sk_buff *skb;
 654                 int pktlen;
 655
 656                 if (ag71xx_desc_empty(desc))
 657                         break;
 658
 659                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 660                         ag71xx_assert(0);
 661                         break;
 662                 }
 663
 664                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 665
 666                 skb = ring->buf[i].skb;
 667                 pktlen = ag71xx_desc_pktlen(desc);
 668                 pktlen -= ETH_FCS_LEN;
 669
 670                 skb_put(skb, pktlen);
 671
 672                 skb->dev = dev;
 673                 skb->ip_summed = CHECKSUM_NONE;
 674
 675                 dev->last_rx = jiffies;
 676                 dev->stats.rx_packets++;
 677                 dev->stats.rx_bytes += pktlen;
 678
 679                 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
 680                         dev->stats.rx_dropped++;
 681                         kfree_skb(skb);
 682                 } else {
 683                         skb->protocol = eth_type_trans(skb, dev);
 684                         netif_receive_skb(skb);
 685                 }
 686
 687                 ring->buf[i].skb = NULL;
 688                 done++;
 689
 690                 ring->curr++;
 691         }
 692
 693         ag71xx_ring_rx_refill(ag);
 694
 695         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 696                 dev->name, ring->curr, ring->dirty, done);
 697
 698         return done;
 699 }
 700
 701 static int ag71xx_poll(struct napi_struct *napi, int limit)
 702 {
 703         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 704         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 705         struct net_device *dev = ag->dev;
 706         struct ag71xx_ring *rx_ring;
 707         unsigned long flags;
 708         u32 status;
 709         int done;
 710
 711         pdata->ddr_flush();
 712         ag71xx_tx_packets(ag);
 713
 714         DBG("%s: processing RX ring\n", dev->name);
 715         done = ag71xx_rx_packets(ag, limit);
 716
 717         rx_ring = &ag->rx_ring;
 718         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 719                 goto oom;
 720
 721         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 722         if (unlikely(status & RX_STATUS_OF)) {
 723                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 724                 dev->stats.rx_fifo_errors++;
 725
 726                 /* restart RX */
 727                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 728         }
 729
 730         if (done < limit) {
 731                 if (status & RX_STATUS_PR)
 732                         goto more;
 733
 734                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 735                 if (status & TX_STATUS_PS)
 736                         goto more;
 737
 738                 DBG("%s: disable polling mode, done=%d, limit=%d\n",
 739                         dev->name, done, limit);
 740
 741                 netif_rx_complete(dev, napi);
 742
 743                 /* enable interrupts */
 744                 spin_lock_irqsave(&ag->lock, flags);
 745                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 746                 spin_unlock_irqrestore(&ag->lock, flags);
 747                 return done;
 748         }
 749
 750  more:
 751         DBG("%s: stay in polling mode, done=%d, limit=%d\n",
 752                         dev->name, done, limit);
 753         return done;
 754
 755  oom:
 756         if (netif_msg_rx_err(ag))
 757                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 758
 759         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 760         netif_rx_complete(dev, napi);
 761         return 0;
 762 }
 763
 764 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 765 {
 766         struct net_device *dev = dev_id;
 767         struct ag71xx *ag = netdev_priv(dev);
 768         u32 status;
 769
 770         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 771         ag71xx_dump_intr(ag, "raw", status);
 772
 773         if (unlikely(!status))
 774                 return IRQ_NONE;
 775
 776         if (unlikely(status & AG71XX_INT_ERR)) {
 777                 if (status & AG71XX_INT_TX_BE) {
 778                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 779                         dev_err(&dev->dev, "TX BUS error\n");
 780                 }
 781                 if (status & AG71XX_INT_RX_BE) {
 782                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 783                         dev_err(&dev->dev, "RX BUS error\n");
 784                 }
 785         }
 786
 787         if (likely(status & AG71XX_INT_POLL)) {
 788                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
 789                 DBG("%s: enable polling mode\n", dev->name);
 790                 netif_rx_schedule(dev, &ag->napi);
 791         }
 792
 793         return IRQ_HANDLED;
 794 }
 795
 796 static void ag71xx_set_multicast_list(struct net_device *dev)
 797 {
 798         /* TODO */
 799 }
 800
 801 static int __init ag71xx_probe(struct platform_device *pdev)
 802 {
 803         struct net_device *dev;
 804         struct resource *res;
 805         struct ag71xx *ag;
 806         struct ag71xx_platform_data *pdata;
 807         int err;
 808
 809         pdata = pdev->dev.platform_data;
 810         if (!pdata) {
 811                 dev_err(&pdev->dev, "no platform data specified\n");
 812                 err = -ENXIO;
 813                 goto err_out;
 814         }
 815
 816         dev = alloc_etherdev(sizeof(*ag));
 817         if (!dev) {
 818                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
 819                 err = -ENOMEM;
 820                 goto err_out;
 821         }
 822
 823         SET_NETDEV_DEV(dev, &pdev->dev);
 824
 825         ag = netdev_priv(dev);
 826         ag->pdev = pdev;
 827         ag->dev = dev;
 828         ag->mii_bus = ag71xx_mdio_bus->mii_bus;
 829         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
 830                                         AG71XX_DEFAULT_MSG_ENABLE);
 831         spin_lock_init(&ag->lock);
 832
 833         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
 834         if (!res) {
 835                 dev_err(&pdev->dev, "no mac_base resource found\n");
 836                 err = -ENXIO;
 837                 goto err_out;
 838         }
 839
 840         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
 841         if (!ag->mac_base) {
 842                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
 843                 err = -ENOMEM;
 844                 goto err_free_dev;
 845         }
 846
 847         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
 848         if (!res) {
 849                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
 850                 err = -ENXIO;
 851                 goto err_unmap_base;
 852         }
 853
 854         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
 855         if (!ag->mii_ctrl) {
 856                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
 857                 err = -ENOMEM;
 858                 goto err_unmap_base;
 859         }
 860
 861         dev->irq = platform_get_irq(pdev, 0);
 862         err = request_irq(dev->irq, ag71xx_interrupt,
 863                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
 864                           dev->name, dev);
 865         if (err) {
 866                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
 867                 goto err_unmap_mii_ctrl;
 868         }
 869
 870         dev->base_addr = (unsigned long)ag->mac_base;
 871         dev->open = ag71xx_open;
 872         dev->stop = ag71xx_stop;
 873         dev->hard_start_xmit = ag71xx_hard_start_xmit;
 874         dev->set_multicast_list = ag71xx_set_multicast_list;
 875         dev->do_ioctl = ag71xx_do_ioctl;
 876         dev->ethtool_ops = &ag71xx_ethtool_ops;
 877
 878         dev->tx_timeout = ag71xx_tx_timeout;
 879         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
 880
 881         init_timer(&ag->oom_timer);
 882         ag->oom_timer.data = (unsigned long) dev;
 883         ag->oom_timer.function = ag71xx_oom_timer_handler;
 884
 885         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
 886
 887         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 888
 889         err = register_netdev(dev);
 890         if (err) {
 891                 dev_err(&pdev->dev, "unable to register net device\n");
 892                 goto err_free_irq;
 893         }
 894
 895         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
 896                dev->name, dev->base_addr, dev->irq);
 897
 898         ag71xx_dump_regs(ag);
 899
 900         ag71xx_hw_init(ag);
 901
 902         ag71xx_dump_regs(ag);
 903
 904         /* Reset the mdio bus explicitly */
 905         if (ag->mii_bus) {
 906                 mutex_lock(&ag->mii_bus->mdio_lock);
 907                 ag->mii_bus->reset(ag->mii_bus);
 908                 mutex_unlock(&ag->mii_bus->mdio_lock);
 909         }
 910
 911         err = ag71xx_phy_connect(ag);
 912         if (err)
 913                 goto err_unregister_netdev;
 914
 915         platform_set_drvdata(pdev, dev);
 916
 917         return 0;
 918
 919  err_unregister_netdev:
 920         unregister_netdev(dev);
 921  err_free_irq:
 922         free_irq(dev->irq, dev);
 923  err_unmap_mii_ctrl:
 924         iounmap(ag->mii_ctrl);
 925  err_unmap_base:
 926         iounmap(ag->mac_base);
 927  err_free_dev:
 928         kfree(dev);
 929  err_out:
 930         platform_set_drvdata(pdev, NULL);
 931         return err;
 932 }
 933
 934 static int __exit ag71xx_remove(struct platform_device *pdev)
 935 {
 936         struct net_device *dev = platform_get_drvdata(pdev);
 937
 938         if (dev) {
 939                 struct ag71xx *ag = netdev_priv(dev);
 940
 941                 ag71xx_phy_disconnect(ag);
 942                 unregister_netdev(dev);
 943                 free_irq(dev->irq, dev);
 944                 iounmap(ag->mii_ctrl);
 945                 iounmap(ag->mac_base);
 946                 kfree(dev);
 947                 platform_set_drvdata(pdev, NULL);
 948         }
 949
 950         return 0;
 951 }
 952
 953 static struct platform_driver ag71xx_driver = {
 954         .probe          = ag71xx_probe,
 955         .remove         = __exit_p(ag71xx_remove),
 956         .driver = {
 957                 .name   = AG71XX_DRV_NAME,
 958         }
 959 };
 960
 961 static int __init ag71xx_module_init(void)
 962 {
 963         int ret;
 964
 965         ret = ag71xx_mdio_driver_init();
 966         if (ret)
 967                 goto err_out;
 968
 969         ret = platform_driver_register(&ag71xx_driver);
 970         if (ret)
 971                 goto err_mdio_exit;
 972
 973         return 0;
 974
 975  err_mdio_exit:
 976         ag71xx_mdio_driver_exit();
 977  err_out:
 978         return ret;
 979 }
 980
 981 static void __exit ag71xx_module_exit(void)
 982 {
 983         platform_driver_unregister(&ag71xx_driver);
 984         ag71xx_mdio_driver_exit();
 985 }
 986
 987 module_init(ag71xx_module_init);
 988 module_exit(ag71xx_module_exit);
 989
 990 MODULE_VERSION(AG71XX_DRV_VERSION);
 991 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 992 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
 993 MODULE_LICENSE("GPL v2");
 994 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);