target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         ( NETIF_MSG_DRV                 \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR )
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113         ring->size = size;
 114
 115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 116         if (!ring->buf) {
 117                 err = -ENOMEM;
 118                 goto err;
 119         }
 120
 121         for (i = 0; i < size; i++) {
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129  err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137
 138         while (ring->curr != ring->dirty) {
 139                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 140
 141                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 142                         ring->buf[i].desc->ctrl = 0;
 143                         dev->stats.tx_errors++;
 144                 }
 145
 146                 if (ring->buf[i].skb)
 147                         dev_kfree_skb_any(ring->buf[i].skb);
 148
 149                 ring->buf[i].skb = NULL;
 150
 151                 ring->dirty++;
 152         }
 153
 154         /* flush descriptors */
 155         wmb();
 156
 157 }
 158
 159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 160 {
 161         struct ag71xx_ring *ring = &ag->tx_ring;
 162         int i;
 163
 164         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 165                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 166                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 167
 168                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 169                 ring->buf[i].skb = NULL;
 170         }
 171
 172         /* flush descriptors */
 173         wmb();
 174
 175         ring->curr = 0;
 176         ring->dirty = 0;
 177 }
 178
 179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         int i;
 183
 184         if (!ring->buf)
 185                 return;
 186
 187         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 188                 if (ring->buf[i].skb) {
 189                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 190                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 191                         kfree_skb(ring->buf[i].skb);
 192                 }
 193 }
 194
 195 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 196 {
 197         struct ag71xx_ring *ring = &ag->rx_ring;
 198         unsigned int i;
 199         int ret;
 200
 201         ret = 0;
 202         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 203                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 204                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 205
 206                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 207                         ring->buf[i].desc,
 208                         ring->buf[i].desc->next);
 209         }
 210
 211         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 212                 struct sk_buff *skb;
 213                 dma_addr_t dma_addr;
 214
 215                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + AG71XX_RX_PKT_RESERVE);
 216                 if (!skb) {
 217                         ret = -ENOMEM;
 218                         break;
 219                 }
 220
 221                 skb->dev = ag->dev;
 222                 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 223
 224                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 225                                           AG71XX_RX_PKT_SIZE,
 226                                           DMA_FROM_DEVICE);
 227                 ring->buf[i].skb = skb;
 228                 ring->buf[i].dma_addr = dma_addr;
 229                 ring->buf[i].desc->data = (u32) dma_addr;
 230                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 231         }
 232
 233         /* flush descriptors */
 234         wmb();
 235
 236         ring->curr = 0;
 237         ring->dirty = 0;
 238
 239         return ret;
 240 }
 241
 242 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 243 {
 244         struct ag71xx_ring *ring = &ag->rx_ring;
 245         unsigned int count;
 246
 247         count = 0;
 248         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 249                 unsigned int i;
 250
 251                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 252
 253                 if (ring->buf[i].skb == NULL) {
 254                         dma_addr_t dma_addr;
 255                         struct sk_buff *skb;
 256
 257                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE +
 258                                             AG71XX_RX_PKT_RESERVE);
 259                         if (skb == NULL)
 260                                 break;
 261
 262                         skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
 263                         skb->dev = ag->dev;
 264
 265                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 266                                                   AG71XX_RX_PKT_SIZE,
 267                                                   DMA_FROM_DEVICE);
 268
 269                         ring->buf[i].skb = skb;
 270                         ring->buf[i].dma_addr = dma_addr;
 271                         ring->buf[i].desc->data = (u32) dma_addr;
 272                 }
 273
 274                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 275                 count++;
 276         }
 277
 278         /* flush descriptors */
 279         wmb();
 280
 281         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 282
 283         return count;
 284 }
 285
 286 static int ag71xx_rings_init(struct ag71xx *ag)
 287 {
 288         int ret;
 289
 290         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 291         if (ret)
 292                 return ret;
 293
 294         ag71xx_ring_tx_init(ag);
 295
 296         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 297         if (ret)
 298                 return ret;
 299
 300         ret = ag71xx_ring_rx_init(ag);
 301         return ret;
 302 }
 303
 304 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 305 {
 306         ag71xx_ring_rx_clean(ag);
 307         ag71xx_ring_free(&ag->rx_ring);
 308
 309         ag71xx_ring_tx_clean(ag);
 310         ag71xx_ring_free(&ag->tx_ring);
 311 }
 312
 313 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 314 {
 315         u32 t;
 316
 317         t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
 318           | (((u32) mac[2]) << 8) | ((u32) mac[3]);
 319
 320         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 321
 322         t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
 323         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 324 }
 325
 326 static void ag71xx_dma_reset(struct ag71xx *ag)
 327 {
 328         u32 val;
 329         int i;
 330
 331         ag71xx_dump_dma_regs(ag);
 332
 333         /* stop RX and TX */
 334         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 335         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 336
 337         /* clear descriptor addresses */
 338         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
 339         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
 340
 341         /* clear pending RX/TX interrupts */
 342         for (i = 0; i < 256; i++) {
 343                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 344                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 345         }
 346
 347         /* clear pending errors */
 348         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 349         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 350
 351         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 352         if (val)
 353                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 354                         ag->dev->name, val);
 355
 356         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 357
 358         /* mask out reserved bits */
 359         val &= ~0xff000000;
 360
 361         if (val)
 362                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 363                         ag->dev->name, val);
 364
 365         ag71xx_dump_dma_regs(ag);
 366 }
 367
 368 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 369                          MAC_CFG1_SRX | MAC_CFG1_STX)
 370
 371 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 372
 373 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 374                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 375                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 376                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 377                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 378                          FIFO_CFG4_VT)
 379
 380 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 381                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 382                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 383                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 384                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 385                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 386
 387 static void ag71xx_hw_init(struct ag71xx *ag)
 388 {
 389         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 390
 391         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 392         udelay(20);
 393
 394         ar71xx_device_stop(pdata->reset_bit);
 395         mdelay(100);
 396         ar71xx_device_start(pdata->reset_bit);
 397         mdelay(100);
 398
 399         /* setup MAC configuration registers */
 400         if (pdata->is_ar724x)
 401                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
 402                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
 403         else
 404                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 405
 406         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 407                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 408
 409         /* setup max frame length */
 410         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 411
 412         /* setup MII interface type */
 413         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 414
 415         /* setup FIFO configuration registers */
 416         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 417         if (pdata->is_ar724x) {
 418                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 419                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 420         } else {
 421                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 422                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 423         }
 424         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 425         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 426
 427         ag71xx_dma_reset(ag);
 428 }
 429
 430 static void ag71xx_hw_start(struct ag71xx *ag)
 431 {
 432         /* start RX engine */
 433         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 434
 435         /* enable interrupts */
 436         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 437 }
 438
 439 static void ag71xx_hw_stop(struct ag71xx *ag)
 440 {
 441         /* disable all interrupts */
 442         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 443
 444         ag71xx_dma_reset(ag);
 445 }
 446
 447 static int ag71xx_open(struct net_device *dev)
 448 {
 449         struct ag71xx *ag = netdev_priv(dev);
 450         int ret;
 451
 452         ret = ag71xx_rings_init(ag);
 453         if (ret)
 454                 goto err;
 455
 456         napi_enable(&ag->napi);
 457
 458         netif_carrier_off(dev);
 459         ag71xx_phy_start(ag);
 460
 461         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 462         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 463
 464         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 465
 466         ag71xx_hw_start(ag);
 467
 468         netif_start_queue(dev);
 469
 470         return 0;
 471
 472  err:
 473         ag71xx_rings_cleanup(ag);
 474         return ret;
 475 }
 476
 477 static int ag71xx_stop(struct net_device *dev)
 478 {
 479         struct ag71xx *ag = netdev_priv(dev);
 480         unsigned long flags;
 481
 482         spin_lock_irqsave(&ag->lock, flags);
 483
 484         netif_stop_queue(dev);
 485
 486         ag71xx_hw_stop(ag);
 487
 488         netif_carrier_off(dev);
 489         ag71xx_phy_stop(ag);
 490
 491         napi_disable(&ag->napi);
 492         del_timer_sync(&ag->oom_timer);
 493
 494         spin_unlock_irqrestore(&ag->lock, flags);
 495
 496         ag71xx_rings_cleanup(ag);
 497
 498         return 0;
 499 }
 500
 501 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 502                                           struct net_device *dev)
 503 {
 504         struct ag71xx *ag = netdev_priv(dev);
 505         struct ag71xx_ring *ring = &ag->tx_ring;
 506         struct ag71xx_desc *desc;
 507         dma_addr_t dma_addr;
 508         int i;
 509
 510         i = ring->curr % AG71XX_TX_RING_SIZE;
 511         desc = ring->buf[i].desc;
 512
 513         if (!ag71xx_desc_empty(desc))
 514                 goto err_drop;
 515
 516         ag71xx_add_ar8216_header(ag, skb);
 517
 518         if (skb->len <= 0) {
 519                 DBG("%s: packet len is too small\n", ag->dev->name);
 520                 goto err_drop;
 521         }
 522
 523         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 524                                   DMA_TO_DEVICE);
 525
 526         ring->buf[i].skb = skb;
 527
 528         /* setup descriptor fields */
 529         desc->data = (u32) dma_addr;
 530         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 531
 532         /* flush descriptor */
 533         wmb();
 534
 535         ring->curr++;
 536         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 537                 DBG("%s: tx queue full\n", ag->dev->name);
 538                 netif_stop_queue(dev);
 539         }
 540
 541         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 542
 543         /* enable TX engine */
 544         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 545
 546         return NETDEV_TX_OK;
 547
 548  err_drop:
 549         dev->stats.tx_dropped++;
 550
 551         dev_kfree_skb(skb);
 552         return NETDEV_TX_OK;
 553 }
 554
 555 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 556 {
 557         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
 558         struct ag71xx *ag = netdev_priv(dev);
 559         int ret;
 560
 561         switch (cmd) {
 562         case SIOCETHTOOL:
 563                 if (ag->phy_dev == NULL)
 564                         break;
 565
 566                 spin_lock_irq(&ag->lock);
 567                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 568                 spin_unlock_irq(&ag->lock);
 569                 return ret;
 570
 571         case SIOCSIFHWADDR:
 572                 if (copy_from_user
 573                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 574                         return -EFAULT;
 575                 return 0;
 576
 577         case SIOCGIFHWADDR:
 578                 if (copy_to_user
 579                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 580                         return -EFAULT;
 581                 return 0;
 582
 583         case SIOCGMIIPHY:
 584         case SIOCGMIIREG:
 585         case SIOCSMIIREG:
 586                 if (ag->phy_dev == NULL)
 587                         break;
 588
 589                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
 590
 591         default:
 592                 break;
 593         }
 594
 595         return -EOPNOTSUPP;
 596 }
 597
 598 static void ag71xx_oom_timer_handler(unsigned long data)
 599 {
 600         struct net_device *dev = (struct net_device *) data;
 601         struct ag71xx *ag = netdev_priv(dev);
 602
 603         napi_schedule(&ag->napi);
 604 }
 605
 606 static void ag71xx_tx_timeout(struct net_device *dev)
 607 {
 608         struct ag71xx *ag = netdev_priv(dev);
 609
 610         if (netif_msg_tx_err(ag))
 611                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 612
 613         schedule_work(&ag->restart_work);
 614 }
 615
 616 static void ag71xx_restart_work_func(struct work_struct *work)
 617 {
 618         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 619
 620         ag71xx_stop(ag->dev);
 621         ag71xx_open(ag->dev);
 622 }
 623
 624 static int ag71xx_tx_packets(struct ag71xx *ag)
 625 {
 626         struct ag71xx_ring *ring = &ag->tx_ring;
 627         int sent;
 628
 629         DBG("%s: processing TX ring\n", ag->dev->name);
 630
 631         sent = 0;
 632         while (ring->dirty != ring->curr) {
 633                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 634                 struct ag71xx_desc *desc = ring->buf[i].desc;
 635                 struct sk_buff *skb = ring->buf[i].skb;
 636
 637                 if (!ag71xx_desc_empty(desc))
 638                         break;
 639
 640                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 641
 642                 ag->dev->stats.tx_bytes += skb->len;
 643                 ag->dev->stats.tx_packets++;
 644
 645                 dev_kfree_skb_any(skb);
 646                 ring->buf[i].skb = NULL;
 647
 648                 ring->dirty++;
 649                 sent++;
 650         }
 651
 652         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 653
 654         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 655                 netif_wake_queue(ag->dev);
 656
 657         return sent;
 658 }
 659
 660 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 661 {
 662         struct net_device *dev = ag->dev;
 663         struct ag71xx_ring *ring = &ag->rx_ring;
 664         int done = 0;
 665
 666         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 667                         dev->name, limit, ring->curr, ring->dirty);
 668
 669         while (done < limit) {
 670                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 671                 struct ag71xx_desc *desc = ring->buf[i].desc;
 672                 struct sk_buff *skb;
 673                 int pktlen;
 674
 675                 if (ag71xx_desc_empty(desc))
 676                         break;
 677
 678                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 679                         ag71xx_assert(0);
 680                         break;
 681                 }
 682
 683                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 684
 685                 skb = ring->buf[i].skb;
 686                 pktlen = ag71xx_desc_pktlen(desc);
 687                 pktlen -= ETH_FCS_LEN;
 688
 689                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 690                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 691
 692                 skb_put(skb, pktlen);
 693
 694                 skb->dev = dev;
 695                 skb->ip_summed = CHECKSUM_NONE;
 696
 697                 dev->last_rx = jiffies;
 698                 dev->stats.rx_packets++;
 699                 dev->stats.rx_bytes += pktlen;
 700
 701                 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
 702                         dev->stats.rx_dropped++;
 703                         kfree_skb(skb);
 704                 } else {
 705                         skb->protocol = eth_type_trans(skb, dev);
 706                         netif_receive_skb(skb);
 707                 }
 708
 709                 ring->buf[i].skb = NULL;
 710                 done++;
 711
 712                 ring->curr++;
 713         }
 714
 715         ag71xx_ring_rx_refill(ag);
 716
 717         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 718                 dev->name, ring->curr, ring->dirty, done);
 719
 720         return done;
 721 }
 722
 723 static int ag71xx_poll(struct napi_struct *napi, int limit)
 724 {
 725         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 726         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 727         struct net_device *dev = ag->dev;
 728         struct ag71xx_ring *rx_ring;
 729         unsigned long flags;
 730         u32 status;
 731         int tx_done;
 732         int rx_done;
 733
 734         pdata->ddr_flush();
 735         tx_done = ag71xx_tx_packets(ag);
 736
 737         DBG("%s: processing RX ring\n", dev->name);
 738         rx_done = ag71xx_rx_packets(ag, limit);
 739
 740         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 741
 742         rx_ring = &ag->rx_ring;
 743         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 744                 goto oom;
 745
 746         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 747         if (unlikely(status & RX_STATUS_OF)) {
 748                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 749                 dev->stats.rx_fifo_errors++;
 750
 751                 /* restart RX */
 752                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 753         }
 754
 755         if (rx_done < limit) {
 756                 if (status & RX_STATUS_PR)
 757                         goto more;
 758
 759                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 760                 if (status & TX_STATUS_PS)
 761                         goto more;
 762
 763                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 764                         dev->name, rx_done, tx_done, limit);
 765
 766                 napi_complete(napi);
 767
 768                 /* enable interrupts */
 769                 spin_lock_irqsave(&ag->lock, flags);
 770                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 771                 spin_unlock_irqrestore(&ag->lock, flags);
 772                 return rx_done;
 773         }
 774
 775  more:
 776         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 777                         dev->name, rx_done, tx_done, limit);
 778         return rx_done;
 779
 780  oom:
 781         if (netif_msg_rx_err(ag))
 782                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 783
 784         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 785         napi_complete(napi);
 786         return 0;
 787 }
 788
 789 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 790 {
 791         struct net_device *dev = dev_id;
 792         struct ag71xx *ag = netdev_priv(dev);
 793         u32 status;
 794
 795         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 796         ag71xx_dump_intr(ag, "raw", status);
 797
 798         if (unlikely(!status))
 799                 return IRQ_NONE;
 800
 801         if (unlikely(status & AG71XX_INT_ERR)) {
 802                 if (status & AG71XX_INT_TX_BE) {
 803                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 804                         dev_err(&dev->dev, "TX BUS error\n");
 805                 }
 806                 if (status & AG71XX_INT_RX_BE) {
 807                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 808                         dev_err(&dev->dev, "RX BUS error\n");
 809                 }
 810         }
 811
 812         if (likely(status & AG71XX_INT_POLL)) {
 813                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
 814                 DBG("%s: enable polling mode\n", dev->name);
 815                 napi_schedule(&ag->napi);
 816         }
 817
 818         ag71xx_debugfs_update_int_stats(ag, status);
 819
 820         return IRQ_HANDLED;
 821 }
 822
 823 static void ag71xx_set_multicast_list(struct net_device *dev)
 824 {
 825         /* TODO */
 826 }
 827
 828 static const struct net_device_ops ag71xx_netdev_ops = {
 829         .ndo_open               = ag71xx_open,
 830         .ndo_stop               = ag71xx_stop,
 831         .ndo_start_xmit         = ag71xx_hard_start_xmit,
 832         .ndo_set_multicast_list = ag71xx_set_multicast_list,
 833         .ndo_do_ioctl           = ag71xx_do_ioctl,
 834         .ndo_tx_timeout         = ag71xx_tx_timeout,
 835         .ndo_change_mtu         = eth_change_mtu,
 836         .ndo_set_mac_address    = eth_mac_addr,
 837         .ndo_validate_addr      = eth_validate_addr,
 838 };
 839
 840 static int __init ag71xx_probe(struct platform_device *pdev)
 841 {
 842         struct net_device *dev;
 843         struct resource *res;
 844         struct ag71xx *ag;
 845         struct ag71xx_platform_data *pdata;
 846         int err;
 847
 848         pdata = pdev->dev.platform_data;
 849         if (!pdata) {
 850                 dev_err(&pdev->dev, "no platform data specified\n");
 851                 err = -ENXIO;
 852                 goto err_out;
 853         }
 854
 855         if (pdata->mii_bus_dev == NULL) {
 856                 dev_err(&pdev->dev, "no MII bus device specified\n");
 857                 err = -EINVAL;
 858                 goto err_out;
 859         }
 860
 861         dev = alloc_etherdev(sizeof(*ag));
 862         if (!dev) {
 863                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
 864                 err = -ENOMEM;
 865                 goto err_out;
 866         }
 867
 868         SET_NETDEV_DEV(dev, &pdev->dev);
 869
 870         ag = netdev_priv(dev);
 871         ag->pdev = pdev;
 872         ag->dev = dev;
 873         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
 874                                         AG71XX_DEFAULT_MSG_ENABLE);
 875         spin_lock_init(&ag->lock);
 876
 877         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
 878         if (!res) {
 879                 dev_err(&pdev->dev, "no mac_base resource found\n");
 880                 err = -ENXIO;
 881                 goto err_out;
 882         }
 883
 884         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
 885         if (!ag->mac_base) {
 886                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
 887                 err = -ENOMEM;
 888                 goto err_free_dev;
 889         }
 890
 891         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
 892         if (!res) {
 893                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
 894                 err = -ENXIO;
 895                 goto err_unmap_base;
 896         }
 897
 898         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
 899         if (!ag->mii_ctrl) {
 900                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
 901                 err = -ENOMEM;
 902                 goto err_unmap_base;
 903         }
 904
 905         dev->irq = platform_get_irq(pdev, 0);
 906         err = request_irq(dev->irq, ag71xx_interrupt,
 907                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
 908                           dev->name, dev);
 909         if (err) {
 910                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
 911                 goto err_unmap_mii_ctrl;
 912         }
 913
 914         dev->base_addr = (unsigned long)ag->mac_base;
 915         dev->netdev_ops = &ag71xx_netdev_ops;
 916         dev->ethtool_ops = &ag71xx_ethtool_ops;
 917
 918         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
 919
 920         init_timer(&ag->oom_timer);
 921         ag->oom_timer.data = (unsigned long) dev;
 922         ag->oom_timer.function = ag71xx_oom_timer_handler;
 923
 924         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
 925
 926         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 927
 928         err = register_netdev(dev);
 929         if (err) {
 930                 dev_err(&pdev->dev, "unable to register net device\n");
 931                 goto err_free_irq;
 932         }
 933
 934         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
 935                dev->name, dev->base_addr, dev->irq);
 936
 937         ag71xx_dump_regs(ag);
 938
 939         ag71xx_hw_init(ag);
 940
 941         ag71xx_dump_regs(ag);
 942
 943         err = ag71xx_phy_connect(ag);
 944         if (err)
 945                 goto err_unregister_netdev;
 946
 947         err = ag71xx_debugfs_init(ag);
 948         if (err)
 949                 goto err_phy_disconnect;
 950
 951         platform_set_drvdata(pdev, dev);
 952
 953         return 0;
 954
 955  err_phy_disconnect:
 956         ag71xx_phy_disconnect(ag);
 957  err_unregister_netdev:
 958         unregister_netdev(dev);
 959  err_free_irq:
 960         free_irq(dev->irq, dev);
 961  err_unmap_mii_ctrl:
 962         iounmap(ag->mii_ctrl);
 963  err_unmap_base:
 964         iounmap(ag->mac_base);
 965  err_free_dev:
 966         kfree(dev);
 967  err_out:
 968         platform_set_drvdata(pdev, NULL);
 969         return err;
 970 }
 971
 972 static int __exit ag71xx_remove(struct platform_device *pdev)
 973 {
 974         struct net_device *dev = platform_get_drvdata(pdev);
 975
 976         if (dev) {
 977                 struct ag71xx *ag = netdev_priv(dev);
 978
 979                 ag71xx_debugfs_exit(ag);
 980                 ag71xx_phy_disconnect(ag);
 981                 unregister_netdev(dev);
 982                 free_irq(dev->irq, dev);
 983                 iounmap(ag->mii_ctrl);
 984                 iounmap(ag->mac_base);
 985                 kfree(dev);
 986                 platform_set_drvdata(pdev, NULL);
 987         }
 988
 989         return 0;
 990 }
 991
 992 static struct platform_driver ag71xx_driver = {
 993         .probe          = ag71xx_probe,
 994         .remove         = __exit_p(ag71xx_remove),
 995         .driver = {
 996                 .name   = AG71XX_DRV_NAME,
 997         }
 998 };
 999
1000 static int __init ag71xx_module_init(void)
1001 {
1002         int ret;
1003
1004         ret = ag71xx_debugfs_root_init();
1005         if (ret)
1006                 goto err_out;
1007
1008         ret = ag71xx_mdio_driver_init();
1009         if (ret)
1010                 goto err_debugfs_exit;
1011
1012         ret = platform_driver_register(&ag71xx_driver);
1013         if (ret)
1014                 goto err_mdio_exit;
1015
1016         return 0;
1017
1018  err_mdio_exit:
1019         ag71xx_mdio_driver_exit();
1020  err_debugfs_exit:
1021         ag71xx_debugfs_root_exit();
1022  err_out:
1023         return ret;
1024 }
1025
1026 static void __exit ag71xx_module_exit(void)
1027 {
1028         platform_driver_unregister(&ag71xx_driver);
1029         ag71xx_mdio_driver_exit();
1030         ag71xx_debugfs_root_exit();
1031 }
1032
1033 module_init(ag71xx_module_init);
1034 module_exit(ag71xx_module_exit);
1035
1036 MODULE_VERSION(AG71XX_DRV_VERSION);
1037 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1038 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1039 MODULE_LICENSE("GPL v2");
1040 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);