2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/cache.h>
17 #define AG71XX_DEFAULT_MSG_ENABLE \
27 static int ag71xx_msg_level = -1;
29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
34 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
36 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
37 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
38 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
40 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
42 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
47 static void ag71xx_dump_regs(struct ag71xx *ag)
49 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
52 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
53 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
54 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
55 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
56 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
58 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
60 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
61 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
65 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
66 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
75 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
76 ag->dev->name, label, intr,
77 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
78 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
79 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
80 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
81 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
82 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
90 dma_free_coherent(NULL, ring->size * ring->desc_size,
91 ring->descs_cpu, ring->descs_dma);
94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
99 ring->desc_size = sizeof(struct ag71xx_desc);
100 if (ring->desc_size % cache_line_size()) {
101 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
102 ring, ring->desc_size,
103 roundup(ring->desc_size, cache_line_size()));
104 ring->desc_size = roundup(ring->desc_size, cache_line_size());
107 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
108 &ring->descs_dma, GFP_ATOMIC);
109 if (!ring->descs_cpu) {
116 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
122 for (i = 0; i < size; i++) {
123 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring, i, ring->buf[i].desc);
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 struct ag71xx_ring *ring = &ag->tx_ring;
137 struct net_device *dev = ag->dev;
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
147 if (ring->buf[i].skb)
148 dev_kfree_skb_any(ring->buf[i].skb);
150 ring->buf[i].skb = NULL;
155 /* flush descriptors */
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
162 struct ag71xx_ring *ring = &ag->tx_ring;
165 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
169 ring->buf[i].desc->ctrl = DESC_EMPTY;
170 ring->buf[i].skb = NULL;
173 /* flush descriptors */
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
182 struct ag71xx_ring *ring = &ag->rx_ring;
188 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189 if (ring->buf[i].skb)
190 kfree_skb(ring->buf[i].skb);
194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
196 struct ag71xx_ring *ring = &ag->rx_ring;
201 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
202 ring->buf[i].desc->next = (u32) (ring->descs_dma +
203 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
205 DBG("ag71xx: RX desc at %p, next is %08x\n",
207 ring->buf[i].desc->next);
210 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
213 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
219 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
223 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
225 ring->buf[i].skb = skb;
226 ring->buf[i].desc->data = virt_to_phys(skb->data);
227 ring->buf[i].desc->ctrl = DESC_EMPTY;
230 /* flush descriptors */
239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
241 struct ag71xx_ring *ring = &ag->rx_ring;
245 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
248 i = ring->dirty % AG71XX_RX_RING_SIZE;
250 if (ring->buf[i].skb == NULL) {
253 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
257 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
260 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
263 ring->buf[i].skb = skb;
264 ring->buf[i].desc->data = virt_to_phys(skb->data);
267 ring->buf[i].desc->ctrl = DESC_EMPTY;
271 /* flush descriptors */
274 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
279 static int ag71xx_rings_init(struct ag71xx *ag)
283 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
287 ag71xx_ring_tx_init(ag);
289 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
293 ret = ag71xx_ring_rx_init(ag);
297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
299 ag71xx_ring_rx_clean(ag);
300 ag71xx_ring_free(&ag->rx_ring);
302 ag71xx_ring_tx_clean(ag);
303 ag71xx_ring_free(&ag->tx_ring);
306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
310 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
311 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
313 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
315 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
316 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
319 static void ag71xx_dma_reset(struct ag71xx *ag)
324 ag71xx_dump_dma_regs(ag);
327 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
328 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
330 /* clear descriptor addresses */
331 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
332 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
334 /* clear pending RX/TX interrupts */
335 for (i = 0; i < 256; i++) {
336 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
337 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
340 /* clear pending errors */
341 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
342 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
344 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
346 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
349 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
351 /* mask out reserved bits */
355 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
358 ag71xx_dump_dma_regs(ag);
361 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
362 MAC_CFG1_SRX | MAC_CFG1_STX)
364 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
366 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
367 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
368 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
369 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
370 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
373 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
374 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
375 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
376 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
377 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
378 FIFO_CFG5_17 | FIFO_CFG5_SF)
380 static void ag71xx_hw_init(struct ag71xx *ag)
382 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
384 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
387 ar71xx_device_stop(pdata->reset_bit);
389 ar71xx_device_start(pdata->reset_bit);
392 /* setup MAC configuration registers */
393 if (pdata->is_ar724x)
394 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
395 MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
397 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
399 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
400 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
402 /* setup max frame length */
403 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
405 /* setup MII interface type */
406 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
408 /* setup FIFO configuration registers */
409 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
410 if (pdata->is_ar724x) {
411 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
412 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
414 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
415 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
417 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
418 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
420 ag71xx_dma_reset(ag);
423 static void ag71xx_hw_start(struct ag71xx *ag)
425 /* start RX engine */
426 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
428 /* enable interrupts */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
432 static void ag71xx_hw_stop(struct ag71xx *ag)
434 /* disable all interrupts */
435 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
437 ag71xx_dma_reset(ag);
440 static int ag71xx_open(struct net_device *dev)
442 struct ag71xx *ag = netdev_priv(dev);
445 ret = ag71xx_rings_init(ag);
449 napi_enable(&ag->napi);
451 netif_carrier_off(dev);
452 ag71xx_phy_start(ag);
454 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
455 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
457 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
461 netif_start_queue(dev);
466 ag71xx_rings_cleanup(ag);
470 static int ag71xx_stop(struct net_device *dev)
472 struct ag71xx *ag = netdev_priv(dev);
475 spin_lock_irqsave(&ag->lock, flags);
477 netif_stop_queue(dev);
481 netif_carrier_off(dev);
484 napi_disable(&ag->napi);
485 del_timer_sync(&ag->oom_timer);
487 spin_unlock_irqrestore(&ag->lock, flags);
489 ag71xx_rings_cleanup(ag);
494 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
496 struct ag71xx *ag = netdev_priv(dev);
497 struct ag71xx_ring *ring = &ag->tx_ring;
498 struct ag71xx_desc *desc;
501 i = ring->curr % AG71XX_TX_RING_SIZE;
502 desc = ring->buf[i].desc;
504 if (!ag71xx_desc_empty(desc))
507 ag71xx_add_ar8216_header(ag, skb);
510 DBG("%s: packet len is too small\n", ag->dev->name);
514 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
516 ring->buf[i].skb = skb;
518 /* setup descriptor fields */
519 desc->data = virt_to_phys(skb->data);
520 desc->ctrl = (skb->len & DESC_PKTLEN_M);
522 /* flush descriptor */
526 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
527 DBG("%s: tx queue full\n", ag->dev->name);
528 netif_stop_queue(dev);
531 DBG("%s: packet injected into TX queue\n", ag->dev->name);
533 /* enable TX engine */
534 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
536 dev->trans_start = jiffies;
541 dev->stats.tx_dropped++;
547 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
549 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
550 struct ag71xx *ag = netdev_priv(dev);
555 if (ag->phy_dev == NULL)
558 spin_lock_irq(&ag->lock);
559 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
560 spin_unlock_irq(&ag->lock);
565 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
571 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
578 if (ag->phy_dev == NULL)
581 return phy_mii_ioctl(ag->phy_dev, data, cmd);
590 static void ag71xx_oom_timer_handler(unsigned long data)
592 struct net_device *dev = (struct net_device *) data;
593 struct ag71xx *ag = netdev_priv(dev);
595 napi_schedule(&ag->napi);
598 static void ag71xx_tx_timeout(struct net_device *dev)
600 struct ag71xx *ag = netdev_priv(dev);
602 if (netif_msg_tx_err(ag))
603 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
605 schedule_work(&ag->restart_work);
608 static void ag71xx_restart_work_func(struct work_struct *work)
610 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
612 ag71xx_stop(ag->dev);
613 ag71xx_open(ag->dev);
616 static int ag71xx_tx_packets(struct ag71xx *ag)
618 struct ag71xx_ring *ring = &ag->tx_ring;
621 DBG("%s: processing TX ring\n", ag->dev->name);
624 while (ring->dirty != ring->curr) {
625 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
626 struct ag71xx_desc *desc = ring->buf[i].desc;
627 struct sk_buff *skb = ring->buf[i].skb;
629 if (!ag71xx_desc_empty(desc))
632 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
634 ag->dev->stats.tx_bytes += skb->len;
635 ag->dev->stats.tx_packets++;
637 dev_kfree_skb_any(skb);
638 ring->buf[i].skb = NULL;
644 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
646 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
647 netif_wake_queue(ag->dev);
652 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
654 struct net_device *dev = ag->dev;
655 struct ag71xx_ring *ring = &ag->rx_ring;
658 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
659 dev->name, limit, ring->curr, ring->dirty);
661 while (done < limit) {
662 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
663 struct ag71xx_desc *desc = ring->buf[i].desc;
667 if (ag71xx_desc_empty(desc))
670 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
675 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
677 skb = ring->buf[i].skb;
678 pktlen = ag71xx_desc_pktlen(desc);
679 pktlen -= ETH_FCS_LEN;
681 skb_put(skb, pktlen);
684 skb->ip_summed = CHECKSUM_NONE;
686 dev->last_rx = jiffies;
687 dev->stats.rx_packets++;
688 dev->stats.rx_bytes += pktlen;
690 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
691 dev->stats.rx_dropped++;
694 skb->protocol = eth_type_trans(skb, dev);
695 netif_receive_skb(skb);
698 ring->buf[i].skb = NULL;
704 ag71xx_ring_rx_refill(ag);
706 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
707 dev->name, ring->curr, ring->dirty, done);
712 static int ag71xx_poll(struct napi_struct *napi, int limit)
714 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
715 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
716 struct net_device *dev = ag->dev;
717 struct ag71xx_ring *rx_ring;
724 tx_done = ag71xx_tx_packets(ag);
726 DBG("%s: processing RX ring\n", dev->name);
727 rx_done = ag71xx_rx_packets(ag, limit);
729 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
731 rx_ring = &ag->rx_ring;
732 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
735 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
736 if (unlikely(status & RX_STATUS_OF)) {
737 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
738 dev->stats.rx_fifo_errors++;
741 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
744 if (rx_done < limit) {
745 if (status & RX_STATUS_PR)
748 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
749 if (status & TX_STATUS_PS)
752 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
753 dev->name, rx_done, tx_done, limit);
757 /* enable interrupts */
758 spin_lock_irqsave(&ag->lock, flags);
759 ag71xx_int_enable(ag, AG71XX_INT_POLL);
760 spin_unlock_irqrestore(&ag->lock, flags);
765 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
766 dev->name, rx_done, tx_done, limit);
770 if (netif_msg_rx_err(ag))
771 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
773 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
778 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
780 struct net_device *dev = dev_id;
781 struct ag71xx *ag = netdev_priv(dev);
784 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
785 ag71xx_dump_intr(ag, "raw", status);
787 if (unlikely(!status))
790 if (unlikely(status & AG71XX_INT_ERR)) {
791 if (status & AG71XX_INT_TX_BE) {
792 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
793 dev_err(&dev->dev, "TX BUS error\n");
795 if (status & AG71XX_INT_RX_BE) {
796 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
797 dev_err(&dev->dev, "RX BUS error\n");
801 if (likely(status & AG71XX_INT_POLL)) {
802 ag71xx_int_disable(ag, AG71XX_INT_POLL);
803 DBG("%s: enable polling mode\n", dev->name);
804 napi_schedule(&ag->napi);
807 ag71xx_debugfs_update_int_stats(ag, status);
812 static void ag71xx_set_multicast_list(struct net_device *dev)
817 static const struct net_device_ops ag71xx_netdev_ops = {
818 .ndo_open = ag71xx_open,
819 .ndo_stop = ag71xx_stop,
820 .ndo_start_xmit = ag71xx_hard_start_xmit,
821 .ndo_set_multicast_list = ag71xx_set_multicast_list,
822 .ndo_do_ioctl = ag71xx_do_ioctl,
823 .ndo_tx_timeout = ag71xx_tx_timeout,
824 .ndo_change_mtu = eth_change_mtu,
825 .ndo_set_mac_address = eth_mac_addr,
826 .ndo_validate_addr = eth_validate_addr,
829 static int __init ag71xx_probe(struct platform_device *pdev)
831 struct net_device *dev;
832 struct resource *res;
834 struct ag71xx_platform_data *pdata;
837 pdata = pdev->dev.platform_data;
839 dev_err(&pdev->dev, "no platform data specified\n");
844 if (pdata->mii_bus_dev == NULL) {
845 dev_err(&pdev->dev, "no MII bus device specified\n");
850 dev = alloc_etherdev(sizeof(*ag));
852 dev_err(&pdev->dev, "alloc_etherdev failed\n");
857 SET_NETDEV_DEV(dev, &pdev->dev);
859 ag = netdev_priv(dev);
862 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
863 AG71XX_DEFAULT_MSG_ENABLE);
864 spin_lock_init(&ag->lock);
866 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
868 dev_err(&pdev->dev, "no mac_base resource found\n");
873 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
875 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
880 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
882 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
887 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
889 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
894 dev->irq = platform_get_irq(pdev, 0);
895 err = request_irq(dev->irq, ag71xx_interrupt,
896 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
899 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
900 goto err_unmap_mii_ctrl;
903 dev->base_addr = (unsigned long)ag->mac_base;
904 dev->netdev_ops = &ag71xx_netdev_ops;
905 dev->ethtool_ops = &ag71xx_ethtool_ops;
907 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
909 init_timer(&ag->oom_timer);
910 ag->oom_timer.data = (unsigned long) dev;
911 ag->oom_timer.function = ag71xx_oom_timer_handler;
913 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
915 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
917 err = register_netdev(dev);
919 dev_err(&pdev->dev, "unable to register net device\n");
923 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
924 dev->name, dev->base_addr, dev->irq);
926 ag71xx_dump_regs(ag);
930 ag71xx_dump_regs(ag);
932 err = ag71xx_phy_connect(ag);
934 goto err_unregister_netdev;
936 err = ag71xx_debugfs_init(ag);
938 goto err_phy_disconnect;
940 platform_set_drvdata(pdev, dev);
945 ag71xx_phy_disconnect(ag);
946 err_unregister_netdev:
947 unregister_netdev(dev);
949 free_irq(dev->irq, dev);
951 iounmap(ag->mii_ctrl);
953 iounmap(ag->mac_base);
957 platform_set_drvdata(pdev, NULL);
961 static int __exit ag71xx_remove(struct platform_device *pdev)
963 struct net_device *dev = platform_get_drvdata(pdev);
966 struct ag71xx *ag = netdev_priv(dev);
968 ag71xx_debugfs_exit(ag);
969 ag71xx_phy_disconnect(ag);
970 unregister_netdev(dev);
971 free_irq(dev->irq, dev);
972 iounmap(ag->mii_ctrl);
973 iounmap(ag->mac_base);
975 platform_set_drvdata(pdev, NULL);
981 static struct platform_driver ag71xx_driver = {
982 .probe = ag71xx_probe,
983 .remove = __exit_p(ag71xx_remove),
985 .name = AG71XX_DRV_NAME,
989 static int __init ag71xx_module_init(void)
993 ret = ag71xx_debugfs_root_init();
997 ret = ag71xx_mdio_driver_init();
999 goto err_debugfs_exit;
1001 ret = platform_driver_register(&ag71xx_driver);
1008 ag71xx_mdio_driver_exit();
1010 ag71xx_debugfs_root_exit();
1015 static void __exit ag71xx_module_exit(void)
1017 platform_driver_unregister(&ag71xx_driver);
1018 ag71xx_mdio_driver_exit();
1019 ag71xx_debugfs_root_exit();
1022 module_init(ag71xx_module_init);
1023 module_exit(ag71xx_module_exit);
1025 MODULE_VERSION(AG71XX_DRV_VERSION);
1026 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1027 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1028 MODULE_LICENSE("GPL v2");
1029 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);