2 * Atheros AR71xx SoC specific definitions
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #ifndef __ASM_MACH_AR71XX_H
17 #define __ASM_MACH_AR71XX_H
19 #include <linux/types.h>
20 #include <linux/init.h>
22 #include <linux/bitops.h>
26 #define AR71XX_PCI_MEM_BASE 0x10000000
27 #define AR71XX_PCI_MEM_SIZE 0x08000000
28 #define AR71XX_APB_BASE 0x18000000
29 #define AR71XX_GE0_BASE 0x19000000
30 #define AR71XX_GE0_SIZE 0x01000000
31 #define AR71XX_GE1_BASE 0x1a000000
32 #define AR71XX_GE1_SIZE 0x01000000
33 #define AR71XX_EHCI_BASE 0x1b000000
34 #define AR71XX_EHCI_SIZE 0x01000000
35 #define AR71XX_OHCI_BASE 0x1c000000
36 #define AR71XX_OHCI_SIZE 0x01000000
37 #define AR7240_OHCI_BASE 0x1b000000
38 #define AR7240_OHCI_SIZE 0x01000000
39 #define AR71XX_SPI_BASE 0x1f000000
40 #define AR71XX_SPI_SIZE 0x01000000
42 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
43 #define AR71XX_DDR_CTRL_SIZE 0x10000
44 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
45 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
46 #define AR71XX_UART_SIZE 0x10000
47 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
48 #define AR71XX_USB_CTRL_SIZE 0x10000
49 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
50 #define AR71XX_GPIO_SIZE 0x10000
51 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
52 #define AR71XX_PLL_SIZE 0x10000
53 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
54 #define AR71XX_RESET_SIZE 0x10000
55 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
56 #define AR71XX_MII_SIZE 0x10000
57 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
58 #define AR71XX_SLIC_SIZE 0x10000
59 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
60 #define AR71XX_DMA_SIZE 0x10000
61 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
62 #define AR71XX_STEREO_SIZE 0x10000
64 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
65 #define AR724X_PCI_CRP_SIZE 0x100
67 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
68 #define AR724X_PCI_CTRL_SIZE 0x100
70 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
71 #define AR91XX_WMAC_SIZE 0x30000
73 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
74 #define AR934X_WMAC_SIZE 0x20000
76 #define AR71XX_MEM_SIZE_MIN 0x0200000
77 #define AR71XX_MEM_SIZE_MAX 0x10000000
79 #define AR71XX_CPU_IRQ_BASE 0
80 #define AR71XX_MISC_IRQ_BASE 8
81 #define AR71XX_MISC_IRQ_COUNT 32
82 #define AR71XX_GPIO_IRQ_BASE 40
83 #define AR71XX_GPIO_IRQ_COUNT 32
84 #define AR71XX_PCI_IRQ_BASE 72
85 #define AR71XX_PCI_IRQ_COUNT 8
87 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
88 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
89 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
90 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
91 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
92 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
94 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
95 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
96 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
97 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
98 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
99 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
100 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
101 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
102 #define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8)
103 #define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9)
104 #define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10)
105 #define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11)
106 #define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12)
108 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
110 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
111 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
112 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
113 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
115 extern u32 ar71xx_ahb_freq;
116 extern u32 ar71xx_cpu_freq;
117 extern u32 ar71xx_ddr_freq;
118 extern u32 ar71xx_ref_freq;
120 enum ar71xx_soc_type {
135 extern enum ar71xx_soc_type ar71xx_soc;
140 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
141 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
142 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
143 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
145 #define AR71XX_PLL_DIV_SHIFT 3
146 #define AR71XX_PLL_DIV_MASK 0x1f
147 #define AR71XX_CPU_DIV_SHIFT 16
148 #define AR71XX_CPU_DIV_MASK 0x3
149 #define AR71XX_DDR_DIV_SHIFT 18
150 #define AR71XX_DDR_DIV_MASK 0x3
151 #define AR71XX_AHB_DIV_SHIFT 20
152 #define AR71XX_AHB_DIV_MASK 0x7
154 #define AR71XX_ETH0_PLL_SHIFT 17
155 #define AR71XX_ETH1_PLL_SHIFT 19
157 #define AR724X_PLL_REG_CPU_CONFIG 0x00
158 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
160 #define AR724X_PLL_DIV_SHIFT 0
161 #define AR724X_PLL_DIV_MASK 0x3ff
162 #define AR724X_PLL_REF_DIV_SHIFT 10
163 #define AR724X_PLL_REF_DIV_MASK 0xf
164 #define AR724X_AHB_DIV_SHIFT 19
165 #define AR724X_AHB_DIV_MASK 0x1
166 #define AR724X_DDR_DIV_SHIFT 22
167 #define AR724X_DDR_DIV_MASK 0x3
169 #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
171 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
172 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
173 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
174 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
176 #define AR91XX_PLL_DIV_SHIFT 0
177 #define AR91XX_PLL_DIV_MASK 0x3ff
178 #define AR91XX_DDR_DIV_SHIFT 22
179 #define AR91XX_DDR_DIV_MASK 0x3
180 #define AR91XX_AHB_DIV_SHIFT 19
181 #define AR91XX_AHB_DIV_MASK 0x1
183 #define AR91XX_ETH0_PLL_SHIFT 20
184 #define AR91XX_ETH1_PLL_SHIFT 22
186 #define AR934X_PLL_REG_CPU_CONFIG 0x00
187 #define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
189 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
190 #define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
191 #define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
193 #define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
194 (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
195 AR934X_CPU_PLL_CFG_OUTDIV_LSB)
197 #define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
198 #define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
199 #define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
201 #define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
202 (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
203 AR934X_DDR_PLL_CFG_OUTDIV_LSB)
205 #define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
206 (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
207 AR934X_DDR_PLL_CFG_OUTDIV_MASK)
209 #define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
210 #define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
211 #define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
213 #define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
214 (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
215 AR934X_CPU_PLL_CFG_REFDIV_LSB)
217 #define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
218 (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
219 AR934X_CPU_PLL_CFG_REFDIV_MASK)
221 #define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
223 #define AR934X_CPU_PLL_CFG_NINT_MSB 11
224 #define AR934X_CPU_PLL_CFG_NINT_LSB 6
225 #define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
227 #define AR934X_CPU_PLL_CFG_NINT_GET(x) \
228 (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
229 AR934X_CPU_PLL_CFG_NINT_LSB)
231 #define AR934X_CPU_PLL_CFG_NINT_SET(x) \
232 (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
233 AR934X_CPU_PLL_CFG_NINT_MASK)
235 #define AR934X_CPU_PLL_CFG_NINT_RESET 20
237 #define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
238 #define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
239 #define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
241 #define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
242 (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
243 AR934X_CPU_PLL_CFG_NFRAC_LSB)
245 #define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
246 (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
247 AR934X_CPU_PLL_CFG_NFRAC_MASK)
249 #define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
250 #define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
251 #define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
253 #define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
254 (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
255 AR934X_DDR_PLL_CFG_REFDIV_LSB)
257 #define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
258 (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
259 AR934X_DDR_PLL_CFG_REFDIV_MASK)
261 #define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
263 #define AR934X_DDR_PLL_CFG_NINT_MSB 15
264 #define AR934X_DDR_PLL_CFG_NINT_LSB 10
265 #define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
267 #define AR934X_DDR_PLL_CFG_NINT_GET(x) \
268 (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
269 AR934X_DDR_PLL_CFG_NINT_LSB)
271 #define AR934X_DDR_PLL_CFG_NINT_SET(x) \
272 (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
273 AR934X_DDR_PLL_CFG_NINT_MASK)
275 #define AR934X_DDR_PLL_CFG_NINT_RESET 20
277 #define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
278 #define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
279 #define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
281 #define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
282 (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
283 AR934X_DDR_PLL_CFG_NFRAC_LSB)
285 #define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
286 (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
287 AR934X_DDR_PLL_CFG_NFRAC_MASK)
289 #define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
291 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
292 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
293 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
295 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
296 (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
297 AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
299 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
300 (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
301 AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
303 #define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
305 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
306 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
307 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
309 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
310 (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
311 AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
313 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
314 (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
315 AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
317 #define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
319 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
320 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
321 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
323 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
324 (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
325 AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
327 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
328 (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
329 AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
331 #define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
333 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
334 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
335 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
337 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
338 (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
339 AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
341 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
342 (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
343 AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
345 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
347 extern void __iomem *ar71xx_pll_base;
349 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
351 __raw_writel(val, ar71xx_pll_base + reg);
354 static inline u32 ar71xx_pll_rr(unsigned reg)
356 return __raw_readl(ar71xx_pll_base + reg);
362 #define USB_CTRL_REG_FLADJ 0x00
363 #define USB_CTRL_REG_CONFIG 0x04
365 extern void __iomem *ar71xx_usb_ctrl_base;
367 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
369 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
372 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
374 return __raw_readl(ar71xx_usb_ctrl_base + reg);
380 #define GPIO_REG_OE 0x00
381 #define GPIO_REG_IN 0x04
382 #define GPIO_REG_OUT 0x08
383 #define GPIO_REG_SET 0x0c
384 #define GPIO_REG_CLEAR 0x10
385 #define GPIO_REG_INT_MODE 0x14
386 #define GPIO_REG_INT_TYPE 0x18
387 #define GPIO_REG_INT_POLARITY 0x1c
388 #define GPIO_REG_INT_PENDING 0x20
389 #define GPIO_REG_INT_ENABLE 0x24
390 #define GPIO_REG_FUNC 0x28
392 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
393 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
394 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
395 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
396 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
397 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
398 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
400 #define AR71XX_GPIO_COUNT 16
402 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
403 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
404 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
405 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
406 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
407 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
408 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
409 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
410 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
411 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
412 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
413 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
414 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
415 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
416 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
417 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
418 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
420 #define AR724X_GPIO_COUNT 18
422 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
423 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
424 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
425 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
426 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
427 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
428 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
429 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
430 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
431 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
433 #define AR91XX_GPIO_COUNT 22
435 #define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
436 #define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
438 #define AR934X_GPIO_COUNT 32
439 #define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
441 extern void __iomem *ar71xx_gpio_base;
443 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
445 __raw_writel(value, ar71xx_gpio_base + reg);
448 static inline u32 ar71xx_gpio_rr(unsigned reg)
450 return __raw_readl(ar71xx_gpio_base + reg);
453 void ar71xx_gpio_init(void) __init;
454 void ar71xx_gpio_function_enable(u32 mask);
455 void ar71xx_gpio_function_disable(u32 mask);
456 void ar71xx_gpio_function_setup(u32 set, u32 clear);
461 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
462 #define AR71XX_DDR_REG_PCI_WIN1 0x80
463 #define AR71XX_DDR_REG_PCI_WIN2 0x84
464 #define AR71XX_DDR_REG_PCI_WIN3 0x88
465 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
466 #define AR71XX_DDR_REG_PCI_WIN5 0x90
467 #define AR71XX_DDR_REG_PCI_WIN6 0x94
468 #define AR71XX_DDR_REG_PCI_WIN7 0x98
469 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
470 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
471 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
472 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
474 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
475 #define AR724X_DDR_REG_FLUSH_GE1 0x80
476 #define AR724X_DDR_REG_FLUSH_USB 0x84
477 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
479 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
480 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
481 #define AR91XX_DDR_REG_FLUSH_USB 0x84
482 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
484 #define AR934X_DDR_REG_FLUSH_GE0 0x9c
485 #define AR934X_DDR_REG_FLUSH_GE1 0xa0
486 #define AR934X_DDR_REG_FLUSH_USB 0xa4
487 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
490 #define PCI_WIN0_OFFS 0x10000000
491 #define PCI_WIN1_OFFS 0x11000000
492 #define PCI_WIN2_OFFS 0x12000000
493 #define PCI_WIN3_OFFS 0x13000000
494 #define PCI_WIN4_OFFS 0x14000000
495 #define PCI_WIN5_OFFS 0x15000000
496 #define PCI_WIN6_OFFS 0x16000000
497 #define PCI_WIN7_OFFS 0x07000000
499 extern void __iomem *ar71xx_ddr_base;
501 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
503 __raw_writel(val, ar71xx_ddr_base + reg);
506 static inline u32 ar71xx_ddr_rr(unsigned reg)
508 return __raw_readl(ar71xx_ddr_base + reg);
511 void ar71xx_ddr_flush(u32 reg);
516 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
517 #define AR71XX_PCI_CFG_SIZE 0x100
519 #define PCI_REG_CRP_AD_CBE 0x00
520 #define PCI_REG_CRP_WRDATA 0x04
521 #define PCI_REG_CRP_RDDATA 0x08
522 #define PCI_REG_CFG_AD 0x0c
523 #define PCI_REG_CFG_CBE 0x10
524 #define PCI_REG_CFG_WRDATA 0x14
525 #define PCI_REG_CFG_RDDATA 0x18
526 #define PCI_REG_PCI_ERR 0x1c
527 #define PCI_REG_PCI_ERR_ADDR 0x20
528 #define PCI_REG_AHB_ERR 0x24
529 #define PCI_REG_AHB_ERR_ADDR 0x28
531 #define PCI_CRP_CMD_WRITE 0x00010000
532 #define PCI_CRP_CMD_READ 0x00000000
533 #define PCI_CFG_CMD_READ 0x0000000a
534 #define PCI_CFG_CMD_WRITE 0x0000000b
536 #define PCI_IDSEL_ADL_START 17
538 #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
539 #define AR724X_PCI_CFG_SIZE 0x1000
541 #define AR724X_PCI_REG_APP 0x00
542 #define AR724X_PCI_REG_RESET 0x18
543 #define AR724X_PCI_REG_INT_STATUS 0x4c
544 #define AR724X_PCI_REG_INT_MASK 0x50
546 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
547 #define AR724X_PCI_RESET_LINK_UP BIT(0)
549 #define AR724X_PCI_INT_DEV0 BIT(14)
554 #define AR71XX_RESET_REG_TIMER 0x00
555 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
556 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
557 #define AR71XX_RESET_REG_WDOG 0x0c
558 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
559 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
560 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
561 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
562 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
563 #define AR71XX_RESET_REG_RESET_MODULE 0x24
564 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
565 #define AR71XX_RESET_REG_PERFC0 0x30
566 #define AR71XX_RESET_REG_PERFC1 0x34
567 #define AR71XX_RESET_REG_REV_ID 0x90
569 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
570 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
571 #define AR91XX_RESET_REG_PERF_CTRL 0x20
572 #define AR91XX_RESET_REG_PERFC0 0x24
573 #define AR91XX_RESET_REG_PERFC1 0x28
575 #define AR724X_RESET_REG_RESET_MODULE 0x1c
577 #define AR934X_RESET_REG_RESET_MODULE 0x1c
578 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
579 /* 0 - 25MHz 1 - 40 MHz */
580 #define AR934X_REF_CLK_40 (1 << 4)
582 #define WDOG_CTRL_LAST_RESET BIT(31)
583 #define WDOG_CTRL_ACTION_MASK 3
584 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
585 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
586 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
587 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
589 #define MISC_INT_ENET_LINK BIT(12)
590 #define MISC_INT_DDR_PERF BIT(11)
591 #define MISC_INT_TIMER4 BIT(10)
592 #define MISC_INT_TIMER3 BIT(9)
593 #define MISC_INT_TIMER2 BIT(8)
594 #define MISC_INT_DMA BIT(7)
595 #define MISC_INT_OHCI BIT(6)
596 #define MISC_INT_PERFC BIT(5)
597 #define MISC_INT_WDOG BIT(4)
598 #define MISC_INT_UART BIT(3)
599 #define MISC_INT_GPIO BIT(2)
600 #define MISC_INT_ERROR BIT(1)
601 #define MISC_INT_TIMER BIT(0)
603 #define PCI_INT_CORE BIT(4)
604 #define PCI_INT_DEV2 BIT(2)
605 #define PCI_INT_DEV1 BIT(1)
606 #define PCI_INT_DEV0 BIT(0)
608 #define RESET_MODULE_EXTERNAL BIT(28)
609 #define RESET_MODULE_FULL_CHIP BIT(24)
610 #define RESET_MODULE_AMBA2WMAC BIT(22)
611 #define RESET_MODULE_CPU_NMI BIT(21)
612 #define RESET_MODULE_CPU_COLD BIT(20)
613 #define RESET_MODULE_DMA BIT(19)
614 #define RESET_MODULE_SLIC BIT(18)
615 #define RESET_MODULE_STEREO BIT(17)
616 #define RESET_MODULE_DDR BIT(16)
617 #define RESET_MODULE_GE1_MAC BIT(13)
618 #define RESET_MODULE_GE1_PHY BIT(12)
619 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
620 #define RESET_MODULE_GE0_MAC BIT(9)
621 #define RESET_MODULE_GE0_PHY BIT(8)
622 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
623 #define RESET_MODULE_USB_HOST BIT(5)
624 #define RESET_MODULE_USB_PHY BIT(4)
625 #define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
626 #define RESET_MODULE_PCI_BUS BIT(1)
627 #define RESET_MODULE_PCI_CORE BIT(0)
629 #define AR724X_RESET_GE1_MDIO BIT(23)
630 #define AR724X_RESET_GE0_MDIO BIT(22)
631 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
632 #define AR724X_RESET_PCIE_PHY BIT(7)
633 #define AR724X_RESET_PCIE BIT(6)
634 #define AR724X_RESET_USB_HOST BIT(5)
635 #define AR724X_RESET_USB_PHY BIT(4)
636 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
638 #define REV_ID_MAJOR_MASK 0xfff0
639 #define REV_ID_MAJOR_AR71XX 0x00a0
640 #define REV_ID_MAJOR_AR913X 0x00b0
641 #define REV_ID_MAJOR_AR7240 0x00c0
642 #define REV_ID_MAJOR_AR7241 0x0100
643 #define REV_ID_MAJOR_AR7242 0x1100
644 #define REV_ID_MAJOR_AR9341 0x0120
645 #define REV_ID_MAJOR_AR9342 0x1120
646 #define REV_ID_MAJOR_AR9344 0x2120
648 #define AR71XX_REV_ID_MINOR_MASK 0x3
649 #define AR71XX_REV_ID_MINOR_AR7130 0x0
650 #define AR71XX_REV_ID_MINOR_AR7141 0x1
651 #define AR71XX_REV_ID_MINOR_AR7161 0x2
652 #define AR71XX_REV_ID_REVISION_MASK 0x3
653 #define AR71XX_REV_ID_REVISION_SHIFT 2
655 #define AR91XX_REV_ID_MINOR_MASK 0x3
656 #define AR91XX_REV_ID_MINOR_AR9130 0x0
657 #define AR91XX_REV_ID_MINOR_AR9132 0x1
658 #define AR91XX_REV_ID_REVISION_MASK 0x3
659 #define AR91XX_REV_ID_REVISION_SHIFT 2
661 #define AR724X_REV_ID_REVISION_MASK 0x3
663 #define AR934X_REV_ID_REVISION_MASK 0xf
665 extern void __iomem *ar71xx_reset_base;
667 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
669 __raw_writel(val, ar71xx_reset_base + reg);
672 static inline u32 ar71xx_reset_rr(unsigned reg)
674 return __raw_readl(ar71xx_reset_base + reg);
677 void ar71xx_device_stop(u32 mask);
678 void ar71xx_device_start(u32 mask);
679 int ar71xx_device_stopped(u32 mask);
684 #define SPI_REG_FS 0x00 /* Function Select */
685 #define SPI_REG_CTRL 0x04 /* SPI Control */
686 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
687 #define SPI_REG_RDS 0x0c /* Read Data Shift */
689 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
691 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
692 #define SPI_CTRL_DIV_MASK 0x3f
694 #define SPI_IOC_DO BIT(0) /* Data Out pin */
695 #define SPI_IOC_CLK BIT(8) /* CLK pin */
696 #define SPI_IOC_CS(n) BIT(16 + (n))
697 #define SPI_IOC_CS0 SPI_IOC_CS(0)
698 #define SPI_IOC_CS1 SPI_IOC_CS(1)
699 #define SPI_IOC_CS2 SPI_IOC_CS(2)
700 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
702 void ar71xx_flash_acquire(void);
703 void ar71xx_flash_release(void);
708 #define MII_REG_MII0_CTRL 0x00
709 #define MII_REG_MII1_CTRL 0x04
711 #define MII0_CTRL_IF_GMII 0
712 #define MII0_CTRL_IF_MII 1
713 #define MII0_CTRL_IF_RGMII 2
714 #define MII0_CTRL_IF_RMII 3
716 #define MII1_CTRL_IF_RGMII 0
717 #define MII1_CTRL_IF_RMII 1
719 #endif /* __ASSEMBLER__ */
721 #endif /* __ASM_MACH_AR71XX_H */