2 * D-Link DIR-825 rev. C1 board support
4 * Copyright (C) 2013 Alexander Stadler
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/pci.h>
12 #include <linux/phy.h>
13 #include <linux/gpio.h>
14 #include <linux/platform_device.h>
15 #include <linux/ath9k_platform.h>
16 #include <linux/ar8216_platform.h>
18 #include <asm/mach-ath79/ar71xx_regs.h>
21 #include "dev-ap9x-pci.h"
23 #include "dev-gpio-buttons.h"
24 #include "dev-leds-gpio.h"
25 #include "dev-m25p80.h"
29 #include "machtypes.h"
31 #define DIR825C1_GPIO_LED_BLUE_USB 11
32 #define DIR825C1_GPIO_LED_ORANGE_POWER 15
33 #define DIR825C1_GPIO_LED_BLUE_POWER 14
34 #define DIR825C1_GPIO_LED_ORANGE_PLANET 19
35 #define DIR825C1_GPIO_LED_BLUE_PLANET 18
37 #define DIR825C1_GPIO_BTN_RESET 17
38 #define DIR825C1_GPIO_BTN_WPS 16
41 #define DIR825C1_KEYS_POLL_INTERVAL 20 /* msecs */
42 #define DIR825C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825C1_KEYS_POLL_INTERVAL)
44 #define DIR825C1_MAC0_OFFSET 0x4
45 #define DIR825C1_MAC1_OFFSET 0x18
46 #define DIR825C1_WMAC_CALDATA_OFFSET 0x1000
47 #define DIR825C1_PCIE_CALDATA_OFFSET 0x5000
49 static struct gpio_led dir825c1_leds_gpio[] __initdata = {
51 .name = "d-link:blue:usb",
52 .gpio = DIR825C1_GPIO_LED_BLUE_USB,
55 .name = "d-link:orange:power",
56 .gpio = DIR825C1_GPIO_LED_ORANGE_POWER,
59 .name = "d-link:blue:power",
60 .gpio = DIR825C1_GPIO_LED_BLUE_POWER,
63 .name = "d-link:orange:planet",
64 .gpio = DIR825C1_GPIO_LED_ORANGE_PLANET,
67 .name = "d-link:blue:planet",
68 .gpio = DIR825C1_GPIO_LED_BLUE_PLANET,
73 static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = {
78 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
79 .gpio = DIR825C1_GPIO_BTN_RESET,
84 .code = KEY_WPS_BUTTON,
85 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
86 .gpio = DIR825C1_GPIO_BTN_WPS,
91 static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = {
92 .mode = AR8327_PAD_MAC_RGMII,
93 .txclk_delay_en = true,
94 .rxclk_delay_en = true,
95 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
96 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
99 static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = {
100 .led_ctrl0 = 0xc737c737,
101 .led_ctrl1 = 0x00000000,
102 .led_ctrl2 = 0x00000000,
103 .led_ctrl3 = 0x0030c300,
107 static struct ar8327_platform_data dir825c1_ar8327_data = {
108 .pad0_cfg = &dir825c1_ar8327_pad0_cfg,
111 .speed = AR8327_PORT_SPEED_1000,
116 .led_cfg = &dir825c1_ar8327_led_cfg,
119 static struct mdio_board_info dir825c1_mdio0_info[] = {
121 .bus_id = "ag71xx-mdio.0",
123 .platform_data = &dir825c1_ar8327_data,
127 static void dir825c1_read_ascii_mac(u8 *dest, u8 *src)
131 ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
132 &dest[0], &dest[1], &dest[2],
133 &dest[3], &dest[4], &dest[5]);
136 memset(dest, 0, ETH_ALEN);
139 static void __init dir825c1_setup(void)
141 u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
142 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
144 u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
146 dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
147 dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
149 ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
151 ath79_register_m25p80(NULL);
153 ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
155 ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
156 ARRAY_SIZE(dir825c1_gpio_keys),
159 ap9x_pci_setup_wmac_led_pin(0, 13);
160 ap9x_pci_setup_wmac_led_pin(1, 32);
162 ath79_init_mac(tmpmac, mac1, 0);
163 ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
165 ath79_init_mac(tmpmac, mac2, 0);
166 ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
168 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
170 mdiobus_register_board_info(dir825c1_mdio0_info,
171 ARRAY_SIZE(dir825c1_mdio0_info));
173 ath79_register_mdio(0, 0x0);
175 ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
177 /* GMAC0 is connected to an AR8327N switch */
178 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
179 ath79_eth0_data.phy_mask = BIT(0);
180 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
181 ath79_eth0_pll_data.pll_1000 = 0x06000000;
182 ath79_register_eth(0);
184 ath79_register_usb();
187 MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1",
188 "D-Link DIR-825 rev. C1",