2 * D-Link DIR-825 rev. C1 board support
4 * Copyright (C) 2013 Alexander Stadler
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/pci.h>
12 #include <linux/phy.h>
13 #include <linux/gpio.h>
14 #include <linux/platform_device.h>
15 #include <linux/ath9k_platform.h>
16 #include <linux/ar8216_platform.h>
18 #include <asm/mach-ath79/ar71xx_regs.h>
21 #include "dev-ap9x-pci.h"
23 #include "dev-gpio-buttons.h"
24 #include "dev-leds-gpio.h"
25 #include "dev-m25p80.h"
29 #include "machtypes.h"
31 #define DIR825C1_GPIO_LED_BLUE_USB 11
32 #define DIR825C1_GPIO_LED_ORANGE_POWER 14
33 #define DIR825C1_GPIO_LED_BLUE_POWER 22
34 #define DIR825C1_GPIO_LED_BLUE_WPS 15
35 #define DIR825C1_GPIO_LED_ORANGE_PLANET 19
36 #define DIR825C1_GPIO_LED_BLUE_PLANET 18
38 #define DIR825C1_GPIO_BTN_RESET 17
39 #define DIR825C1_GPIO_BTN_WPS 16
41 #define DIR825C1_KEYS_POLL_INTERVAL 20 /* msecs */
42 #define DIR825C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825C1_KEYS_POLL_INTERVAL)
44 #define DIR825C1_MAC0_OFFSET 0x4
45 #define DIR825C1_MAC1_OFFSET 0x18
46 #define DIR825C1_WMAC_CALDATA_OFFSET 0x1000
47 #define DIR825C1_PCIE_CALDATA_OFFSET 0x5000
49 static struct gpio_led dir825c1_leds_gpio[] __initdata = {
51 .name = "d-link:blue:usb",
52 .gpio = DIR825C1_GPIO_LED_BLUE_USB,
56 .name = "d-link:orange:power",
57 .gpio = DIR825C1_GPIO_LED_ORANGE_POWER,
61 .name = "d-link:blue:power",
62 .gpio = DIR825C1_GPIO_LED_BLUE_POWER,
66 .name = "d-link:blue:wps",
67 .gpio = DIR825C1_GPIO_LED_BLUE_WPS,
71 .name = "d-link:orange:planet",
72 .gpio = DIR825C1_GPIO_LED_ORANGE_PLANET,
76 .name = "d-link:blue:planet",
77 .gpio = DIR825C1_GPIO_LED_BLUE_PLANET,
82 static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = {
87 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
88 .gpio = DIR825C1_GPIO_BTN_RESET,
94 .code = KEY_WPS_BUTTON,
95 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
96 .gpio = DIR825C1_GPIO_BTN_WPS,
101 static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = {
102 .mode = AR8327_PAD_MAC_RGMII,
103 .txclk_delay_en = true,
104 .rxclk_delay_en = true,
105 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
106 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
109 static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = {
110 .led_ctrl0 = 0xc737c737,
111 .led_ctrl1 = 0x00000000,
112 .led_ctrl2 = 0x00000000,
113 .led_ctrl3 = 0x0030c300,
117 static struct ar8327_platform_data dir825c1_ar8327_data = {
118 .pad0_cfg = &dir825c1_ar8327_pad0_cfg,
121 .speed = AR8327_PORT_SPEED_1000,
126 .led_cfg = &dir825c1_ar8327_led_cfg,
129 static struct mdio_board_info dir825c1_mdio0_info[] = {
131 .bus_id = "ag71xx-mdio.0",
133 .platform_data = &dir825c1_ar8327_data,
137 static void dir825c1_read_ascii_mac(u8 *dest, u8 *src)
141 ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
142 &dest[0], &dest[1], &dest[2],
143 &dest[3], &dest[4], &dest[5]);
146 memset(dest, 0, ETH_ALEN);
149 static void __init dir825c1_setup(void)
151 u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
152 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
153 u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
154 u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
156 dir825c1_read_ascii_mac(mac0, mac + DIR825C1_MAC0_OFFSET);
157 dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC1_OFFSET);
159 ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
161 ath79_register_m25p80(NULL);
163 ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
165 ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
166 ARRAY_SIZE(dir825c1_gpio_keys),
169 ap9x_pci_setup_wmac_led_pin(0, 13);
170 ap9x_pci_setup_wmac_led_pin(1, 32);
172 ath79_init_mac(wmac0, mac0, 0);
173 ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0);
175 ath79_init_mac(wmac1, mac1, 1);
176 ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1);
178 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
180 mdiobus_register_board_info(dir825c1_mdio0_info,
181 ARRAY_SIZE(dir825c1_mdio0_info));
183 ath79_register_mdio(0, 0x0);
185 ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
187 /* GMAC0 is connected to an AR8327N switch */
188 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
189 ath79_eth0_data.phy_mask = BIT(0);
190 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
191 ath79_eth0_pll_data.pll_1000 = 0x06000000;
192 ath79_register_eth(0);
194 ath79_register_usb();
197 MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1",
198 "D-Link DIR-825 rev. C1",