target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26
  27 #include <asm/mach-ar71xx/ar71xx.h>
  28 #include <asm/mach-ar71xx/pci.h>
  29 #include <asm/mach-ar71xx/platform.h>
  30
  31 #define AR71XX_SYS_TYPE_LEN     64
  32 #define AR71XX_BASE_FREQ        40000000
  33 #define AR91XX_BASE_FREQ        5000000
  34
  35 #define AR71XX_MEM_SIZE_MIN     0x0200000
  36 #define AR71XX_MEM_SIZE_MAX     0x8000000
  37
  38 unsigned long ar71xx_mach_type;
  39
  40 u32 ar71xx_cpu_freq;
  41 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  42
  43 u32 ar71xx_ahb_freq;
  44 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  45
  46 u32 ar71xx_ddr_freq;
  47 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  48
  49 enum ar71xx_soc_type ar71xx_soc;
  50 EXPORT_SYMBOL_GPL(ar71xx_soc);
  51
  52 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  53                              struct ar71xx_pci_irq *map) __initdata;
  54
  55 int (*ar71xx_pci_be_handler)(int is_fixup);
  56
  57 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  58
  59 static void ar71xx_restart(char *command)
  60 {
  61         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  62         for (;;)
  63                 if (cpu_wait)
  64                         cpu_wait();
  65 }
  66
  67 static void ar71xx_halt(void)
  68 {
  69         while (1)
  70                 cpu_wait();
  71 }
  72
  73 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  74 {
  75         int err = 0;
  76
  77         if (ar71xx_pci_be_handler)
  78                 err = ar71xx_pci_be_handler(is_fixup);
  79
  80         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  81 }
  82
  83 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  84 {
  85         if (!ar71xx_pci_bios_init)
  86                 return 0;
  87
  88         return ar71xx_pci_bios_init(nr_irqs, map);
  89 }
  90
  91 static void __init ar71xx_detect_mem_size(void)
  92 {
  93         unsigned long size;
  94
  95         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  96              size <<= 1 ) {
  97                 if (!memcmp(ar71xx_detect_mem_size,
  98                             ar71xx_detect_mem_size + size, 1024))
  99                         break;
 100         }
 101
 102         add_memory_region(0, size, BOOT_MEM_RAM);
 103 }
 104
 105 static void __init ar71xx_detect_sys_type(void)
 106 {
 107         char *chip;
 108         u32 id;
 109         u32 rev;
 110
 111         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
 112         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 113
 114         switch (id & REV_ID_CHIP_MASK) {
 115         case REV_ID_CHIP_AR7130:
 116                 ar71xx_soc = AR71XX_SOC_AR7130;
 117                 chip = "7130";
 118                 break;
 119
 120         case REV_ID_CHIP_AR7141:
 121                 ar71xx_soc = AR71XX_SOC_AR7141;
 122                 chip = "7141";
 123                 break;
 124
 125         case REV_ID_CHIP_AR7161:
 126                 ar71xx_soc = AR71XX_SOC_AR7161;
 127                 chip = "7161";
 128                 break;
 129
 130         case REV_ID_CHIP_AR9130:
 131                 ar71xx_soc = AR71XX_SOC_AR9130;
 132                 chip = "9130";
 133                 break;
 134
 135         case REV_ID_CHIP_AR9132:
 136                 ar71xx_soc = AR71XX_SOC_AR9132;
 137                 chip = "9132";
 138                 break;
 139
 140         default:
 141                 panic("ar71xx: unknown chip id:0x%02x\n", id);
 142         }
 143
 144         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 145                 chip, rev, id);
 146 }
 147
 148 static void __init ar91xx_detect_sys_frequency(void)
 149 {
 150         u32 pll;
 151         u32 freq;
 152         u32 div;
 153
 154         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 155
 156         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 157         freq = div * AR91XX_BASE_FREQ;
 158
 159         ar71xx_cpu_freq = freq;
 160
 161         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 162         ar71xx_ddr_freq = freq / div;
 163
 164         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 165         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 166 }
 167
 168 static void __init ar71xx_detect_sys_frequency(void)
 169 {
 170         u32 pll;
 171         u32 freq;
 172         u32 div;
 173
 174         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 175
 176         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 177         freq = div * AR71XX_BASE_FREQ;
 178
 179         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 180         ar71xx_cpu_freq = freq / div;
 181
 182         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 183         ar71xx_ddr_freq = freq / div;
 184
 185         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 186         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 187 }
 188
 189 static void __init detect_sys_frequency(void)
 190 {
 191         switch (ar71xx_soc) {
 192         case AR71XX_SOC_AR7130:
 193         case AR71XX_SOC_AR7141:
 194         case AR71XX_SOC_AR7161:
 195                 ar71xx_detect_sys_frequency();
 196                 break;
 197
 198         case AR71XX_SOC_AR9130:
 199         case AR71XX_SOC_AR9132:
 200                 ar91xx_detect_sys_frequency();
 201                 break;
 202
 203         default:
 204                 BUG();
 205         }
 206 }
 207
 208 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 209 static void __init ar71xx_early_serial_setup(void)
 210 {
 211         struct uart_port p;
 212
 213         memset(&p, 0, sizeof(p));
 214
 215         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 216         p.iotype        = UPIO_MEM32;
 217         p.uartclk       = ar71xx_ahb_freq;
 218         p.irq           = AR71XX_MISC_IRQ_UART;
 219         p.regshift      = 2;
 220         p.mapbase       = AR71XX_UART_BASE;
 221
 222         early_serial_setup(&p);
 223 }
 224 #else
 225 static inline void ar71xx_early_serial_setup(void) {};
 226 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 227
 228 const char *get_system_type(void)
 229 {
 230         return ar71xx_sys_type;
 231 }
 232
 233 unsigned int __cpuinit get_c0_compare_irq(void)
 234 {
 235         return CP0_LEGACY_COMPARE_IRQ;
 236 }
 237
 238 void __init plat_mem_setup(void)
 239 {
 240         set_io_port_base(KSEG1);
 241
 242         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 243                                                 AR71XX_DDR_CTRL_SIZE);
 244
 245         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 246                                                 AR71XX_PLL_SIZE);
 247
 248         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 249                                                 AR71XX_RESET_SIZE);
 250
 251         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 252
 253         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 254                                                 AR71XX_USB_CTRL_SIZE);
 255
 256         ar71xx_detect_mem_size();
 257         ar71xx_detect_sys_type();
 258         detect_sys_frequency();
 259
 260         _machine_restart = ar71xx_restart;
 261         _machine_halt = ar71xx_halt;
 262         pm_power_off = ar71xx_halt;
 263
 264         board_be_handler = ar71xx_be_handler;
 265
 266         ar71xx_early_serial_setup();
 267 }
 268
 269 void __init plat_time_init(void)
 270 {
 271         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 272 }