2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
25 #include <asm/mach-ar71xx/ar71xx.h>
30 #define AR71XX_SYS_TYPE_LEN 64
31 #define AR71XX_BASE_FREQ 40000000
32 #define AR91XX_BASE_FREQ 5000000
33 #define AR724X_BASE_FREQ 5000000
36 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
39 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
42 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
45 EXPORT_SYMBOL_GPL(ar934x_ref_freq);
47 enum ar71xx_soc_type ar71xx_soc;
48 EXPORT_SYMBOL_GPL(ar71xx_soc);
50 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
52 static void ar71xx_restart(char *command)
54 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
60 static void ar71xx_halt(void)
66 static void __init ar71xx_detect_mem_size(void)
70 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
72 if (!memcmp(ar71xx_detect_mem_size,
73 ar71xx_detect_mem_size + size, 1024))
77 add_memory_region(0, size, BOOT_MEM_RAM);
80 static void __init ar71xx_detect_sys_type(void)
88 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
89 major = id & REV_ID_MAJOR_MASK;
92 case REV_ID_MAJOR_AR71XX:
93 minor = id & AR71XX_REV_ID_MINOR_MASK;
94 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
95 rev &= AR71XX_REV_ID_REVISION_MASK;
97 case AR71XX_REV_ID_MINOR_AR7130:
98 ar71xx_soc = AR71XX_SOC_AR7130;
102 case AR71XX_REV_ID_MINOR_AR7141:
103 ar71xx_soc = AR71XX_SOC_AR7141;
107 case AR71XX_REV_ID_MINOR_AR7161:
108 ar71xx_soc = AR71XX_SOC_AR7161;
114 case REV_ID_MAJOR_AR7240:
115 ar71xx_soc = AR71XX_SOC_AR7240;
117 rev = id & AR724X_REV_ID_REVISION_MASK;
120 case REV_ID_MAJOR_AR7241:
121 ar71xx_soc = AR71XX_SOC_AR7241;
123 rev = id & AR724X_REV_ID_REVISION_MASK;
126 case REV_ID_MAJOR_AR7242:
127 ar71xx_soc = AR71XX_SOC_AR7242;
129 rev = id & AR724X_REV_ID_REVISION_MASK;
132 case REV_ID_MAJOR_AR913X:
133 minor = id & AR91XX_REV_ID_MINOR_MASK;
134 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
135 rev &= AR91XX_REV_ID_REVISION_MASK;
137 case AR91XX_REV_ID_MINOR_AR9130:
138 ar71xx_soc = AR71XX_SOC_AR9130;
142 case AR91XX_REV_ID_MINOR_AR9132:
143 ar71xx_soc = AR71XX_SOC_AR9132;
149 case REV_ID_MAJOR_AR9341:
150 ar71xx_soc = AR71XX_SOC_AR9341;
152 rev = id & AR934X_REV_ID_REVISION_MASK;
155 case REV_ID_MAJOR_AR9342:
156 ar71xx_soc = AR71XX_SOC_AR9342;
158 rev = id & AR934X_REV_ID_REVISION_MASK;
161 case REV_ID_MAJOR_AR9344:
162 ar71xx_soc = AR71XX_SOC_AR9344;
164 rev = id & AR934X_REV_ID_REVISION_MASK;
168 panic("ar71xx: unknown chip id:0x%08x\n", id);
171 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
172 pr_info("SoC: %s\n", ar71xx_sys_type);
175 static void __init ar934x_detect_sys_frequency(void)
177 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv;
179 if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
180 ref = (40 * 1000000);
182 ref = (25 * 1000000);
184 ar934x_ref_freq = ref;
186 clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
188 pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
189 out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
190 ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
191 nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
192 frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
193 postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
194 ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
196 out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
197 ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
198 nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
199 frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
200 postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
201 ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
203 postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
205 if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
206 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
208 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
213 static void __init ar91xx_detect_sys_frequency(void)
219 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
221 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
222 freq = div * AR91XX_BASE_FREQ;
224 ar71xx_cpu_freq = freq;
226 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
227 ar71xx_ddr_freq = freq / div;
229 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
230 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
233 static void __init ar71xx_detect_sys_frequency(void)
239 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
241 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
242 freq = div * AR71XX_BASE_FREQ;
244 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
245 ar71xx_cpu_freq = freq / div;
247 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
248 ar71xx_ddr_freq = freq / div;
250 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
251 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
254 static void __init ar724x_detect_sys_frequency(void)
260 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
262 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
263 freq = div * AR724X_BASE_FREQ;
265 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
268 ar71xx_cpu_freq = freq;
270 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
271 ar71xx_ddr_freq = freq / div;
273 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
274 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
277 static void __init detect_sys_frequency(void)
279 switch (ar71xx_soc) {
280 case AR71XX_SOC_AR7130:
281 case AR71XX_SOC_AR7141:
282 case AR71XX_SOC_AR7161:
283 ar71xx_detect_sys_frequency();
286 case AR71XX_SOC_AR7240:
287 case AR71XX_SOC_AR7241:
288 case AR71XX_SOC_AR7242:
289 ar724x_detect_sys_frequency();
292 case AR71XX_SOC_AR9130:
293 case AR71XX_SOC_AR9132:
294 ar91xx_detect_sys_frequency();
297 case AR71XX_SOC_AR9341:
298 case AR71XX_SOC_AR9342:
299 case AR71XX_SOC_AR9344:
300 ar934x_detect_sys_frequency();
307 const char *get_system_type(void)
309 return ar71xx_sys_type;
312 unsigned int __cpuinit get_c0_compare_irq(void)
314 return CP0_LEGACY_COMPARE_IRQ;
317 void __init plat_mem_setup(void)
319 set_io_port_base(KSEG1);
321 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
322 AR71XX_DDR_CTRL_SIZE);
324 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
327 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
330 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
332 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
333 AR71XX_USB_CTRL_SIZE);
335 ar71xx_detect_mem_size();
336 ar71xx_detect_sys_type();
337 detect_sys_frequency();
339 pr_info("Clocks: CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
340 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
341 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
342 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
344 _machine_restart = ar71xx_restart;
345 _machine_halt = ar71xx_halt;
346 pm_power_off = ar71xx_halt;
349 void __init plat_time_init(void)
351 mips_hpt_frequency = ar71xx_cpu_freq / 2;
354 __setup("board=", mips_machtype_setup);
356 static int __init ar71xx_machine_setup(void)
360 ar71xx_add_device_uart();
361 ar71xx_add_device_wdt();
363 mips_machine_setup();
367 arch_initcall(ar71xx_machine_setup);
369 static void __init ar71xx_generic_init(void)
374 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
375 ar71xx_generic_init);