2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
24 static int ip2_flush_reg;
26 static void ar71xx_gpio_irq_dispatch(void)
28 void __iomem *base = ar71xx_gpio_base;
31 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
32 __raw_readl(base + GPIO_REG_INT_ENABLE);
35 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
40 static void ar71xx_gpio_irq_unmask(unsigned int irq)
42 void __iomem *base = ar71xx_gpio_base;
45 irq -= AR71XX_GPIO_IRQ_BASE;
47 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
48 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
51 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
54 static void ar71xx_gpio_irq_mask(unsigned int irq)
56 void __iomem *base = ar71xx_gpio_base;
59 irq -= AR71XX_GPIO_IRQ_BASE;
61 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
62 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
65 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
69 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
75 #define ar71xx_gpio_irq_set_type NULL
78 static struct irq_chip ar71xx_gpio_irq_chip = {
79 .name = "AR71XX GPIO",
80 .unmask = ar71xx_gpio_irq_unmask,
81 .mask = ar71xx_gpio_irq_mask,
82 .mask_ack = ar71xx_gpio_irq_mask,
83 .set_type = ar71xx_gpio_irq_set_type,
86 static struct irqaction ar71xx_gpio_irqaction = {
88 .name = "cascade [AR71XX GPIO]",
91 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
92 #define GPIO_INT_ALL 0xffff
94 static void __init ar71xx_gpio_irq_init(void)
96 void __iomem *base = ar71xx_gpio_base;
99 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
100 __raw_writel(0, base + GPIO_REG_INT_PENDING);
102 /* setup type of all GPIO interrupts to level sensitive */
103 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
105 /* setup polarity of all GPIO interrupts to active high */
106 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
108 for (i = AR71XX_GPIO_IRQ_BASE;
109 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
110 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
111 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
115 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
118 static void ar71xx_misc_irq_dispatch(void)
122 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
123 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
125 if (pending & MISC_INT_UART)
126 do_IRQ(AR71XX_MISC_IRQ_UART);
128 else if (pending & MISC_INT_DMA)
129 do_IRQ(AR71XX_MISC_IRQ_DMA);
131 else if (pending & MISC_INT_PERFC)
132 do_IRQ(AR71XX_MISC_IRQ_PERFC);
134 else if (pending & MISC_INT_TIMER)
135 do_IRQ(AR71XX_MISC_IRQ_TIMER);
137 else if (pending & MISC_INT_OHCI)
138 do_IRQ(AR71XX_MISC_IRQ_OHCI);
140 else if (pending & MISC_INT_ERROR)
141 do_IRQ(AR71XX_MISC_IRQ_ERROR);
143 else if (pending & MISC_INT_GPIO)
144 ar71xx_gpio_irq_dispatch();
146 else if (pending & MISC_INT_WDOG)
147 do_IRQ(AR71XX_MISC_IRQ_WDOG);
150 spurious_interrupt();
153 static void ar71xx_misc_irq_unmask(unsigned int irq)
155 void __iomem *base = ar71xx_reset_base;
158 irq -= AR71XX_MISC_IRQ_BASE;
160 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
161 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
164 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
167 static void ar71xx_misc_irq_mask(unsigned int irq)
169 void __iomem *base = ar71xx_reset_base;
172 irq -= AR71XX_MISC_IRQ_BASE;
174 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
175 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
178 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
181 static void ar724x_misc_irq_ack(unsigned int irq)
183 void __iomem *base = ar71xx_reset_base;
186 irq -= AR71XX_MISC_IRQ_BASE;
188 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
189 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
192 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
195 static struct irq_chip ar71xx_misc_irq_chip = {
196 .name = "AR71XX MISC",
197 .unmask = ar71xx_misc_irq_unmask,
198 .mask = ar71xx_misc_irq_mask,
201 static struct irqaction ar71xx_misc_irqaction = {
202 .handler = no_action,
203 .name = "cascade [AR71XX MISC]",
206 static void __init ar71xx_misc_irq_init(void)
208 void __iomem *base = ar71xx_reset_base;
211 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
212 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
214 switch (ar71xx_soc) {
215 case AR71XX_SOC_AR7240:
216 case AR71XX_SOC_AR7241:
217 case AR71XX_SOC_AR7242:
218 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
221 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
225 for (i = AR71XX_MISC_IRQ_BASE;
226 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
227 irq_desc[i].status = IRQ_DISABLED;
228 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
232 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
235 asmlinkage void plat_irq_dispatch(void)
237 unsigned long pending;
239 pending = read_c0_status() & read_c0_cause() & ST0_IM;
241 if (pending & STATUSF_IP7)
242 do_IRQ(AR71XX_CPU_IRQ_TIMER);
244 else if (pending & STATUSF_IP2) {
246 * This IRQ is meant for a PCI device. Drivers for PCI devices
247 * typically allocate coherent DMA memory for the descriptor
248 * ring, however the DMA controller may still have some
249 * unsynchronized data in the FIFO.
250 * Issue a flush here to ensure that the driver sees the update.
252 ar71xx_ddr_flush(ip2_flush_reg);
253 do_IRQ(AR71XX_CPU_IRQ_IP2);
256 else if (pending & STATUSF_IP4)
257 do_IRQ(AR71XX_CPU_IRQ_GE0);
259 else if (pending & STATUSF_IP5)
260 do_IRQ(AR71XX_CPU_IRQ_GE1);
262 else if (pending & STATUSF_IP3)
263 do_IRQ(AR71XX_CPU_IRQ_USB);
265 else if (pending & STATUSF_IP6)
266 ar71xx_misc_irq_dispatch();
269 spurious_interrupt();
272 void __init arch_init_irq(void)
275 case AR71XX_SOC_AR7240:
276 case AR71XX_SOC_AR7241:
277 case AR71XX_SOC_AR7242:
278 ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
280 case AR71XX_SOC_AR9130:
281 case AR71XX_SOC_AR9132:
282 ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
285 ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
290 ar71xx_misc_irq_init();
292 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
294 ar71xx_gpio_irq_init();