2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_dispatch(void)
29 pending = ar71xx_reset_rr(RESET_REG_PCI_INT_STATUS) &
30 ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE);
32 if (pending & PCI_INT_DEV0)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0);
35 else if (pending & PCI_INT_DEV1)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1);
38 else if (pending & PCI_INT_DEV2)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2);
45 static void ar71xx_pci_irq_unmask(unsigned int irq)
47 irq -= AR71XX_PCI_IRQ_BASE;
48 ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE,
49 ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) | (1 << irq));
52 static void ar71xx_pci_irq_mask(unsigned int irq)
54 irq -= AR71XX_PCI_IRQ_BASE;
55 ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE,
56 ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
59 static struct irq_chip ar71xx_pci_irq_chip = {
60 .name = "AR71XX PCI ",
61 .mask = ar71xx_pci_irq_mask,
62 .unmask = ar71xx_pci_irq_unmask,
63 .mask_ack = ar71xx_pci_irq_mask,
66 static struct irqaction ar71xx_pci_irqaction = {
68 .name = "cascade [AR71XX PCI]",
71 static void __init ar71xx_pci_irq_init(void)
75 ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, 0);
76 ar71xx_reset_wr(RESET_REG_PCI_INT_STATUS, 0);
78 for (i = AR71XX_PCI_IRQ_BASE;
79 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
80 irq_desc[i].status = IRQ_DISABLED;
81 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
85 setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
88 #endif /* CONFIG_PCI */
90 static void ar71xx_gpio_irq_dispatch(void)
94 pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
95 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
98 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
100 spurious_interrupt();
103 static void ar71xx_gpio_irq_unmask(unsigned int irq)
105 irq -= AR71XX_GPIO_IRQ_BASE;
106 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
107 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
110 static void ar71xx_gpio_irq_mask(unsigned int irq)
112 irq -= AR71XX_GPIO_IRQ_BASE;
113 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
114 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
118 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
120 /* TODO: implement */
124 #define ar71xx_gpio_irq_set_type NULL
127 struct irq_chip ar71xx_gpio_irq_chip = {
128 .name = "AR71XX GPIO",
129 .unmask = ar71xx_gpio_irq_unmask,
130 .mask = ar71xx_gpio_irq_mask,
131 .mask_ack = ar71xx_gpio_irq_mask,
132 .set_type = ar71xx_gpio_irq_set_type,
135 static struct irqaction ar71xx_gpio_irqaction = {
136 .handler = no_action,
137 .name = "cascade [AR71XX GPIO]",
140 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
141 #define GPIO_INT_ALL 0xffff
143 static void __init ar71xx_gpio_irq_init(void)
147 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
148 ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
150 /* setup type of all GPIO interrupts to level sensitive */
151 ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
153 /* setup polarity of all GPIO interrupts to active high */
154 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
156 for (i = AR71XX_GPIO_IRQ_BASE;
157 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
158 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
159 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
163 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
166 static void ar71xx_misc_irq_dispatch(void)
170 pending = ar71xx_reset_rr(RESET_REG_MISC_INT_STATUS)
171 & ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE);
173 if (pending & MISC_INT_UART)
174 do_IRQ(AR71XX_MISC_IRQ_UART);
176 else if (pending & MISC_INT_DMA)
177 do_IRQ(AR71XX_MISC_IRQ_DMA);
179 else if (pending & MISC_INT_PERFC)
180 do_IRQ(AR71XX_MISC_IRQ_PERFC);
182 else if (pending & MISC_INT_TIMER)
183 do_IRQ(AR71XX_MISC_IRQ_TIMER);
185 else if (pending & MISC_INT_OHCI)
186 do_IRQ(AR71XX_MISC_IRQ_OHCI);
188 else if (pending & MISC_INT_ERROR)
189 do_IRQ(AR71XX_MISC_IRQ_ERROR);
191 else if (pending & MISC_INT_GPIO)
192 ar71xx_gpio_irq_dispatch();
194 else if (pending & MISC_INT_WDOG)
195 do_IRQ(AR71XX_MISC_IRQ_WDOG);
198 spurious_interrupt();
201 static void ar71xx_misc_irq_unmask(unsigned int irq)
203 irq -= AR71XX_MISC_IRQ_BASE;
204 ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE,
205 ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) | (1 << irq));
208 static void ar71xx_misc_irq_mask(unsigned int irq)
210 irq -= AR71XX_MISC_IRQ_BASE;
211 ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE,
212 ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
215 struct irq_chip ar71xx_misc_irq_chip = {
216 .name = "AR71XX MISC",
217 .unmask = ar71xx_misc_irq_unmask,
218 .mask = ar71xx_misc_irq_mask,
219 .mask_ack = ar71xx_misc_irq_mask,
222 static struct irqaction ar71xx_misc_irqaction = {
223 .handler = no_action,
224 .name = "cascade [AR71XX MISC]",
227 static void __init ar71xx_misc_irq_init(void)
231 ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, 0);
232 ar71xx_reset_wr(RESET_REG_MISC_INT_STATUS, 0);
234 for (i = AR71XX_MISC_IRQ_BASE;
235 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
236 irq_desc[i].status = IRQ_DISABLED;
237 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
241 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
244 asmlinkage void plat_irq_dispatch(void)
246 unsigned long pending;
248 pending = read_c0_status() & read_c0_cause() & ST0_IM;
250 if (pending & STATUSF_IP7)
251 do_IRQ(AR71XX_CPU_IRQ_TIMER);
254 else if (pending & STATUSF_IP2)
255 ar71xx_pci_irq_dispatch();
258 else if (pending & STATUSF_IP4)
259 do_IRQ(AR71XX_CPU_IRQ_GE0);
261 else if (pending & STATUSF_IP5)
262 do_IRQ(AR71XX_CPU_IRQ_GE1);
264 else if (pending & STATUSF_IP3)
265 do_IRQ(AR71XX_CPU_IRQ_USB);
267 else if (pending & STATUSF_IP6)
268 ar71xx_misc_irq_dispatch();
271 spurious_interrupt();
274 void __init arch_init_irq(void)
278 ar71xx_misc_irq_init();
281 ar71xx_pci_irq_init();
284 ar71xx_gpio_irq_init();