2 * Atheros AR71xx SoC GPIO API support
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/spinlock.h>
18 #include <linux/ioport.h>
19 #include <linux/gpio.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
23 static DEFINE_SPINLOCK(ar71xx_gpio_lock);
25 unsigned long ar71xx_gpio_count;
26 EXPORT_SYMBOL(ar71xx_gpio_count);
28 void __ar71xx_gpio_set_value(unsigned gpio, int value)
32 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
35 ar71xx_gpio_wr(GPIO_REG_SET, (1 << gpio));
37 ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << gpio));
39 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
41 EXPORT_SYMBOL(__ar71xx_gpio_set_value);
43 int __ar71xx_gpio_get_value(unsigned gpio)
45 return (ar71xx_gpio_rr(GPIO_REG_IN) & (1 << gpio)) ? 1 : 0;
47 EXPORT_SYMBOL(__ar71xx_gpio_get_value);
49 static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
51 return __ar71xx_gpio_get_value(offset);
54 static void ar71xx_gpio_set_value(struct gpio_chip *chip,
55 unsigned offset, int value)
57 __ar71xx_gpio_set_value(offset, value);
60 static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
65 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
67 ar71xx_gpio_wr(GPIO_REG_OE,
68 ar71xx_gpio_rr(GPIO_REG_OE) & ~(1 << offset));
70 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
75 static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
76 unsigned offset, int value)
80 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
83 ar71xx_gpio_wr(GPIO_REG_SET, (1 << offset));
85 ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << offset));
87 ar71xx_gpio_wr(GPIO_REG_OE,
88 ar71xx_gpio_rr(GPIO_REG_OE) | (1 << offset));
90 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
95 static struct gpio_chip ar71xx_gpio_chip = {
97 .get = ar71xx_gpio_get_value,
98 .set = ar71xx_gpio_set_value,
99 .direction_input = ar71xx_gpio_direction_input,
100 .direction_output = ar71xx_gpio_direction_output,
102 .ngpio = AR71XX_GPIO_COUNT,
105 void ar71xx_gpio_function_enable(u32 mask)
109 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
111 ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) | mask);
113 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
116 void ar71xx_gpio_function_disable(u32 mask)
120 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
122 ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) & ~mask);
124 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
127 void __init ar71xx_gpio_init(void)
131 if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
132 "AR71xx GPIO controller"))
133 panic("cannot allocate AR71xx GPIO registers page");
135 switch (ar71xx_soc) {
136 case AR71XX_SOC_AR7130:
137 case AR71XX_SOC_AR7141:
138 case AR71XX_SOC_AR7161:
139 ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
142 case AR71XX_SOC_AR7240:
143 ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
146 case AR71XX_SOC_AR9130:
147 case AR71XX_SOC_AR9132:
148 ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
155 err = gpiochip_add(&ar71xx_gpio_chip);
157 panic("cannot add AR71xx GPIO chip, error=%d", err);