4 * Copyright (C) 2006, 2007 OpenWrt.org
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <asm/ar7/vlynq.h>
28 #define VLYNQ_PCI_SLOTS 2
30 struct vlynq_reg_config {
35 struct vlynq_pci_config {
38 struct vlynq_mapping rx_mapping[4];
44 struct vlynq_reg_config regs[10];
47 struct vlynq_pci_private {
52 struct vlynq_pci_config *config;
55 static struct vlynq_pci_config known_devices[] = {
57 .chip_id = 0x00000009, .name = "TI ACX111",
59 { .size = 0x22000, .offset = 0xf0000000 },
60 { .size = 0x40000, .offset = 0xc0000000 },
61 { .size = 0x0, .offset = 0x0 },
62 { .size = 0x0, .offset = 0x0 },
64 .irq = 0, .chip = 0x9066104c,
65 .irq_type = IRQ_TYPE_EDGE_RISING,
66 .class = PCI_CLASS_NETWORK_OTHER,
69 { .offset = 0x790, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
70 { .offset = 0x794, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
71 { .offset = 0x740, .value = 0 },
72 { .offset = 0x744, .value = 0x00010000 },
73 { .offset = 0x764, .value = 0x00010000 },
78 static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
80 static struct resource vlynq_io_resource = {
83 .name = "pci IO space",
84 .flags = IORESOURCE_IO
87 static struct resource vlynq_mem_resource = {
90 .name = "pci memory space",
91 .flags = IORESOURCE_MEM
94 static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
97 struct vlynq_pci_private *priv = dev->priv;
98 u32 ret = dev->mem_start;
99 if (!priv->config->rx_mapping[res].size) return 0;
100 for (i = 0; i < res; i++)
101 ret += priv->config->rx_mapping[i].size;
106 static inline u32 vlynq_read(u32 val, int size) {
116 static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
118 struct vlynq_device *dev;
119 struct vlynq_pci_private *priv;
120 int resno, slot = PCI_SLOT(devfn);
122 if ((size == 2) && (where & 1))
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124 else if ((size == 4) && (where & 3))
125 return PCIBIOS_BAD_REGISTER_NUMBER;
127 if (slot >= VLYNQ_PCI_SLOTS)
128 return PCIBIOS_DEVICE_NOT_FOUND;
132 if (!dev || (PCI_FUNC(devfn) > 0))
133 return PCIBIOS_DEVICE_NOT_FOUND;
139 *val = vlynq_read(priv->config->chip, size);
142 *val = priv->config->chip & 0xffff;
144 *val = priv->command;
146 /* *val = PCI_STATUS_CAP_LIST;*/
149 case PCI_CLASS_REVISION:
150 *val = priv->config->class;
152 case PCI_LATENCY_TIMER:
153 *val = priv->latency;
155 case PCI_HEADER_TYPE:
156 *val = PCI_HEADER_TYPE_NORMAL;
158 case PCI_CACHE_LINE_SIZE:
159 *val = priv->cache_line;
161 case PCI_BASE_ADDRESS_0:
162 case PCI_BASE_ADDRESS_1:
163 case PCI_BASE_ADDRESS_2:
164 case PCI_BASE_ADDRESS_3:
165 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
166 if (priv->sz_mask & (1 << resno)) {
167 priv->sz_mask &= ~(1 << resno);
168 *val = priv->config->rx_mapping[resno].size;
170 *val = vlynq_get_mapped(dev, resno);
173 case PCI_BASE_ADDRESS_4:
174 case PCI_BASE_ADDRESS_5:
175 case PCI_SUBSYSTEM_VENDOR_ID:
176 case PCI_SUBSYSTEM_ID:
177 case PCI_ROM_ADDRESS:
178 case PCI_INTERRUPT_LINE:
179 case PCI_CARDBUS_CIS:
180 case PCI_CAPABILITY_LIST:
183 case PCI_INTERRUPT_PIN:
187 printk("%s: Read of unknown register 0x%x (size %d)\n",
188 dev->dev.bus_id, where, size);
189 return PCIBIOS_BAD_REGISTER_NUMBER;
191 return PCIBIOS_SUCCESSFUL;
194 static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
196 struct vlynq_device *dev;
197 struct vlynq_pci_private *priv;
198 int resno, slot = PCI_SLOT(devfn);
200 if ((size == 2) && (where & 1))
201 return PCIBIOS_BAD_REGISTER_NUMBER;
202 else if ((size == 4) && (where & 3))
203 return PCIBIOS_BAD_REGISTER_NUMBER;
205 if (slot >= VLYNQ_PCI_SLOTS)
206 return PCIBIOS_DEVICE_NOT_FOUND;
210 if (!dev || (PCI_FUNC(devfn) > 0))
211 return PCIBIOS_DEVICE_NOT_FOUND;
219 case PCI_CLASS_REVISION:
220 case PCI_HEADER_TYPE:
221 case PCI_CACHE_LINE_SIZE:
222 case PCI_SUBSYSTEM_VENDOR_ID:
223 case PCI_SUBSYSTEM_ID:
224 case PCI_INTERRUPT_LINE:
225 case PCI_INTERRUPT_PIN:
226 case PCI_CARDBUS_CIS:
227 case PCI_CAPABILITY_LIST:
228 return PCIBIOS_FUNC_NOT_SUPPORTED;
231 case PCI_LATENCY_TIMER:
234 case PCI_BASE_ADDRESS_0:
235 case PCI_BASE_ADDRESS_1:
236 case PCI_BASE_ADDRESS_2:
237 case PCI_BASE_ADDRESS_3:
238 if (val == 0xffffffff) {
239 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
240 priv->sz_mask |= (1 << resno);
243 case PCI_BASE_ADDRESS_4:
244 case PCI_BASE_ADDRESS_5:
245 case PCI_ROM_ADDRESS:
248 printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
249 dev->dev.bus_id, where, size, val);
250 return PCIBIOS_BAD_REGISTER_NUMBER;
252 return PCIBIOS_SUCCESSFUL;
255 static struct pci_ops vlynq_pci_ops = {
260 static struct pci_controller vlynq_controller = {
261 .pci_ops = &vlynq_pci_ops,
262 .io_resource = &vlynq_io_resource,
263 .mem_resource = &vlynq_mem_resource,
266 static int vlynq_pci_probe(struct vlynq_device *dev)
270 struct vlynq_pci_private *priv;
271 struct vlynq_mapping mapping[4] = { { 0, }, };
272 struct vlynq_pci_config *config = NULL;
274 result = vlynq_set_local_irq(dev, 31);
278 result = vlynq_set_remote_irq(dev, 30);
282 result = vlynq_device_enable(dev);
286 chip_id = vlynq_remote_id(dev);
287 for (i = 0; i < ARRAY_SIZE(known_devices); i++)
288 if (chip_id == known_devices[i].chip_id)
289 config = &known_devices[i];
292 printk("vlynq-pci: skipping unknown device "
293 "%04x:%04x at %s\n", chip_id >> 16,
294 chip_id & 0xffff, dev->dev.bus_id);
299 printk("vlynq-pci: attaching device %s at %s\n",
300 config->name, dev->dev.bus_id);
302 priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
304 printk(KERN_ERR "%s: failed to allocate private data\n",
310 memset(priv, 0, sizeof(struct vlynq_pci_private));
312 priv->cache_line = 32;
313 priv->config = config;
315 mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
316 mapping[0].size = 0x02000000;
317 vlynq_set_local_mapping(dev, dev->mem_start, mapping);
318 vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
320 set_irq_type(vlynq_virq_to_irq(dev, config->irq), config->irq_type);
322 addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
324 printk(KERN_ERR "%s: failed to remap io memory\n",
330 for (i = 0; i < config->num_regs; i++)
331 *(volatile u32 *)(addr + config->regs[i].offset) =
332 config->regs[i].value;
335 for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
345 vlynq_device_disable(dev);
350 static int vlynq_pci_remove(struct vlynq_device *dev)
353 struct vlynq_pci_private *priv = dev->priv;
355 for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
359 vlynq_device_disable(dev);
365 static struct vlynq_driver vlynq_pci = {
366 .name = "PCI over VLYNQ emulation",
367 .probe = vlynq_pci_probe,
368 .remove = vlynq_pci_remove,
371 int vlynq_pci_init(void)
374 res = vlynq_register_driver(&vlynq_pci);
378 register_pci_controller(&vlynq_controller);
383 int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
385 struct vlynq_device *dev;
386 struct vlynq_pci_private *priv;
395 return vlynq_virq_to_irq(dev, priv->config->irq);
398 /* Do platform specific device initialization at pci_enable_device() time */
399 int pcibios_plat_dev_init(struct pci_dev *dev)