4 * Copyright (C) 2007 OpenWrt.org
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/init.h>
22 #include <linux/types.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <asm/addrspace.h>
27 #include <asm/ar7/ar7.h>
29 #define BOOT_PLL_SOURCE_MASK 0x3
30 #define CPU_PLL_SOURCE_SHIFT 16
31 #define BUS_PLL_SOURCE_SHIFT 14
32 #define USB_PLL_SOURCE_SHIFT 18
33 #define DSP_PLL_SOURCE_SHIFT 22
34 #define BOOT_PLL_SOURCE_AFE 0
35 #define BOOT_PLL_SOURCE_BUS 0
36 #define BOOT_PLL_SOURCE_REF 1
37 #define BOOT_PLL_SOURCE_XTAL 2
38 #define BOOT_PLL_SOURCE_CPU 3
39 #define BOOT_PLL_BYPASS 0x00000020
40 #define BOOT_PLL_ASYNC_MODE 0x02000000
41 #define BOOT_PLL_2TO1_MODE 0x00008000
43 struct tnetd7300_clock {
45 #define PREDIV_MASK 0x001f0000
46 #define PREDIV_SHIFT 16
47 #define POSTDIV_MASK 0x0000001f
50 #define MUL_MASK 0x0000f000
52 #define PLL_MODE_MASK 0x00000001
53 #define PLL_NDIV 0x00000800
54 #define PLL_DIV 0x00000002
55 #define PLL_STATUS 0x00000001
57 } __attribute__ ((packed));
59 struct tnetd7300_clocks {
60 struct tnetd7300_clock bus;
61 struct tnetd7300_clock cpu;
62 struct tnetd7300_clock usb;
63 struct tnetd7300_clock dsp;
64 } __attribute__ ((packed));
66 struct tnetd7200_clock {
69 #define DIVISOR_ENABLE_MASK 0x00008000
80 struct tnetd7200_clocks {
81 struct tnetd7200_clock cpu;
82 struct tnetd7200_clock dsp;
83 struct tnetd7200_clock usb;
86 int ar7_afe_clock = 35328000;
87 int ar7_ref_clock = 25000000;
88 int ar7_xtal_clock = 24000000;
90 int ar7_cpu_clock = 150000000;
91 EXPORT_SYMBOL(ar7_cpu_clock);
92 int ar7_bus_clock = 125000000;
93 EXPORT_SYMBOL(ar7_bus_clock);
94 int ar7_dsp_clock = 0;
95 EXPORT_SYMBOL(ar7_dsp_clock);
97 static int gcd(int x, int y)
100 return (x % y) ? gcd(y, x % y) : y;
101 return (y % x) ? gcd(x, y % x) : x;
104 static inline int ABS(int x)
106 return (x >= 0) ? x : -x;
109 static void approximate(int base, int target, int *prediv,
110 int *postdiv, int *mul)
112 int i, j, k, freq, res = target;
113 for (i = 1; i <= 16; i++) {
114 for (j = 1; j <= 32; j++) {
115 for (k = 1; k <= 32; k++) {
116 freq = ABS(base / j * i / k - target);
128 static void calculate(int base, int target, int *prediv, int *postdiv,
131 int tmp_gcd, tmp_base, tmp_freq;
133 for (*prediv = 1; *prediv <= 32; (*prediv)++) {
134 tmp_base = base / *prediv;
135 tmp_gcd = gcd(target, tmp_base);
136 *mul = target / tmp_gcd;
137 *postdiv = tmp_base / tmp_gcd;
138 if ((*mul < 1) || (*mul >= 16))
140 if ((*postdiv > 0) & (*postdiv <= 32))
144 if (base / (*prediv) * (*mul) / (*postdiv) != target) {
145 approximate(base, target, prediv, postdiv, mul);
146 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
148 "Adjusted requested frequency %d to %d\n",
152 printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
153 *prediv, *postdiv, *mul);
156 static int tnetd7300_dsp_clock(void)
159 u8 rev = ar7_chip_rev();
160 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
161 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
162 if (didr2 & (1 << 23))
164 if ((rev >= 0x23) && (rev != 0x57))
166 if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
172 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
173 u32 *bootcr, u32 bus_clock)
176 int base_clock = ar7_ref_clock;
177 u32 ctrl = clock->ctrl;
178 u32 pll = clock->pll;
179 int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
180 int postdiv = (ctrl & POSTDIV_MASK) + 1;
181 int divisor = prediv * postdiv;
182 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
184 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
185 case BOOT_PLL_SOURCE_BUS:
186 base_clock = bus_clock;
188 case BOOT_PLL_SOURCE_REF:
189 base_clock = ar7_ref_clock;
191 case BOOT_PLL_SOURCE_XTAL:
192 base_clock = ar7_xtal_clock;
194 case BOOT_PLL_SOURCE_CPU:
195 base_clock = ar7_cpu_clock;
199 if (*bootcr & BOOT_PLL_BYPASS)
200 return base_clock / divisor;
202 if ((pll & PLL_MODE_MASK) == 0)
203 return (base_clock >> (mul / 16 + 1)) / divisor;
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
206 product = (mul & 1) ?
207 (base_clock * mul) >> 1 :
208 (base_clock * (mul - 1)) >> 2;
209 return product / divisor;
213 return base_clock / divisor;
215 return base_clock * mul / divisor;
218 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
219 u32 *bootcr, u32 frequency)
222 int prediv, postdiv, mul;
223 int base_clock = ar7_bus_clock;
225 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
226 case BOOT_PLL_SOURCE_BUS:
227 base_clock = ar7_bus_clock;
229 case BOOT_PLL_SOURCE_REF:
230 base_clock = ar7_ref_clock;
232 case BOOT_PLL_SOURCE_XTAL:
233 base_clock = ar7_xtal_clock;
235 case BOOT_PLL_SOURCE_CPU:
236 base_clock = ar7_cpu_clock;
240 calculate(base_clock, frequency, &prediv, &postdiv, &mul);
242 clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
247 } while (status & PLL_STATUS);
248 clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
252 static void __init tnetd7300_init_clocks(void)
254 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
255 struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
257 ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
258 &clocks->bus, bootcr,
261 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
262 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
264 bootcr, ar7_afe_clock);
266 ar7_cpu_clock = ar7_bus_clock;
269 tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
272 if (ar7_dsp_clock == 250000000)
273 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
274 bootcr, ar7_dsp_clock);
280 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
281 u32 *bootcr, u32 bus_clock)
283 int divisor = ((clock->prediv & 0x1f) + 1) *
284 ((clock->postdiv & 0x1f) + 1);
286 if (*bootcr & BOOT_PLL_BYPASS)
287 return base / divisor;
289 return base * ((clock->mul & 0xf) + 1) / divisor;
292 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
293 u32 *bootcr, u32 frequency)
296 int prediv, postdiv, mul;
298 calculate(base, frequency, &prediv, &postdiv, &mul);
301 clock->prediv = DIVISOR_ENABLE_MASK | prediv;
305 status = clock->status;
306 } while (status & PLL_STATUS);
307 clock->postdiv = DIVISOR_ENABLE_MASK | postdiv;
311 status = clock->status;
312 } while (status & PLL_STATUS);
316 static void __init tnetd7200_init_clocks(void)
318 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
319 struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
321 ar7_cpu_clock = tnetd7200_get_clock(ar7_afe_clock,
323 bootcr, ar7_afe_clock);
325 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
326 ar7_bus_clock = 125000000;
328 if (*bootcr & BOOT_PLL_2TO1_MODE) {
329 ar7_bus_clock = ar7_cpu_clock / 2;
331 ar7_bus_clock = ar7_cpu_clock;
335 tnetd7200_set_clock(ar7_ref_clock * 5, &clocks->usb,
338 if (ar7_dsp_clock == 250000000)
339 tnetd7200_set_clock(ar7_ref_clock, &clocks->dsp,
340 bootcr, ar7_dsp_clock);
346 void __init ar7_init_clocks(void)
348 switch (ar7_chip_id()) {
350 tnetd7200_init_clocks();
353 #warning FIXME: check revision
354 ar7_dsp_clock = 250000000;
355 tnetd7200_init_clocks();
358 ar7_dsp_clock = tnetd7300_dsp_clock();
359 tnetd7300_init_clocks();