1 Index: linux-2.6.32.7/arch/mips/ar7/platform.c
2 ===================================================================
3 --- linux-2.6.32.7.orig/arch/mips/ar7/platform.c 2010-01-29 00:06:20.000000000 +0100
4 +++ linux-2.6.32.7/arch/mips/ar7/platform.c 2010-02-04 14:40:23.000000000 +0100
9 +static struct resource cpmac_low_res_titan[] = {
12 + .flags = IORESOURCE_MEM,
13 + .start = TITAN_REGS_MAC0,
14 + .end = TITAN_REGS_MAC0 + 0x7ff,
18 + .flags = IORESOURCE_IRQ,
24 +static struct resource cpmac_high_res_titan[] = {
27 + .flags = IORESOURCE_MEM,
28 + .start = TITAN_REGS_MAC1,
29 + .end = TITAN_REGS_MAC1 + 0x7ff,
33 + .flags = IORESOURCE_IRQ,
39 static struct resource vlynq_low_res[] = {
46 +static struct resource vlynq_low_res_titan[] = {
49 + .flags = IORESOURCE_MEM,
50 + .start = TITAN_REGS_VLYNQ0,
51 + .end = TITAN_REGS_VLYNQ0 + 0xff,
55 + .flags = IORESOURCE_IRQ,
61 + .flags = IORESOURCE_MEM,
62 + .start = 0x0c000000,
67 + .flags = IORESOURCE_IRQ,
73 +static struct resource vlynq_high_res_titan[] = {
76 + .flags = IORESOURCE_MEM,
77 + .start = TITAN_REGS_VLYNQ1,
78 + .end = TITAN_REGS_VLYNQ1 + 0xff,
82 + .flags = IORESOURCE_IRQ,
88 + .flags = IORESOURCE_MEM,
89 + .start = 0x40000000,
94 + .flags = IORESOURCE_IRQ,
100 static struct resource usb_res[] = {
104 .phy_mask = 0x7fffffff,
107 +static struct plat_cpmac_data cpmac_low_data_titan = {
110 + .phy_mask = 0x40000000,
113 +static struct plat_cpmac_data cpmac_high_data_titan = {
116 + .phy_mask = 0x80000000,
119 static struct plat_vlynq_data vlynq_low_data = {
121 .ops.off = vlynq_off,
126 +static struct plat_vlynq_data vlynq_low_data_titan = {
127 + .ops.on = vlynq_on,
128 + .ops.off = vlynq_off,
133 +static struct plat_vlynq_data vlynq_high_data_titan = {
134 + .ops.on = vlynq_on,
135 + .ops.off = vlynq_off,
140 static struct platform_device physmap_flash = {
142 .name = "physmap-flash",
144 .num_resources = ARRAY_SIZE(cpmac_high_res),
147 +static struct platform_device cpmac_low_titan = {
151 + .dma_mask = &cpmac_dma_mask,
152 + .coherent_dma_mask = DMA_BIT_MASK(32),
153 + .platform_data = &cpmac_low_data_titan,
155 + .resource = cpmac_low_res_titan,
156 + .num_resources = ARRAY_SIZE(cpmac_low_res_titan),
159 +static struct platform_device cpmac_high_titan = {
163 + .dma_mask = &cpmac_dma_mask,
164 + .coherent_dma_mask = DMA_BIT_MASK(32),
165 + .platform_data = &cpmac_high_data_titan,
167 + .resource = cpmac_high_res_titan,
168 + .num_resources = ARRAY_SIZE(cpmac_high_res_titan),
171 static struct platform_device vlynq_low = {
175 .num_resources = ARRAY_SIZE(vlynq_high_res),
178 +static struct platform_device vlynq_low_titan = {
181 + .dev.platform_data = &vlynq_low_data_titan,
182 + .resource = vlynq_low_res_titan,
183 + .num_resources = ARRAY_SIZE(vlynq_low_res_titan),
186 +static struct platform_device vlynq_high_titan = {
189 + .dev.platform_data = &vlynq_high_data_titan,
190 + .resource = vlynq_high_res_titan,
191 + .num_resources = ARRAY_SIZE(vlynq_high_res_titan),
195 static struct gpio_led default_leds[] = {
201 +static struct gpio_led titan_leds[] = {
202 + { .name = "status", .gpio = 8, .active_low = 1, },
203 + { .name = "wifi", .gpio = 13, .active_low = 1, },
206 static struct gpio_led dsl502t_leds[] = {
210 } else if (strstr(prid, "DG834")) {
211 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
212 ar7_led_data.leds = dg834g_leds;
213 + } else if (strstr(prid, "CYWM")) {
214 + ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
215 + ar7_led_data.leds = titan_leds;
219 @@ -541,14 +699,18 @@
223 - ar7_device_disable(vlynq_low_data.reset_bit);
224 - res = platform_device_register(&vlynq_low);
225 + ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit :
226 + vlynq_low_data.reset_bit);
227 + res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan :
232 if (ar7_has_high_vlynq()) {
233 - ar7_device_disable(vlynq_high_data.reset_bit);
234 - res = platform_device_register(&vlynq_high);
235 + ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit :
236 + vlynq_high_data.reset_bit);
237 + res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan :
242 Index: linux-2.6.32.7/arch/mips/ar7/gpio.c
243 ===================================================================
244 --- linux-2.6.32.7.orig/arch/mips/ar7/gpio.c 2010-01-29 00:06:20.000000000 +0100
245 +++ linux-2.6.32.7/arch/mips/ar7/gpio.c 2010-02-04 14:33:24.000000000 +0100
248 #include <asm/mach-ar7/gpio.h>
250 -static const char *ar7_gpio_list[AR7_GPIO_MAX];
251 +static const char *ar7_gpio_list[TITAN_GPIO_MAX];
253 int gpio_request(unsigned gpio, const char *label)
255 - if (gpio >= AR7_GPIO_MAX)
256 + if (gpio >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX))
259 if (ar7_gpio_list[gpio])
260 Index: linux-2.6.32.7/arch/mips/ar7/setup.c
261 ===================================================================
262 --- linux-2.6.32.7.orig/arch/mips/ar7/setup.c 2010-01-29 00:06:20.000000000 +0100
263 +++ linux-2.6.32.7/arch/mips/ar7/setup.c 2010-02-04 14:33:24.000000000 +0100
265 #include <asm/reboot.h>
266 #include <asm/mach-ar7/ar7.h>
267 #include <asm/mach-ar7/prom.h>
268 +#include <asm/mach-ar7/gpio.h>
270 +static int titan_variant;
272 static void ar7_machine_restart(char *command)
275 return "TI AR7 (TNETD7100)";
277 return "TI AR7 (TNETD7200)";
278 + case AR7_CHIP_TITAN:
279 + titan_variant = ar7_init_titan_variant();
280 + switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) {
281 + case TITAN_CHIP_1050:
282 + return "TI AR7 (TNETV1050)";
283 + case TITAN_CHIP_1055:
284 + return "TI AR7 (TNETV1055)";
285 + case TITAN_CHIP_1056:
286 + return "TI AR7 (TNETV1056)";
287 + case TITAN_CHIP_1060:
288 + return "TI AR7 (TNETV1060)";
291 return "TI AR7 (Unknown)";
293 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h
294 ===================================================================
295 --- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/ar7.h 2010-01-29 00:06:20.000000000 +0100
296 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h 2010-02-04 14:33:24.000000000 +0100
298 #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
299 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
301 +#define TITAN_REGS_MAC0 (0x08640000)
302 +#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800)
303 +#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
304 +#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
306 #define AR7_RESET_PEREPHERIAL 0x0
307 #define AR7_RESET_SOFTWARE 0x4
308 #define AR7_RESET_STATUS 0x8
310 #define AR7_RESET_BIT_MDIO 22
311 #define AR7_RESET_BIT_EPHY 26
313 +#define TITAN_RESET_BIT_EPHY1 28
315 /* GPIO control registers */
316 #define AR7_GPIO_INPUT 0x0
317 #define AR7_GPIO_OUTPUT 0x4
318 #define AR7_GPIO_DIR 0x8
319 #define AR7_GPIO_ENABLE 0xc
320 +#define TITAN_GPIO_INPUT_0 0x0
321 +#define TITAN_GPIO_INPUT_1 0x4
322 +#define TITAN_GPIO_OUTPUT_0 0x8
323 +#define TITAN_GPIO_OUTPUT_1 0xc
324 +#define TITAN_GPIO_DIR_0 0x10
325 +#define TITAN_GPIO_DIR_1 0x14
326 +#define TITAN_GPIO_ENBL_0 0x18
327 +#define TITAN_GPIO_ENBL_1 0x1c
329 #define AR7_CHIP_7100 0x18
330 #define AR7_CHIP_7200 0x2b
331 #define AR7_CHIP_7300 0x05
332 +#define AR7_CHIP_TITAN 0x07
333 +#define TITAN_CHIP_1050 0x0f
334 +#define TITAN_CHIP_1055 0x0e
335 +#define TITAN_CHIP_1056 0x0d
336 +#define TITAN_CHIP_1060 0x07
339 #define AR7_IRQ_UART0 15
342 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
344 +static inline int ar7_is_titan(void)
346 + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
350 static inline u16 ar7_chip_id(void)
352 - return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
353 + return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
354 + KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
357 static inline u8 ar7_chip_rev(void)
359 - return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
360 + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
361 + 0x14))) >> 16) & 0xff;
364 static inline int ar7_cpu_freq(void)
365 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h
366 ===================================================================
367 --- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/gpio.h 2010-01-29 00:06:20.000000000 +0100
368 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h 2010-02-04 14:39:21.000000000 +0100
370 #define __AR7_GPIO_H__
372 #include <asm/mach-ar7/ar7.h>
373 +#ifndef __AR7_TITAN_H__
374 +#include <asm/mach-ar7/titan.h>
377 #define AR7_GPIO_MAX 32
378 +#define TITAN_GPIO_MAX 51
380 extern int gpio_request(unsigned gpio, const char *label);
381 extern void gpio_free(unsigned gpio);
383 /* Common GPIO layer */
384 -static inline int gpio_get_value(unsigned gpio)
385 +static inline int gpio_get_value_ar7(unsigned gpio)
387 void __iomem *gpio_in =
388 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
390 return readl(gpio_in) & (1 << gpio);
393 -static inline void gpio_set_value(unsigned gpio, int value)
394 +static inline int gpio_get_value_titan(unsigned gpio)
396 + void __iomem *gpio_in0 =
397 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
398 + void __iomem *gpio_in1 =
399 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
401 + return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
404 +static inline int gpio_get_value(unsigned gpio)
406 + return ar7_is_titan() ? gpio_get_value_titan(gpio) :
407 + gpio_get_value_ar7(gpio);
410 +static inline void gpio_set_value_ar7(unsigned gpio, int value)
412 void __iomem *gpio_out =
413 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
415 writel(tmp, gpio_out);
418 -static inline int gpio_direction_input(unsigned gpio)
419 +static inline void gpio_set_value_titan(unsigned gpio, int value)
421 + void __iomem *gpio_out0 =
422 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
423 + void __iomem *gpio_out1 =
424 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
427 + tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
429 + tmp |= 1 << (gpio & 0x1f);
430 + writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
433 +static inline void gpio_set_value(unsigned gpio, int value)
435 + if (ar7_is_titan())
436 + gpio_set_value_titan(gpio, value);
438 + gpio_set_value_ar7(gpio, value);
441 +static inline int gpio_direction_input_ar7(unsigned gpio)
443 void __iomem *gpio_dir =
444 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
449 -static inline int gpio_direction_output(unsigned gpio, int value)
450 +static inline int gpio_direction_input_titan(unsigned gpio)
452 + void __iomem *gpio_dir0 =
453 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
454 + void __iomem *gpio_dir1 =
455 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
457 + if (gpio >= TITAN_GPIO_MAX)
460 + writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
461 + gpio >> 5 ? gpio_dir1 : gpio_dir0);
466 +static inline int gpio_direction_input(unsigned gpio)
468 + return ar7_is_titan() ? gpio_direction_input_titan(gpio) :
469 + gpio_direction_input_ar7(gpio);
472 +static inline int gpio_direction_output_ar7(unsigned gpio, int value)
474 void __iomem *gpio_dir =
475 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
480 +static inline int gpio_direction_output_titan(unsigned gpio, int value)
482 + void __iomem *gpio_dir0 =
483 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
484 + void __iomem *gpio_dir1 =
485 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
487 + if (gpio >= TITAN_GPIO_MAX)
490 + gpio_set_value_titan(gpio, value);
491 + writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
492 + (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
497 +static inline int gpio_direction_output(unsigned gpio, int value)
499 + return ar7_is_titan() ? gpio_direction_output_titan(gpio, value) :
500 + gpio_direction_output_ar7(gpio, value);
503 static inline int gpio_to_irq(unsigned gpio)
509 /* Board specific GPIO functions */
510 -static inline int ar7_gpio_enable(unsigned gpio)
511 +static inline int ar7_gpio_enable_ar7(unsigned gpio)
513 void __iomem *gpio_en =
514 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
519 -static inline int ar7_gpio_disable(unsigned gpio)
520 +static inline int ar7_gpio_enable_titan(unsigned gpio)
522 + void __iomem *gpio_en0 =
523 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
524 + void __iomem *gpio_en1 =
525 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
527 + writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
528 + gpio >> 5 ? gpio_en1 : gpio_en0);
533 +static inline int ar7_gpio_enable(unsigned gpio)
535 + return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
536 + ar7_gpio_enable_ar7(gpio);
539 +static inline int ar7_gpio_disable_ar7(unsigned gpio)
541 void __iomem *gpio_en =
542 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
547 +static inline int ar7_gpio_disable_titan(unsigned gpio)
549 + void __iomem *gpio_en0 =
550 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
551 + void __iomem *gpio_en1 =
552 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
554 + writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
555 + gpio >> 5 ? gpio_en1 : gpio_en0);
560 +static inline int ar7_gpio_disable(unsigned gpio)
562 + return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
563 + ar7_gpio_disable_ar7(gpio);
566 +static inline int ar7_init_titan_variant(void)
568 + /*UINT32 new_val;*/
571 + /* set GPIO 44 - 47 as input */
572 + /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
573 + /*define titan_gpio_ctrl in titan.h*/
574 + titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
575 + titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
576 + titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
577 + titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
579 + /* read GPIO to get Titan variant type */
581 + titan_sysGpioInValue( &new_val, 1 );
588 + case TITAN_CHIP_1050:
589 + case TITAN_CHIP_1055:
590 + case TITAN_CHIP_1056:
591 + case TITAN_CHIP_1060:
597 + /* In case we get an invalid value, return the default Titan chip */
598 + return TITAN_CHIP_1050;
601 #include <asm-generic/gpio.h>
604 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h
605 ===================================================================
606 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
607 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h 2010-02-04 14:40:44.000000000 +0100
610 + * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
612 + * This program is free software; you can redistribute it and/or modify
613 + * it under the terms of the GNU General Public License as published by
614 + * the Free Software Foundation; either version 2 of the License, or
615 + * (at your option) any later version.
617 + * This program is distributed in the hope that it will be useful,
618 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
619 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
620 + * GNU General Public License for more details.
622 + * You should have received a copy of the GNU General Public License
623 + * along with this program; if not, write to the Free Software
624 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
626 +#ifndef __AR7_TITAN_H__
627 +#define __AR7_TITAN_H__
629 +#include <asm/mach-ar7/gpio.h>
631 +typedef enum TITAN_GPIO_PIN_MODE_tag
633 + FUNCTIONAL_PIN = 0,
635 +} TITAN_GPIO_PIN_MODE_T;
637 +typedef enum TITAN_GPIO_PIN_DIRECTION_tag
639 + GPIO_OUTPUT_PIN = 0,
641 +} TITAN_GPIO_PIN_DIRECTION_T;
643 +/**********************************************************************
645 + **********************************************************************/
655 +static GPIO_CFG gptable[]= {
656 + /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
713 + volatile unsigned int reg[21];
715 +PIN_SEL_REG_ARRAY_T;
719 + unsigned int data_in [2];
720 + unsigned int data_out[2];
721 + unsigned int dir[2];
722 + unsigned int enable[2];
724 +} TITAN_GPIO_CONTROL_T;
726 +#define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/
728 +static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
729 + TITAN_GPIO_PIN_DIRECTION_T pin_direction)
734 + volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
735 + volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
737 + if (gpio_pin > 51 )
740 + gpio_cfg = gptable[gpio_pin];
741 + mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
742 + if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
744 + return(-1); /* Pin have been configured for non GPIO funcs. */
747 + /* Set the pin to be used as GPIO. */
748 + pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
750 + /* Check whether gpio refers to the first GPIO reg or second. */
758 + gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */
760 + gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
763 + gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */
765 + gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
769 +}/* end of function titan_gpio_ctrl */
771 +static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
773 + volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
778 + *in_val = gpio_cntl->data_in[reg_index];