2 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/interrupt.h>
23 #include <asm/irq_cpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/ar7/ar7.h>
27 #define EXCEPT_OFFSET 0x80
28 #define PACE_OFFSET 0xA0
29 #define CHNLS_OFFSET 0x200
31 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
32 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
33 #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
34 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
35 #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
36 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
37 #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
38 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
39 #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
40 #define PIR_OFFSET (0x40)
41 #define MSR_OFFSET (0x44)
42 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
43 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
45 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
47 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
49 static void ar7_unmask_irq(unsigned int irq_nr);
50 static void ar7_mask_irq(unsigned int irq_nr);
51 static void ar7_ack_irq(unsigned int irq_nr);
52 static void ar7_unmask_sec_irq(unsigned int irq_nr);
53 static void ar7_mask_sec_irq(unsigned int irq_nr);
54 static void ar7_ack_sec_irq(unsigned int irq_nr);
55 static void ar7_cascade(void);
56 static void ar7_irq_init(int base);
57 static int ar7_irq_base;
59 static struct irq_chip ar7_irq_type = {
61 .unmask = ar7_unmask_irq,
66 static struct irq_chip ar7_sec_irq_type = {
68 .unmask = ar7_unmask_sec_irq,
69 .mask = ar7_mask_sec_irq,
70 .ack = ar7_ack_sec_irq,
73 static struct irqaction ar7_cascade_action = {
75 .name = "AR7 cascade interrupt"
78 static void ar7_unmask_irq(unsigned int irq)
80 writel(1 << ((irq - ar7_irq_base) % 32),
81 REG(ESR_OFFSET(irq - ar7_irq_base)));
84 static void ar7_mask_irq(unsigned int irq)
86 writel(1 << ((irq - ar7_irq_base) % 32),
87 REG(ECR_OFFSET(irq - ar7_irq_base)));
90 static void ar7_ack_irq(unsigned int irq)
92 writel(1 << ((irq - ar7_irq_base) % 32),
93 REG(CR_OFFSET(irq - ar7_irq_base)));
96 static void ar7_unmask_sec_irq(unsigned int irq)
98 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
101 static void ar7_mask_sec_irq(unsigned int irq)
103 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
106 static void ar7_ack_sec_irq(unsigned int irq)
108 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
111 void __init arch_init_irq(void) {
116 static void __init ar7_irq_init(int base)
120 * Disable interrupts and clear pending
122 writel(0xffffffff, REG(ECR_OFFSET(0)));
123 writel(0xff, REG(ECR_OFFSET(32)));
124 writel(0xffffffff, REG(SEC_ECR_OFFSET));
125 writel(0xffffffff, REG(CR_OFFSET(0)));
126 writel(0xff, REG(CR_OFFSET(32)));
127 writel(0xffffffff, REG(SEC_CR_OFFSET));
131 for (i = 0; i < 40; i++) {
132 writel(i, REG(CHNL_OFFSET(i)));
134 set_irq_chip_and_handler(base + i, &ar7_irq_type,
136 /* Secondary IRQ's */
138 set_irq_chip_and_handler(base + i + 40,
143 setup_irq(2, &ar7_cascade_action);
144 setup_irq(ar7_irq_base, &ar7_cascade_action);
145 set_c0_status(IE_IRQ0);
148 static void ar7_cascade(void)
154 irq = readl(REG(PIR_OFFSET)) & 0x3f;
156 do_IRQ(ar7_irq_base + irq);
160 /* Secondary IRQ's are cascaded through primary '0' */
161 writel(1, REG(CR_OFFSET(irq)));
162 status = readl(REG(SEC_SR_OFFSET));
163 for (i = 0; i < 32; i++) {
165 do_IRQ(ar7_irq_base + i + 40);
171 spurious_interrupt();
174 asmlinkage void plat_irq_dispatch(void)
176 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
177 if (pending & STATUSF_IP7) /* cpu timer */
179 else if (pending & STATUSF_IP2) /* int0 hardware line */
182 spurious_interrupt();