2 * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 #ifndef __AR7_TITAN_H__
19 #define __AR7_TITAN_H__
21 #ifndef __AR7_GPIO_H__
22 #include <asm/ar7/gpio.h>
25 typedef enum TITAN_GPIO_PIN_MODE_tag
29 } TITAN_GPIO_PIN_MODE_T;
31 typedef enum TITAN_GPIO_PIN_DIRECTION_tag
35 } TITAN_GPIO_PIN_DIRECTION_T;
37 /**********************************************************************
39 **********************************************************************/
49 static GPIO_CFG gptable[]= {
50 /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
107 volatile unsigned int reg[21];
113 unsigned int data_in [2];
114 unsigned int data_out[2];
116 unsigned int enable[2];
118 } TITAN_GPIO_CONTROL_T;
120 #define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/
122 static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
123 TITAN_GPIO_PIN_DIRECTION_T pin_direction)
128 volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
129 volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
134 gpio_cfg = gptable[gpio_pin];
135 mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
136 if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
138 return(-1); /* Pin have been configured for non GPIO funcs. */
141 /* Set the pin to be used as GPIO. */
142 pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
144 /* Check whether gpio refers to the first GPIO reg or second. */
152 gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */
154 gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
157 gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */
159 gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
163 }/* end of function titan_gpio_ctrl */
165 static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
167 volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
172 *in_val = gpio_cntl->data_in[reg_index];