4 * ADM5120 PCI Host Controller driver
6 * Copyright (C) 2007 OpenWrt.org
7 * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
9 * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
10 * done by Jeroen Vreeken
11 * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
13 * Jeroen's code was based on the Linux 2.4.xx source codes found in various
14 * tarballs released by Edimax for it's ADM5120 based devices
15 * Copyright (C) ADMtek Incorporated
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published
19 * by the Free Software Foundation.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/pci_ids.h>
30 #include <linux/pci_regs.h>
32 #include <asm/delay.h>
33 #include <asm/bootinfo.h>
35 #include <adm5120_defs.h>
36 #include <adm5120_info.h>
37 #include <adm5120_defs.h>
38 #include <adm5120_platform.h>
43 #define DBG(f, a...) printk(KERN_DEBUG f, ## a)
45 #define DBG(f, a...) do {} while (0)
48 #define PCI_ENABLE 0x80000000
50 /* -------------------------------------------------------------------------*/
52 static unsigned int adm5120_pci_nr_irqs __initdata;
53 static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
55 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
57 /* -------------------------------------------------------------------------*/
59 static inline void write_cfgaddr(u32 addr)
61 __raw_writel((addr | PCI_ENABLE),
62 (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
65 static inline void write_cfgdata(u32 data)
67 __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
70 static inline u32 read_cfgdata(void)
72 return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
75 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
77 return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
81 /* -------------------------------------------------------------------------*/
83 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
89 spin_lock_irqsave(&pci_lock, flags);
91 write_cfgaddr(mkaddr(bus, devfn, where));
92 data = read_cfgdata();
94 DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
95 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
114 DBG(", 0x%08X returned\n", data);
116 spin_unlock_irqrestore(&pci_lock, flags);
118 return PCIBIOS_SUCCESSFUL;
121 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
128 spin_lock_irqsave(&pci_lock, flags);
130 write_cfgaddr(mkaddr(bus, devfn, where));
131 data = read_cfgdata();
133 DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
134 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
139 s = ((where & 3) << 3);
140 data &= ~(0xFF << s);
141 data |= ((val & 0xFF) << s);
144 s = ((where & 2) << 4);
145 data &= ~(0xFFFF << s);
146 data |= ((val & 0xFFFF) << s);
154 DBG(", 0x%08X written\n", data);
156 spin_unlock_irqrestore(&pci_lock, flags);
158 return PCIBIOS_SUCCESSFUL;
161 struct pci_ops adm5120_pci_ops = {
162 .read = pci_config_read,
163 .write = pci_config_write,
166 /* -------------------------------------------------------------------------*/
168 static void adm5120_pci_fixup(struct pci_dev *dev)
173 /* setup COMMAND register */
174 pci_write_config_word(dev, PCI_COMMAND,
175 (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
177 /* setup CACHE_LINE_SIZE register */
178 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
181 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
182 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
188 /* -------------------------------------------------------------------------*/
190 void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
191 struct adm5120_pci_irq *map)
193 adm5120_pci_nr_irqs = nr_irqs;
194 adm5120_pci_irq_map = map;
197 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
202 if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
203 printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
207 if (slot < 1 || slot > 3) {
208 printk(KERN_ALERT "PCI: slot number %u is not supported\n",
213 for (i = 0; i < adm5120_pci_nr_irqs; i++) {
214 if ((adm5120_pci_irq_map[i].slot == slot)
215 && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
216 && (adm5120_pci_irq_map[i].pin == pin)) {
217 irq = adm5120_pci_irq_map[i].irq;
223 printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
224 pci_name((struct pci_dev *)dev), pin);
226 printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
227 pci_name((struct pci_dev *)dev), pin, irq);
234 int pcibios_plat_dev_init(struct pci_dev *dev)
239 /* -------------------------------------------------------------------------*/
241 static struct resource pci_io_resource = {
242 .name = "ADM5120 PCI I/O",
243 .start = ADM5120_PCIIO_BASE,
244 .end = ADM5120_PCICFG_ADDR-1,
245 .flags = IORESOURCE_IO
248 static struct resource pci_mem_resource = {
249 .name = "ADM5120 PCI MEM",
250 .start = ADM5120_PCIMEM_BASE,
251 .end = ADM5120_PCIIO_BASE-1,
252 .flags = IORESOURCE_MEM
255 static struct pci_controller adm5120_controller = {
256 .pci_ops = &adm5120_pci_ops,
257 .io_resource = &pci_io_resource,
258 .mem_resource = &pci_mem_resource,
261 static int __init adm5120_pci_setup(void)
265 pci_bios = adm5120_has_pci();
267 printk(KERN_INFO "adm5120: system has %sPCI BIOS\n",
268 pci_bios ? "" : "no ");
272 /* Avoid ISA compat ranges. */
273 PCIBIOS_MIN_IO = 0x00000000;
274 PCIBIOS_MIN_MEM = 0x00000000;
276 /* Set I/O resource limits. */
277 ioport_resource.end = 0x1fffffff;
278 iomem_resource.end = 0xffffffff;
280 register_pci_controller(&adm5120_controller);
284 arch_initcall(adm5120_pci_setup);