2 * ADM5120 specific interrupt handlers
4 * Copyright (C) 2007-2008 OpenWrt.org
5 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/version.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/bitops.h>
25 #include <asm/mach-adm5120/adm5120_defs.h>
26 #include <asm/mach-adm5120/adm5120_irq.h>
28 static void adm5120_intc_irq_unmask(unsigned int irq);
29 static void adm5120_intc_irq_mask(unsigned int irq);
30 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
32 static inline void intc_write_reg(unsigned int reg, u32 val)
34 void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
36 __raw_writel(val, base + reg);
39 static inline u32 intc_read_reg(unsigned int reg)
41 void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
43 return __raw_readl(base + reg);
46 static struct irq_chip adm5120_intc_irq_chip = {
48 .unmask = adm5120_intc_irq_unmask,
49 .mask = adm5120_intc_irq_mask,
50 .mask_ack = adm5120_intc_irq_mask,
51 .set_type = adm5120_intc_irq_set_type
54 static struct irqaction adm5120_intc_irq_action = {
56 .name = "cascade [INTC]"
59 static void adm5120_intc_irq_unmask(unsigned int irq)
61 irq -= ADM5120_INTC_IRQ_BASE;
62 intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
65 static void adm5120_intc_irq_mask(unsigned int irq)
67 irq -= ADM5120_INTC_IRQ_BASE;
68 intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
71 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
77 sense = flow_type & (IRQ_TYPE_SENSE_MASK);
80 case IRQ_TYPE_LEVEL_HIGH:
82 case IRQ_TYPE_LEVEL_LOW:
84 case ADM5120_IRQ_GPIO2:
85 case ADM5120_IRQ_GPIO4:
101 case ADM5120_IRQ_GPIO2:
102 case ADM5120_IRQ_GPIO4:
103 mode = intc_read_reg(INTC_REG_INT_MODE);
104 if (sense == IRQ_TYPE_LEVEL_LOW)
105 mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
107 mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
109 intc_write_reg(INTC_REG_INT_MODE, mode);
112 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
113 irq_desc[irq].status |= sense;
120 static void adm5120_intc_irq_dispatch(void)
122 unsigned long status;
125 /* dispatch only one IRQ at a time */
126 status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
129 irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
132 spurious_interrupt();
135 asmlinkage void plat_irq_dispatch(void)
137 unsigned long pending;
139 pending = read_c0_status() & read_c0_cause() & ST0_IM;
141 if (pending & STATUSF_IP7)
142 do_IRQ(ADM5120_IRQ_COUNTER);
143 else if (pending & STATUSF_IP2)
144 adm5120_intc_irq_dispatch();
146 spurious_interrupt();
149 #define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
151 static void __init adm5120_intc_irq_init(void)
155 /* disable all interrupts */
156 intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
158 /* setup all interrupts to generate IRQ instead of FIQ */
159 intc_write_reg(INTC_REG_INT_MODE, 0);
161 /* set active level for all external interrupts to HIGH */
162 intc_write_reg(INTC_REG_INT_LEVEL, 0);
164 /* disable usage of the TEST_SOURCE register */
165 intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
167 for (i = ADM5120_INTC_IRQ_BASE;
168 i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
170 irq_desc[i].status = INTC_IRQ_STATUS;
171 set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
175 setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
178 void __init arch_init_irq(void) {
180 adm5120_intc_irq_init();