package/uboot-lantiq/files/board/arcadyan/board.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Thomas Langer, Ralph Hempel
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <command.h>
  29 #include <netdev.h>
  30 #include <miiphy.h>
  31 #include <asm/addrspace.h>
  32 #include <asm/danube.h>
  33 #include <asm/reboot.h>
  34 #include <asm/io.h>
  35 #if defined(CONFIG_CMD_HTTPD)
  36 #include <httpd.h>
  37 #endif
  38 #if defined(CONFIG_PCI)
  39 #include <pci.h>
  40 #endif
  41 #if defined(CONFIG_AR8216_SWITCH)
  42 #include "athrs26_phy.h"
  43 #endif
  44
  45 extern ulong ifx_get_ddr_hz(void);
  46 extern ulong ifx_get_cpuclk(void);
  47
  48 /* IDs and registers of known external switches */
  49 void _machine_restart(void)
  50 {
  51         *DANUBE_RCU_RST_REQ |=1<<30;
  52 }
  53
  54 #ifdef CONFIG_SYS_RAMBOOT
  55 phys_size_t initdram(int board_type)
  56 {
  57         return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
  58 }
  59 #elif defined(CONFIG_USE_DDR_RAM)
  60 phys_size_t initdram(int board_type)
  61 {
  62         return (CONFIG_SYS_MAX_RAM);
  63 }
  64 #else
  65
  66 static ulong max_sdram_size(void)     /* per Chip Select */
  67 {
  68         /* The only supported SDRAM data width is 16bit.
  69          */
  70 #define CFG_DW  4
  71
  72         /* The only supported number of SDRAM banks is 4.
  73          */
  74 #define CFG_NB  4
  75
  76         ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
  77         int   cols   = cfgpb0 & 0xF;
  78         int   rows   = (cfgpb0 & 0xF0) >> 4;
  79         ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
  80
  81         return size;
  82 }
  83
  84 /*
  85  * Check memory range for valid RAM. A simple memory test determines
  86  * the actually available RAM size between addresses `base' and
  87  * `base + maxsize'.
  88  */
  89
  90 static long int dram_size(long int *base, long int maxsize)
  91 {
  92         volatile long int *addr;
  93         ulong cnt, val;
  94         ulong save[32];                 /* to make test non-destructive */
  95         unsigned char i = 0;
  96
  97         for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
  98                 addr = base + cnt;              /* pointer arith! */
  99
 100                 save[i++] = *addr;
 101                 *addr = ~cnt;
 102         }
 103
 104         /* write 0 to base address */
 105         addr = base;
 106         save[i] = *addr;
 107         *addr = 0;
 108
 109         /* check at base address */
 110         if ((val = *addr) != 0) {
 111                 *addr = save[i];
 112                 return (0);
 113         }
 114
 115         for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
 116                 addr = base + cnt;              /* pointer arith! */
 117
 118                 val = *addr;
 119                 *addr = save[--i];
 120
 121                 if (val != (~cnt)) {
 122                         return (cnt * sizeof (long));
 123                 }
 124         }
 125         return (maxsize);
 126 }
 127
 128 phys_size_t initdram(int board_type)
 129 {
 130         int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
 131         ulong size, max_size       = 0;
 132         ulong our_address;
 133
 134         /* load t9 into our_address */
 135         asm volatile ("move %0, $25" : "=r" (our_address) :);
 136
 137         /* Can't probe for RAM size unless we are running from Flash.
 138          * find out whether running from DRAM or Flash.
 139          */
 140         if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 141         {
 142                 return max_sdram_size();
 143         }
 144
 145         for (cols = 0x8; cols <= 0xC; cols++)
 146         {
 147                 for (rows = 0xB; rows <= 0xD; rows++)
 148                 {
 149                         *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 150                                                   (rows << 4) | cols;
 151                         size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 152                                                   max_sdram_size());
 153
 154                         if (size > max_size)
 155                         {
 156                                 best_val = *DANUBE_SDRAM_MC_CFGPB0;
 157                                 max_size = size;
 158                         }
 159                 }
 160         }
 161
 162         *DANUBE_SDRAM_MC_CFGPB0 = best_val;
 163         return max_size;
 164 }
 165 #endif
 166
 167 static void gpio_default(void)
 168 {
 169 #ifdef CONFIG_SWITCH_PORT0
 170         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 171         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 172         *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
 173         *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
 174         *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
 175 #elif defined(CONFIG_SWITCH_PORT1)
 176         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 177         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 178         *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
 179         *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
 180         *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
 181 #endif
 182 #ifdef CONFIG_EBU_GPIO
 183         {
 184                 int i = 0;
 185                 printf ("bring up ebu gpio\n");
 186                 *DANUBE_EBU_BUSCON1 = 0x1e7ff;
 187                 *DANUBE_EBU_ADDSEL1 = 0x14000001;
 188
 189                 *((volatile u16*)0xb4000000) = 0x0;
 190                 for(i = 0; i < 1000; i++)
 191                         udelay(1000);
 192                 *((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
 193                 *DANUBE_EBU_BUSCON1 = 0x8001e7ff;
 194         }
 195 #endif
 196 #ifdef CONFIG_BUTTON_PORT0
 197         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 198         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 199         *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 200         if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 201         {
 202                 printf("button is pressed\n");
 203                 setenv("bootdelay", "0");
 204                 setenv("bootcmd", "httpd");
 205         }
 206 #elif defined(CONFIG_BUTTON_PORT1)
 207         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 208         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 209         *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 210         if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 211         {
 212                 printf("button is pressed\n");
 213                 setenv("bootdelay", "0");
 214                 setenv("bootcmd", "httpd");
 215         }
 216 #endif
 217
 218 }
 219
 220 int checkboard (void)
 221 {
 222         unsigned long chipid = *DANUBE_MPS_CHIPID;
 223         int part_num;
 224
 225         puts ("Board: "CONFIG_ARCADYAN"\n");
 226         puts ("SoC: ");
 227
 228         part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
 229         switch (part_num)
 230         {
 231         case 0x129:
 232         case 0x12D:
 233         case 0x12b:
 234                 puts("Danube/Twinpass/Vinax-VE ");
 235                 break;
 236         default:
 237                 printf ("unknown, chip part number 0x%03X ", part_num);
 238                 break;
 239         }
 240         printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
 241
 242         printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
 243         printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
 244
 245
 246         return 0;
 247 }
 248
 249 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 250 int board_early_init_f(void)
 251 {
 252 #ifdef CONFIG_EBU_ADDSEL0
 253         (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
 254 #endif
 255 #ifdef CONFIG_EBU_ADDSEL1
 256         (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
 257 #endif
 258 #ifdef CONFIG_EBU_ADDSEL2
 259         (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
 260 #endif
 261 #ifdef CONFIG_EBU_ADDSEL3
 262         (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
 263 #endif
 264 #ifdef CONFIG_EBU_BUSCON0
 265         (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
 266 #endif
 267 #ifdef CONFIG_EBU_BUSCON1
 268         (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
 269 #endif
 270 #ifdef CONFIG_EBU_BUSCON2
 271         (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
 272 #endif
 273 #ifdef CONFIG_EBU_BUSCON3
 274         (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
 275 #endif
 276
 277         return 0;
 278 }
 279 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 280
 281 #ifdef CONFIG_RTL8306_SWITCH
 282 #define ID_RTL8306      0x5988
 283 static int external_switch_rtl8306(void)
 284 {
 285         unsigned short chipid;
 286         static char * const name = "lq_cpe_eth";
 287
 288         udelay(100000);
 289
 290         puts("\nsearching for rtl8306 switch ... ");
 291         if (miiphy_read(name, 4, 30, &chipid) == 0) {
 292                 if (chipid == ID_RTL8306) {
 293                         puts("found");
 294                         /* set led mode */
 295                         miiphy_write(name, 0, 19, 0xffff);
 296                         /* magic */
 297                         miiphy_write(name, 4, 22, 0x877f);
 298                         puts("\n");
 299                         return 0;
 300                 }
 301                 puts("failed\n");
 302         }
 303         puts("\nno known switch found ... \n");
 304
 305         return 0;
 306 }
 307 #endif
 308
 309 #ifdef CONFIG_AR8216_SWITCH
 310 static int external_switch_ar8216(void)
 311 {
 312         puts("initializing ar8216 switch... ");
 313         if (athrs26_phy_setup(0)==0) {
 314            printf("initialized\n");
 315            return 0;
 316         }
 317         puts("failed ... \n");
 318         return 0;
 319 }
 320 #endif
 321
 322 int board_eth_init(bd_t *bis)
 323 {
 324         gpio_default();
 325
 326 #if defined(CONFIG_IFX_ETOP)
 327         uchar enetaddr[6];
 328         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 329                eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
 330
 331         *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
 332         *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
 333
 334         if (lq_eth_initialize(bis))
 335                 return -1;
 336
 337         *DANUBE_RCU_RST_REQ |=1;
 338         udelay(200000);
 339         *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
 340         udelay(1000);
 341
 342 #ifdef CONFIG_RTL8306_SWITCH
 343         if (external_switch_rtl8306()<0)
 344                 return -1;
 345 #endif
 346 #ifdef CONFIG_AR8216_SWITCH
 347         if (external_switch_ar8216()<0)
 348                 return -1;
 349 #endif
 350 #endif
 351         return 0;
 352 }
 353
 354 #if defined(CONFIG_CMD_HTTPD)
 355 int do_http_upgrade(const unsigned char *data, const ulong size)
 356 {
 357         char buf[128];
 358
 359         if(getenv ("ram_addr") == NULL)
 360                 return -1;
 361         if(getenv ("kernel_addr") == NULL)
 362                 return -1;
 363         /* check the image */
 364         if(run_command("imi ${ram_addr}", 0) < 0) {
 365                 return -1;
 366         }
 367         /* write the image to the flash */
 368         puts("http ugrade ...\n");
 369         sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
 370         return run_command(buf, 0);
 371 }
 372
 373 int do_http_progress(const int state)
 374 {
 375         /* toggle LED's here */
 376         switch(state) {
 377                 case HTTP_PROGRESS_START:
 378                 puts("http start\n");
 379                 break;
 380                 case HTTP_PROGRESS_TIMEOUT:
 381                 puts(".");
 382                 break;
 383                 case HTTP_PROGRESS_UPLOAD_READY:
 384                 puts("http upload ready\n");
 385                 break;
 386                 case HTTP_PROGRESS_UGRADE_READY:
 387                 puts("http ugrade ready\n");
 388                 break;
 389                 case HTTP_PROGRESS_UGRADE_FAILED:
 390                 puts("http ugrade failed\n");
 391                 break;
 392         }
 393         return 0;
 394 }
 395
 396 unsigned long do_http_tmp_address(void)
 397 {
 398         char *s = getenv ("ram_addr");
 399         if (s) {
 400                 ulong tmp = simple_strtoul (s, NULL, 16);
 401                 return tmp;
 402         }
 403         return 0 /*0x80a00000*/;
 404 }
 405
 406 #endif