2 * Copyright (C) 2009-2012
3 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
4 * Luka Perkov <uboot@lukaperkov.net>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/kirkwood.h>
27 #include <asm/arch/mpp.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 int board_early_init_f(void)
35 * default gpio configuration
36 * There are maximum 64 gpios controlled through 2 sets of registers
37 * the below configuration configures mainly initial LED status
39 kw_config_gpio(ICONNECT_OE_VAL_LOW,
41 ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
43 /* Multi-Purpose Pins Functionality configuration */
44 u32 kwmpp_config[] = {
97 kirkwood_mpp_conf(kwmpp_config);
103 /* Boot parameters address */
104 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
109 #ifdef CONFIG_RESET_PHY_R
110 /* Configure and initialize PHY */
115 char *name = "egiga0";
117 if (miiphy_set_current_dev(name))
120 /* command to read PHY dev address */
121 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
122 printf("Err..(%s) could not read PHY dev address\n", __func__);
127 * Enable RGMII delay on Tx and Rx for CPU port
128 * Ref: sec 4.7.2 of chip datasheet
130 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
131 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
132 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
133 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
134 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
137 miiphy_reset(name, devadr);
139 debug("88E1116 Initialized on %s\n", name);
141 #endif /* CONFIG_RESET_PHY_R */