3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/addrspace.h>
27 #include <asm/danube.h>
29 #ifdef DANUBE_USE_DDR_RAM
30 long int initdram(int board_type)
32 return (1024*1024*DANUBE_DDR_RAM_SIZE);
35 extern uint danube_get_cpuclk(void);
37 static ulong max_sdram_size(void) /* per Chip Select */
39 /* The only supported SDRAM data width is 16bit.
43 /* The only supported number of SDRAM banks is 4.
47 ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
48 int cols = cfgpb0 & 0xF;
49 int rows = (cfgpb0 & 0xF0) >> 4;
50 ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
56 * Check memory range for valid RAM. A simple memory test determines
57 * the actually available RAM size between addresses `base' and
61 static long int dram_size(long int *base, long int maxsize)
63 volatile long int *addr;
65 ulong save[32]; /* to make test non-destructive */
68 for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
69 addr = base + cnt; /* pointer arith! */
75 /* write 0 to base address */
80 /* check at base address */
81 if ((val = *addr) != 0) {
86 for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
87 addr = base + cnt; /* pointer arith! */
93 return (cnt * sizeof (long));
99 long int initdram(int board_type)
101 int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
102 ulong size, max_size = 0;
105 /* load t9 into our_address */
106 asm volatile ("move %0, $25" : "=r" (our_address) :);
108 /* Can't probe for RAM size unless we are running from Flash.
109 * find out whether running from DRAM or Flash.
111 if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
113 return max_sdram_size();
116 for (cols = 0x8; cols <= 0xC; cols++)
118 for (rows = 0xB; rows <= 0xD; rows++)
120 *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
122 size = dram_size((ulong *)CFG_SDRAM_BASE,
127 best_val = *DANUBE_SDRAM_MC_CFGPB0;
133 *DANUBE_SDRAM_MC_CFGPB0 = best_val;
138 int checkboard (void)
140 /* No such register in Amazon */
142 unsigned long chipid = *AMAZON_MCD_CHIPID;
145 puts ("Board: AMAZON ");
146 part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
148 case AMAZON_CHIPID_STANDARD:
149 printf ("Standard Version, ");
151 case AMAZON_CHIPID_YANGTSE:
152 printf ("Yangtse Version, ");
155 printf ("Unknown Part Number 0x%x ", part_num);
159 printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid));
162 printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000);
170 * Disk On Chip (NAND) Millenium initialization.
171 * The NAND lives in the CS2* space
173 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
175 nand_probe(ulong physadr);
177 #define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
183 //TODO: should we keep this?
184 //Set GPIO23 to be Flash CS1;
185 *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7);
186 *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7);
187 *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ;
188 *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ;
190 *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31;
191 /* byte swap;minimum delay*/
192 *EBU_CON_1 = 0x40C155;
193 *EBU_NAND_CON = 0x000005F3;
195 /* Set bus signals to inactive */
199 nand_probe(NAND_BASE_ADDRESS);
203 //nand_probe(AT91_SMARTMEDIA_BASE);