package/mac80211/patches/562-ath9k_use_reg_rmw.patch

   1 --- a/drivers/net/wireless/ath/ath9k/hw.c
   2 +++ b/drivers/net/wireless/ath/ath9k/hw.c
   3 @@ -684,14 +684,14 @@ static void ath9k_hw_init_qos(struct ath
   4
   5  unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
   6  {
   7 -               REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
   8 -               udelay(100);
   9 -               REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
  10 +       REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
  11 +       udelay(100);
  12 +       REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
  13
  14 -               while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
  15 -                       udelay(100);
  16 +       while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
  17 +               udelay(100);
  18
  19 -               return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
  20 +       return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
  21  }
  22  EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
  23
  24 @@ -841,8 +841,7 @@ void ath9k_hw_init_global_settings(struc
  25                 ah->misc_mode);
  26
  27         if (ah->misc_mode != 0)
  28 -               REG_WRITE(ah, AR_PCU_MISC,
  29 -                         REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
  30 +               REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
  31
  32         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
  33                 sifstime = 16;
  34 @@ -910,23 +909,19 @@ u32 ath9k_regd_get_ctl(struct ath_regula
  35  static inline void ath9k_hw_set_dma(struct ath_hw *ah)
  36  {
  37         struct ath_common *common = ath9k_hw_common(ah);
  38 -       u32 regval;
  39
  40         ENABLE_REGWRITE_BUFFER(ah);
  41
  42         /*
  43          * set AHB_MODE not to do cacheline prefetches
  44         */
  45 -       if (!AR_SREV_9300_20_OR_LATER(ah)) {
  46 -               regval = REG_READ(ah, AR_AHB_MODE);
  47 -               REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
  48 -       }
  49 +       if (!AR_SREV_9300_20_OR_LATER(ah))
  50 +               REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
  51
  52         /*
  53          * let mac dma reads be in 128 byte chunks
  54          */
  55 -       regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
  56 -       REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
  57 +       REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
  58
  59         REGWRITE_BUFFER_FLUSH(ah);
  60
  61 @@ -943,8 +938,7 @@ static inline void ath9k_hw_set_dma(stru
  62         /*
  63          * let mac dma writes be in 128 byte chunks
  64          */
  65 -       regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
  66 -       REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
  67 +       REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
  68
  69         /*
  70          * Setup receive FIFO threshold to hold off TX activities
  71 @@ -983,30 +977,27 @@ static inline void ath9k_hw_set_dma(stru
  72
  73  static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
  74  {
  75 -       u32 val;
  76 +       u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
  77 +       u32 set = AR_STA_ID1_KSRCH_MODE;
  78
  79 -       val = REG_READ(ah, AR_STA_ID1);
  80 -       val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
  81         switch (opmode) {
  82 -       case NL80211_IFTYPE_AP:
  83 -               REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
  84 -                         | AR_STA_ID1_KSRCH_MODE);
  85 -               REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  86 -               break;
  87         case NL80211_IFTYPE_ADHOC:
  88         case NL80211_IFTYPE_MESH_POINT:
  89 -               REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
  90 -                         | AR_STA_ID1_KSRCH_MODE);
  91 +               set |= AR_STA_ID1_ADHOC;
  92                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  93                 break;
  94 +       case NL80211_IFTYPE_AP:
  95 +               set |= AR_STA_ID1_STA_AP;
  96 +               /* fall through */
  97         case NL80211_IFTYPE_STATION:
  98 -               REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
  99 +               REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 100                 break;
 101         default:
 102 -               if (ah->is_monitoring)
 103 -                       REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 104 +               if (!ah->is_monitoring)
 105 +                       set = 0;
 106                 break;
 107         }
 108 +       REG_RMW(ah, AR_STA_ID1, set, mask);
 109  }
 110
 111  void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 112 @@ -1032,10 +1023,8 @@ static bool ath9k_hw_set_reset(struct at
 113         u32 tmpReg;
 114
 115         if (AR_SREV_9100(ah)) {
 116 -               u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 117 -               val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 118 -               val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 119 -               REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 120 +               REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
 121 +                             AR_RTC_DERIVED_CLK_PERIOD, 1);
 122                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 123         }
 124
 125 @@ -1460,8 +1449,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
 126                 ar9002_hw_enable_wep_aggregation(ah);
 127         }
 128
 129 -       REG_WRITE(ah, AR_STA_ID1,
 130 -                 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
 131 +       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
 132
 133         ath9k_hw_set_dma(ah);
 134
 135 @@ -2213,11 +2201,9 @@ void ath9k_hw_setrxfilter(struct ath_hw
 136         REG_WRITE(ah, AR_PHY_ERR, phybits);
 137
 138         if (phybits)
 139 -               REG_WRITE(ah, AR_RXCFG,
 140 -                         REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
 141 +               REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
 142         else
 143 -               REG_WRITE(ah, AR_RXCFG,
 144 -                         REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 145 +               REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
 146
 147         REGWRITE_BUFFER_FLUSH(ah);
 148  }
 149 --- a/drivers/net/wireless/ath/ath9k/mac.c
 150 +++ b/drivers/net/wireless/ath/ath9k/mac.c
 151 @@ -465,10 +465,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw
 152                 REG_WRITE(ah, AR_QCBRCFG(q),
 153                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
 154                           SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
 155 -               REG_WRITE(ah, AR_QMISC(q),
 156 -                         REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
 157 -                         (qi->tqi_cbrOverflowLimit ?
 158 -                          AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
 159 +               REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
 160 +                           (qi->tqi_cbrOverflowLimit ?
 161 +                            AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
 162         }
 163         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
 164                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
 165 @@ -481,40 +480,31 @@ bool ath9k_hw_resettxqueue(struct ath_hw
 166                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
 167
 168         if (qi->tqi_burstTime
 169 -           && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
 170 -               REG_WRITE(ah, AR_QMISC(q),
 171 -                         REG_READ(ah, AR_QMISC(q)) |
 172 -                         AR_Q_MISC_RDYTIME_EXP_POLICY);
 173 +           && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
 174 +               REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
 175
 176 -       }
 177 -
 178 -       if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
 179 -               REG_WRITE(ah, AR_DMISC(q),
 180 -                         REG_READ(ah, AR_DMISC(q)) |
 181 -                         AR_D_MISC_POST_FR_BKOFF_DIS);
 182 -       }
 183 +       if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
 184 +               REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
 185
 186         REGWRITE_BUFFER_FLUSH(ah);
 187
 188 -       if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
 189 -               REG_WRITE(ah, AR_DMISC(q),
 190 -                         REG_READ(ah, AR_DMISC(q)) |
 191 -                         AR_D_MISC_FRAG_BKOFF_EN);
 192 -       }
 193 +       if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
 194 +               REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
 195 +
 196         switch (qi->tqi_type) {
 197         case ATH9K_TX_QUEUE_BEACON:
 198                 ENABLE_REGWRITE_BUFFER(ah);
 199
 200 -               REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
 201 -                         | AR_Q_MISC_FSP_DBA_GATED
 202 -                         | AR_Q_MISC_BEACON_USE
 203 -                         | AR_Q_MISC_CBR_INCR_DIS1);
 204 +               REG_SET_BIT(ah, AR_QMISC(q),
 205 +                           AR_Q_MISC_FSP_DBA_GATED
 206 +                           | AR_Q_MISC_BEACON_USE
 207 +                           | AR_Q_MISC_CBR_INCR_DIS1);
 208
 209 -               REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
 210 -                         | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
 211 +               REG_SET_BIT(ah, AR_DMISC(q),
 212 +                           (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
 213                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
 214 -                         | AR_D_MISC_BEACON_USE
 215 -                         | AR_D_MISC_POST_FR_BKOFF_DIS);
 216 +                           | AR_D_MISC_BEACON_USE
 217 +                           | AR_D_MISC_POST_FR_BKOFF_DIS);
 218
 219                 REGWRITE_BUFFER_FLUSH(ah);
 220
 221 @@ -533,41 +523,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw
 222         case ATH9K_TX_QUEUE_CAB:
 223                 ENABLE_REGWRITE_BUFFER(ah);
 224
 225 -               REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
 226 -                         | AR_Q_MISC_FSP_DBA_GATED
 227 -                         | AR_Q_MISC_CBR_INCR_DIS1
 228 -                         | AR_Q_MISC_CBR_INCR_DIS0);
 229 +               REG_SET_BIT(ah, AR_QMISC(q),
 230 +                           AR_Q_MISC_FSP_DBA_GATED
 231 +                           | AR_Q_MISC_CBR_INCR_DIS1
 232 +                           | AR_Q_MISC_CBR_INCR_DIS0);
 233                 value = (qi->tqi_readyTime -
 234                          (ah->config.sw_beacon_response_time -
 235                           ah->config.dma_beacon_response_time) -
 236                          ah->config.additional_swba_backoff) * 1024;
 237                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
 238                           value | AR_Q_RDYTIMECFG_EN);
 239 -               REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
 240 -                         | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
 241 +               REG_SET_BIT(ah, AR_DMISC(q),
 242 +                           (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
 243                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
 244
 245                 REGWRITE_BUFFER_FLUSH(ah);
 246
 247                 break;
 248         case ATH9K_TX_QUEUE_PSPOLL:
 249 -               REG_WRITE(ah, AR_QMISC(q),
 250 -                         REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
 251 +               REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
 252                 break;
 253         case ATH9K_TX_QUEUE_UAPSD:
 254 -               REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
 255 -                         AR_D_MISC_POST_FR_BKOFF_DIS);
 256 +               REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
 257                 break;
 258         default:
 259                 break;
 260         }
 261
 262         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
 263 -               REG_WRITE(ah, AR_DMISC(q),
 264 -                         REG_READ(ah, AR_DMISC(q)) |
 265 -                         SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
 266 -                            AR_D_MISC_ARB_LOCKOUT_CNTRL) |
 267 -                         AR_D_MISC_POST_FR_BKOFF_DIS);
 268 +               REG_SET_BIT(ah, AR_DMISC(q),
 269 +                           SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
 270 +                              AR_D_MISC_ARB_LOCKOUT_CNTRL) |
 271 +                           AR_D_MISC_POST_FR_BKOFF_DIS);
 272         }
 273
 274         if (AR_SREV_9300_20_OR_LATER(ah))