package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch

   1 --- a/drivers/net/wireless/ath/ath9k/hw.c
   2 +++ b/drivers/net/wireless/ath/ath9k/hw.c
   3 @@ -742,6 +742,39 @@ static void ath9k_hw_init_pll(struct ath
   4                 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
   5                               AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
   6                 udelay(1000);
   7 +       } else if (AR_SREV_9330(ah)) {
   8 +               u32 ddr_dpll2, pll_control2, kd;
   9 +
  10 +               if (ah->is_clk_25mhz) {
  11 +                       ddr_dpll2 = 0x18e82f01;
  12 +                       pll_control2 = 0xe04a3d;
  13 +                       kd = 0x1d;
  14 +               } else {
  15 +                       ddr_dpll2 = 0x19e82f01;
  16 +                       pll_control2 = 0x886666;
  17 +                       kd = 0x3d;
  18 +               }
  19 +
  20 +               /* program DDR PLL ki and kd value */
  21 +               REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
  22 +
  23 +               /* program DDR PLL phase_shift */
  24 +               REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
  25 +                             AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
  26 +
  27 +               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
  28 +               udelay(1000);
  29 +
  30 +               /* program refdiv, nint, frac to RTC register */
  31 +               REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
  32 +
  33 +               /* program BB PLL kd and ki value */
  34 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
  35 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
  36 +
  37 +               /* program BB PLL phase_shift */
  38 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
  39 +                             AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
  40         } else if (AR_SREV_9340(ah)) {
  41                 u32 regval, pll2_divint, pll2_divfrac, refdiv;
  42
  43 @@ -783,7 +816,7 @@ static void ath9k_hw_init_pll(struct ath
  44
  45         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
  46
  47 -       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
  48 +       if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
  49                 udelay(1000);
  50
  51         /* Switch the core clock for ar9271 to 117Mhz */