package/mac80211/patches/310-pending_work.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
   2 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
   3 @@ -189,7 +189,6 @@ struct ath_txq {
   4         u32 axq_ampdu_depth;
   5         bool stopped;
   6         bool axq_tx_inprogress;
   7 -       bool txq_flush_inprogress;
   8         struct list_head axq_acq;
   9         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
  10         struct list_head txq_fifo_pending;
  11 --- a/drivers/net/wireless/ath/ath9k/beacon.c
  12 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
  13 @@ -373,6 +373,7 @@ void ath_beacon_tasklet(unsigned long da
  14                         ath_dbg(common, ATH_DBG_BSTUCK,
  15                                 "missed %u consecutive beacons\n",
  16                                 sc->beacon.bmisscnt);
  17 +                       ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
  18                         ath9k_hw_bstuck_nfcal(ah);
  19                 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
  20                         ath_dbg(common, ATH_DBG_BSTUCK,
  21 @@ -450,16 +451,6 @@ void ath_beacon_tasklet(unsigned long da
  22                 sc->beacon.updateslot = OK;
  23         }
  24         if (bfaddr != 0) {
  25 -               /*
  26 -                * Stop any current dma and put the new frame(s) on the queue.
  27 -                * This should never fail since we check above that no frames
  28 -                * are still pending on the queue.
  29 -                */
  30 -               if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
  31 -                       ath_err(common, "beacon queue %u did not stop?\n",
  32 -                               sc->beacon.beaconq);
  33 -               }
  34 -
  35                 /* NB: cabq traffic should already be queued and primed */
  36                 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
  37                 ath9k_hw_txstart(ah, sc->beacon.beaconq);
  38 @@ -780,7 +771,7 @@ void ath9k_set_beaconing_status(struct a
  39                 ah->imask &= ~ATH9K_INT_SWBA;
  40                 ath9k_hw_set_interrupts(ah, ah->imask);
  41                 tasklet_kill(&sc->bcon_tasklet);
  42 -               ath9k_hw_stoptxdma(ah, sc->beacon.beaconq);
  43 +               ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
  44         }
  45         ath9k_ps_restore(sc);
  46  }
  47 --- a/drivers/net/wireless/ath/ath9k/hw.h
  48 +++ b/drivers/net/wireless/ath/ath9k/hw.h
  49 @@ -95,9 +95,9 @@
  50  #define REG_READ_FIELD(_a, _r, _f) \
  51         (((REG_READ(_a, _r) & _f) >> _f##_S))
  52  #define REG_SET_BIT(_a, _r, _f) \
  53 -       REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  54 +       REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
  55  #define REG_CLR_BIT(_a, _r, _f) \
  56 -       REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  57 +       REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
  58
  59  #define DO_DELAY(x) do {                       \
  60                 if ((++(x) % 64) == 0)          \
  61 --- a/drivers/net/wireless/ath/ath9k/mac.c
  62 +++ b/drivers/net/wireless/ath/ath9k/mac.c
  63 @@ -143,84 +143,59 @@ bool ath9k_hw_updatetxtriglevel(struct a
  64  }
  65  EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
  66
  67 -bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
  68 +void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
  69  {
  70 -#define ATH9K_TX_STOP_DMA_TIMEOUT      4000    /* usec */
  71 -#define ATH9K_TIME_QUANTUM             100     /* usec */
  72 -       struct ath_common *common = ath9k_hw_common(ah);
  73 -       struct ath9k_hw_capabilities *pCap = &ah->caps;
  74 -       struct ath9k_tx_queue_info *qi;
  75 -       u32 tsfLow, j, wait;
  76 -       u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
  77 +       int i, q;
  78
  79 -       if (q >= pCap->total_queues) {
  80 -               ath_dbg(common, ATH_DBG_QUEUE,
  81 -                       "Stopping TX DMA, invalid queue: %u\n", q);
  82 -               return false;
  83 -       }
  84 +       REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
  85
  86 -       qi = &ah->txq[q];
  87 -       if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
  88 -               ath_dbg(common, ATH_DBG_QUEUE,
  89 -                       "Stopping TX DMA, inactive queue: %u\n", q);
  90 -               return false;
  91 -       }
  92 +       REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
  93 +       REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
  94 +       REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
  95
  96 -       REG_WRITE(ah, AR_Q_TXD, 1 << q);
  97 +       for (q = 0; q < AR_NUM_QCU; q++) {
  98 +               for (i = 0; i < 1000; i++) {
  99 +                       if (i)
 100 +                               udelay(5);
 101
 102 -       for (wait = wait_time; wait != 0; wait--) {
 103 -               if (ath9k_hw_numtxpending(ah, q) == 0)
 104 -                       break;
 105 -               udelay(ATH9K_TIME_QUANTUM);
 106 +                       if (!ath9k_hw_numtxpending(ah, q))
 107 +                               break;
 108 +               }
 109         }
 110
 111 -       if (ath9k_hw_numtxpending(ah, q)) {
 112 -               ath_dbg(common, ATH_DBG_QUEUE,
 113 -                       "%s: Num of pending TX Frames %d on Q %d\n",
 114 -                       __func__, ath9k_hw_numtxpending(ah, q), q);
 115 -
 116 -               for (j = 0; j < 2; j++) {
 117 -                       tsfLow = REG_READ(ah, AR_TSF_L32);
 118 -                       REG_WRITE(ah, AR_QUIET2,
 119 -                                 SM(10, AR_QUIET2_QUIET_DUR));
 120 -                       REG_WRITE(ah, AR_QUIET_PERIOD, 100);
 121 -                       REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
 122 -                       REG_SET_BIT(ah, AR_TIMER_MODE,
 123 -                                      AR_QUIET_TIMER_EN);
 124 -
 125 -                       if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
 126 -                               break;
 127 +       REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
 128 +       REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
 129 +       REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
 130
 131 -                       ath_dbg(common, ATH_DBG_QUEUE,
 132 -                               "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
 133 -                               tsfLow);
 134 -               }
 135 +       REG_WRITE(ah, AR_Q_TXD, 0);
 136 +}
 137 +EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
 138
 139 -               REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
 140 +bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
 141 +{
 142 +#define ATH9K_TX_STOP_DMA_TIMEOUT      1000    /* usec */
 143 +#define ATH9K_TIME_QUANTUM             100     /* usec */
 144 +       int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
 145 +       int wait;
 146
 147 -               udelay(200);
 148 -               REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
 149 +       REG_WRITE(ah, AR_Q_TXD, 1 << q);
 150
 151 -               wait = wait_time;
 152 -               while (ath9k_hw_numtxpending(ah, q)) {
 153 -                       if ((--wait) == 0) {
 154 -                               ath_err(common,
 155 -                                       "Failed to stop TX DMA in 100 msec after killing last frame\n");
 156 -                               break;
 157 -                       }
 158 +       for (wait = wait_time; wait != 0; wait--) {
 159 +               if (wait != wait_time)
 160                         udelay(ATH9K_TIME_QUANTUM);
 161 -               }
 162
 163 -               REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
 164 +               if (ath9k_hw_numtxpending(ah, q) == 0)
 165 +                       break;
 166         }
 167
 168         REG_WRITE(ah, AR_Q_TXD, 0);
 169 +
 170         return wait != 0;
 171
 172  #undef ATH9K_TX_STOP_DMA_TIMEOUT
 173  #undef ATH9K_TIME_QUANTUM
 174  }
 175 -EXPORT_SYMBOL(ath9k_hw_stoptxdma);
 176 +EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
 177
 178  void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
 179  {
 180 --- a/drivers/net/wireless/ath/ath9k/mac.h
 181 +++ b/drivers/net/wireless/ath/ath9k/mac.h
 182 @@ -676,7 +676,8 @@ void ath9k_hw_txstart(struct ath_hw *ah,
 183  void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
 184  u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
 185  bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
 186 -bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
 187 +bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
 188 +void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
 189  void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
 190  bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
 191                             const struct ath9k_tx_queue_info *qinfo);
 192 --- a/drivers/net/wireless/ath/ath9k/main.c
 193 +++ b/drivers/net/wireless/ath/ath9k/main.c
 194 @@ -2128,56 +2128,42 @@ static void ath9k_set_coverage_class(str
 195
 196  static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
 197  {
 198 -#define ATH_FLUSH_TIMEOUT      60 /* ms */
 199         struct ath_softc *sc = hw->priv;
 200 -       struct ath_txq *txq = NULL;
 201 -       struct ath_hw *ah = sc->sc_ah;
 202 -       struct ath_common *common = ath9k_hw_common(ah);
 203 -       int i, j, npend = 0;
 204 +       int timeout = 200; /* ms */
 205 +       int i, j;
 206
 207 +       ath9k_ps_wakeup(sc);
 208         mutex_lock(&sc->mutex);
 209
 210         cancel_delayed_work_sync(&sc->tx_complete_work);
 211
 212 -       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 213 -               if (!ATH_TXQ_SETUP(sc, i))
 214 -                       continue;
 215 -               txq = &sc->tx.txq[i];
 216 -
 217 -               if (!drop) {
 218 -                       for (j = 0; j < ATH_FLUSH_TIMEOUT; j++) {
 219 -                               if (!ath9k_has_pending_frames(sc, txq))
 220 -                                       break;
 221 -                               usleep_range(1000, 2000);
 222 -                       }
 223 -               }
 224 +       if (drop)
 225 +               timeout = 1;
 226 +
 227 +       for (j = 0; j < timeout; j++) {
 228 +               int npend = 0;
 229 +
 230 +               if (j)
 231 +                       usleep_range(1000, 2000);
 232
 233 -               if (drop || ath9k_has_pending_frames(sc, txq)) {
 234 -                       ath_dbg(common, ATH_DBG_QUEUE, "Drop frames from hw queue:%d\n",
 235 -                               txq->axq_qnum);
 236 -                       spin_lock_bh(&txq->axq_lock);
 237 -                       txq->txq_flush_inprogress = true;
 238 -                       spin_unlock_bh(&txq->axq_lock);
 239 -
 240 -                       ath9k_ps_wakeup(sc);
 241 -                       ath9k_hw_stoptxdma(ah, txq->axq_qnum);
 242 -                       npend = ath9k_hw_numtxpending(ah, txq->axq_qnum);
 243 -                       ath9k_ps_restore(sc);
 244 -                       if (npend)
 245 -                               break;
 246 +               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 247 +                       if (!ATH_TXQ_SETUP(sc, i))
 248 +                               continue;
 249
 250 -                       ath_draintxq(sc, txq, false);
 251 -                       txq->txq_flush_inprogress = false;
 252 +                       npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
 253                 }
 254 +
 255 +               if (!npend)
 256 +                   goto out;
 257         }
 258
 259 -       if (npend) {
 260 +       if (!ath_drain_all_txq(sc, false))
 261                 ath_reset(sc, false);
 262 -               txq->txq_flush_inprogress = false;
 263 -       }
 264
 265 +out:
 266         ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
 267         mutex_unlock(&sc->mutex);
 268 +       ath9k_ps_restore(sc);
 269  }
 270
 271  struct ieee80211_ops ath9k_ops = {
 272 --- a/drivers/net/wireless/ath/ath9k/xmit.c
 273 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
 274 @@ -166,7 +166,7 @@ static void ath_tx_flush_tid(struct ath_
 275                 fi = get_frame_info(bf->bf_mpdu);
 276                 if (fi->retries) {
 277                         ath_tx_update_baw(sc, tid, fi->seqno);
 278 -                       ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
 279 +                       ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
 280                 } else {
 281                         ath_tx_send_normal(sc, txq, NULL, &bf_head);
 282                 }
 283 @@ -1194,16 +1194,14 @@ bool ath_drain_all_txq(struct ath_softc
 284         if (sc->sc_flags & SC_OP_INVALID)
 285                 return true;
 286
 287 -       /* Stop beacon queue */
 288 -       ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
 289 +       ath9k_hw_abort_tx_dma(ah);
 290
 291 -       /* Stop data queues */
 292 +       /* Check if any queue remains active */
 293         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 294 -               if (ATH_TXQ_SETUP(sc, i)) {
 295 -                       txq = &sc->tx.txq[i];
 296 -                       ath9k_hw_stoptxdma(ah, txq->axq_qnum);
 297 -                       npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
 298 -               }
 299 +               if (!ATH_TXQ_SETUP(sc, i))
 300 +                       continue;
 301 +
 302 +               npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
 303         }
 304
 305         if (npend)
 306 @@ -2014,8 +2012,7 @@ static void ath_tx_processq(struct ath_s
 307                 spin_lock_bh(&txq->axq_lock);
 308                 if (list_empty(&txq->axq_q)) {
 309                         txq->axq_link = NULL;
 310 -                       if (sc->sc_flags & SC_OP_TXAGGR &&
 311 -                           !txq->txq_flush_inprogress)
 312 +                       if (sc->sc_flags & SC_OP_TXAGGR)
 313                                 ath_txq_schedule(sc, txq);
 314                         spin_unlock_bh(&txq->axq_lock);
 315                         break;
 316 @@ -2096,7 +2093,7 @@ static void ath_tx_processq(struct ath_s
 317
 318                 spin_lock_bh(&txq->axq_lock);
 319
 320 -               if (sc->sc_flags & SC_OP_TXAGGR && !txq->txq_flush_inprogress)
 321 +               if (sc->sc_flags & SC_OP_TXAGGR)
 322                         ath_txq_schedule(sc, txq);
 323                 spin_unlock_bh(&txq->axq_lock);
 324         }
 325 @@ -2267,18 +2264,17 @@ void ath_tx_edma_tasklet(struct ath_soft
 326
 327                 spin_lock_bh(&txq->axq_lock);
 328
 329 -               if (!txq->txq_flush_inprogress) {
 330 -                       if (!list_empty(&txq->txq_fifo_pending)) {
 331 -                               INIT_LIST_HEAD(&bf_head);
 332 -                               bf = list_first_entry(&txq->txq_fifo_pending,
 333 -                                                     struct ath_buf, list);
 334 -                               list_cut_position(&bf_head,
 335 -                                                 &txq->txq_fifo_pending,
 336 -                                                 &bf->bf_lastbf->list);
 337 -                               ath_tx_txqaddbuf(sc, txq, &bf_head);
 338 -                       } else if (sc->sc_flags & SC_OP_TXAGGR)
 339 -                               ath_txq_schedule(sc, txq);
 340 -               }
 341 +               if (!list_empty(&txq->txq_fifo_pending)) {
 342 +                       INIT_LIST_HEAD(&bf_head);
 343 +                       bf = list_first_entry(&txq->txq_fifo_pending,
 344 +                                             struct ath_buf, list);
 345 +                       list_cut_position(&bf_head,
 346 +                                         &txq->txq_fifo_pending,
 347 +                                         &bf->bf_lastbf->list);
 348 +                       ath_tx_txqaddbuf(sc, txq, &bf_head);
 349 +               } else if (sc->sc_flags & SC_OP_TXAGGR)
 350 +                       ath_txq_schedule(sc, txq);
 351 +
 352                 spin_unlock_bh(&txq->axq_lock);
 353         }
 354  }
 355 --- a/net/mac80211/chan.c
 356 +++ b/net/mac80211/chan.c
 357 @@ -77,6 +77,9 @@ bool ieee80211_set_channel_type(struct i
 358                 switch (tmp->vif.bss_conf.channel_type) {
 359                 case NL80211_CHAN_NO_HT:
 360                 case NL80211_CHAN_HT20:
 361 +                       if (superchan > tmp->vif.bss_conf.channel_type)
 362 +                               break;
 363 +
 364                         superchan = tmp->vif.bss_conf.channel_type;
 365                         break;
 366                 case NL80211_CHAN_HT40PLUS:
 367 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
 368 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
 369 @@ -88,66 +88,6 @@ static void ar9003_hw_init_mode_regs(str
 370                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 371                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 372                                 2);
 373 -       } else if (AR_SREV_9485(ah)) {
 374 -               /* mac */
 375 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 376 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 377 -                               ar9485_1_0_mac_core,
 378 -                               ARRAY_SIZE(ar9485_1_0_mac_core), 2);
 379 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 380 -                               ar9485_1_0_mac_postamble,
 381 -                               ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
 382 -
 383 -               /* bb */
 384 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
 385 -                               ARRAY_SIZE(ar9485_1_0), 2);
 386 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 387 -                               ar9485_1_0_baseband_core,
 388 -                               ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
 389 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 390 -                               ar9485_1_0_baseband_postamble,
 391 -                               ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
 392 -
 393 -               /* radio */
 394 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 395 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 396 -                               ar9485_1_0_radio_core,
 397 -                               ARRAY_SIZE(ar9485_1_0_radio_core), 2);
 398 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 399 -                               ar9485_1_0_radio_postamble,
 400 -                               ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
 401 -
 402 -               /* soc */
 403 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 404 -                               ar9485_1_0_soc_preamble,
 405 -                               ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
 406 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 407 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 408 -
 409 -               /* rx/tx gain */
 410 -               INIT_INI_ARRAY(&ah->iniModesRxGain,
 411 -                               ar9485Common_rx_gain_1_0,
 412 -                               ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
 413 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 414 -                               ar9485Modes_lowest_ob_db_tx_gain_1_0,
 415 -                               ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
 416 -                               5);
 417 -
 418 -               /* Load PCIE SERDES settings from INI */
 419 -
 420 -               /* Awake Setting */
 421 -
 422 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 423 -                               ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
 424 -                               ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
 425 -                               2);
 426 -
 427 -               /* Sleep Setting */
 428 -
 429 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 430 -                               ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
 431 -                               ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
 432 -                               2);
 433         } else {
 434                 /* mac */
 435                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 436 @@ -228,11 +168,6 @@ static void ar9003_tx_gain_table_apply(s
 437                                        ar9485_modes_lowest_ob_db_tx_gain_1_1,
 438                                        ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 439                                        5);
 440 -               else if (AR_SREV_9485(ah))
 441 -                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 442 -                                      ar9485Modes_lowest_ob_db_tx_gain_1_0,
 443 -                                      ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
 444 -                                      5);
 445                 else
 446                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 447                                        ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 448 @@ -245,11 +180,6 @@ static void ar9003_tx_gain_table_apply(s
 449                                        ar9485Modes_high_ob_db_tx_gain_1_1,
 450                                        ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 451                                        5);
 452 -               else if (AR_SREV_9485(ah))
 453 -                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 454 -                                      ar9485Modes_high_ob_db_tx_gain_1_0,
 455 -                                      ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_0),
 456 -                                      5);
 457                 else
 458                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 459                                        ar9300Modes_high_ob_db_tx_gain_table_2p2,
 460 @@ -262,11 +192,6 @@ static void ar9003_tx_gain_table_apply(s
 461                                        ar9485Modes_low_ob_db_tx_gain_1_1,
 462                                        ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 463                                        5);
 464 -               else if (AR_SREV_9485(ah))
 465 -                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 466 -                                      ar9485Modes_low_ob_db_tx_gain_1_0,
 467 -                                      ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_0),
 468 -                                      5);
 469                 else
 470                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 471                                        ar9300Modes_low_ob_db_tx_gain_table_2p2,
 472 @@ -279,11 +204,6 @@ static void ar9003_tx_gain_table_apply(s
 473                                        ar9485Modes_high_power_tx_gain_1_1,
 474                                        ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 475                                        5);
 476 -               else if (AR_SREV_9485(ah))
 477 -                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 478 -                                      ar9485Modes_high_power_tx_gain_1_0,
 479 -                                      ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
 480 -                                      5);
 481                 else
 482                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 483                                        ar9300Modes_high_power_tx_gain_table_2p2,
 484 @@ -303,11 +223,6 @@ static void ar9003_rx_gain_table_apply(s
 485                                        ar9485_common_rx_gain_1_1,
 486                                        ARRAY_SIZE(ar9485_common_rx_gain_1_1),
 487                                        2);
 488 -               else if (AR_SREV_9485(ah))
 489 -                       INIT_INI_ARRAY(&ah->iniModesRxGain,
 490 -                                      ar9485Common_rx_gain_1_0,
 491 -                                      ARRAY_SIZE(ar9485Common_rx_gain_1_0),
 492 -                                      2);
 493                 else
 494                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 495                                        ar9300Common_rx_gain_table_2p2,
 496 @@ -320,11 +235,6 @@ static void ar9003_rx_gain_table_apply(s
 497                                        ar9485Common_wo_xlna_rx_gain_1_1,
 498                                        ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 499                                        2);
 500 -               else if (AR_SREV_9485(ah))
 501 -                       INIT_INI_ARRAY(&ah->iniModesRxGain,
 502 -                                      ar9485Common_wo_xlna_rx_gain_1_0,
 503 -                                      ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
 504 -                                      2);
 505                 else
 506                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 507                                        ar9300Common_wo_xlna_rx_gain_table_2p2,
 508 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
 509 +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
 510 @@ -17,931 +17,6 @@
 511  #ifndef INITVALS_9485_H
 512  #define INITVALS_9485_H
 513
 514 -static const u32 ar9485Common_1_0[][2] = {
 515 -       /*   Addr     allmodes */
 516 -       {0x00007010, 0x00000022},
 517 -       {0x00007020, 0x00000000},
 518 -       {0x00007034, 0x00000002},
 519 -       {0x00007038, 0x000004c2},
 520 -};
 521 -
 522 -static const u32 ar9485_1_0_mac_postamble[][5] = {
 523 -       /* Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20    */
 524 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
 525 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
 526 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
 527 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
 528 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
 529 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
 530 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
 531 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
 532 -};
 533 -
 534 -static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
 535 -       /*   Addr     allmodes */
 536 -       {0x00018c00, 0x10212e5e},
 537 -       {0x00018c04, 0x000801d8},
 538 -       {0x00018c08, 0x0000580c},
 539 -};
 540 -
 541 -static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
 542 -       /*   Addr     allmodes */
 543 -       {0x0000a000, 0x00010000},
 544 -       {0x0000a004, 0x00030002},
 545 -       {0x0000a008, 0x00050004},
 546 -       {0x0000a00c, 0x00810080},
 547 -       {0x0000a010, 0x01800082},
 548 -       {0x0000a014, 0x01820181},
 549 -       {0x0000a018, 0x01840183},
 550 -       {0x0000a01c, 0x01880185},
 551 -       {0x0000a020, 0x018a0189},
 552 -       {0x0000a024, 0x02850284},
 553 -       {0x0000a028, 0x02890288},
 554 -       {0x0000a02c, 0x03850384},
 555 -       {0x0000a030, 0x03890388},
 556 -       {0x0000a034, 0x038b038a},
 557 -       {0x0000a038, 0x038d038c},
 558 -       {0x0000a03c, 0x03910390},
 559 -       {0x0000a040, 0x03930392},
 560 -       {0x0000a044, 0x03950394},
 561 -       {0x0000a048, 0x00000396},
 562 -       {0x0000a04c, 0x00000000},
 563 -       {0x0000a050, 0x00000000},
 564 -       {0x0000a054, 0x00000000},
 565 -       {0x0000a058, 0x00000000},
 566 -       {0x0000a05c, 0x00000000},
 567 -       {0x0000a060, 0x00000000},
 568 -       {0x0000a064, 0x00000000},
 569 -       {0x0000a068, 0x00000000},
 570 -       {0x0000a06c, 0x00000000},
 571 -       {0x0000a070, 0x00000000},
 572 -       {0x0000a074, 0x00000000},
 573 -       {0x0000a078, 0x00000000},
 574 -       {0x0000a07c, 0x00000000},
 575 -       {0x0000a080, 0x28282828},
 576 -       {0x0000a084, 0x28282828},
 577 -       {0x0000a088, 0x28282828},
 578 -       {0x0000a08c, 0x28282828},
 579 -       {0x0000a090, 0x28282828},
 580 -       {0x0000a094, 0x21212128},
 581 -       {0x0000a098, 0x171c1c1c},
 582 -       {0x0000a09c, 0x02020212},
 583 -       {0x0000a0a0, 0x00000202},
 584 -       {0x0000a0a4, 0x00000000},
 585 -       {0x0000a0a8, 0x00000000},
 586 -       {0x0000a0ac, 0x00000000},
 587 -       {0x0000a0b0, 0x00000000},
 588 -       {0x0000a0b4, 0x00000000},
 589 -       {0x0000a0b8, 0x00000000},
 590 -       {0x0000a0bc, 0x00000000},
 591 -       {0x0000a0c0, 0x001f0000},
 592 -       {0x0000a0c4, 0x111f1100},
 593 -       {0x0000a0c8, 0x111d111e},
 594 -       {0x0000a0cc, 0x111b111c},
 595 -       {0x0000a0d0, 0x22032204},
 596 -       {0x0000a0d4, 0x22012202},
 597 -       {0x0000a0d8, 0x221f2200},
 598 -       {0x0000a0dc, 0x221d221e},
 599 -       {0x0000a0e0, 0x33013302},
 600 -       {0x0000a0e4, 0x331f3300},
 601 -       {0x0000a0e8, 0x4402331e},
 602 -       {0x0000a0ec, 0x44004401},
 603 -       {0x0000a0f0, 0x441e441f},
 604 -       {0x0000a0f4, 0x55015502},
 605 -       {0x0000a0f8, 0x551f5500},
 606 -       {0x0000a0fc, 0x6602551e},
 607 -       {0x0000a100, 0x66006601},
 608 -       {0x0000a104, 0x661e661f},
 609 -       {0x0000a108, 0x7703661d},
 610 -       {0x0000a10c, 0x77017702},
 611 -       {0x0000a110, 0x00007700},
 612 -       {0x0000a114, 0x00000000},
 613 -       {0x0000a118, 0x00000000},
 614 -       {0x0000a11c, 0x00000000},
 615 -       {0x0000a120, 0x00000000},
 616 -       {0x0000a124, 0x00000000},
 617 -       {0x0000a128, 0x00000000},
 618 -       {0x0000a12c, 0x00000000},
 619 -       {0x0000a130, 0x00000000},
 620 -       {0x0000a134, 0x00000000},
 621 -       {0x0000a138, 0x00000000},
 622 -       {0x0000a13c, 0x00000000},
 623 -       {0x0000a140, 0x001f0000},
 624 -       {0x0000a144, 0x111f1100},
 625 -       {0x0000a148, 0x111d111e},
 626 -       {0x0000a14c, 0x111b111c},
 627 -       {0x0000a150, 0x22032204},
 628 -       {0x0000a154, 0x22012202},
 629 -       {0x0000a158, 0x221f2200},
 630 -       {0x0000a15c, 0x221d221e},
 631 -       {0x0000a160, 0x33013302},
 632 -       {0x0000a164, 0x331f3300},
 633 -       {0x0000a168, 0x4402331e},
 634 -       {0x0000a16c, 0x44004401},
 635 -       {0x0000a170, 0x441e441f},
 636 -       {0x0000a174, 0x55015502},
 637 -       {0x0000a178, 0x551f5500},
 638 -       {0x0000a17c, 0x6602551e},
 639 -       {0x0000a180, 0x66006601},
 640 -       {0x0000a184, 0x661e661f},
 641 -       {0x0000a188, 0x7703661d},
 642 -       {0x0000a18c, 0x77017702},
 643 -       {0x0000a190, 0x00007700},
 644 -       {0x0000a194, 0x00000000},
 645 -       {0x0000a198, 0x00000000},
 646 -       {0x0000a19c, 0x00000000},
 647 -       {0x0000a1a0, 0x00000000},
 648 -       {0x0000a1a4, 0x00000000},
 649 -       {0x0000a1a8, 0x00000000},
 650 -       {0x0000a1ac, 0x00000000},
 651 -       {0x0000a1b0, 0x00000000},
 652 -       {0x0000a1b4, 0x00000000},
 653 -       {0x0000a1b8, 0x00000000},
 654 -       {0x0000a1bc, 0x00000000},
 655 -       {0x0000a1c0, 0x00000000},
 656 -       {0x0000a1c4, 0x00000000},
 657 -       {0x0000a1c8, 0x00000000},
 658 -       {0x0000a1cc, 0x00000000},
 659 -       {0x0000a1d0, 0x00000000},
 660 -       {0x0000a1d4, 0x00000000},
 661 -       {0x0000a1d8, 0x00000000},
 662 -       {0x0000a1dc, 0x00000000},
 663 -       {0x0000a1e0, 0x00000000},
 664 -       {0x0000a1e4, 0x00000000},
 665 -       {0x0000a1e8, 0x00000000},
 666 -       {0x0000a1ec, 0x00000000},
 667 -       {0x0000a1f0, 0x00000396},
 668 -       {0x0000a1f4, 0x00000396},
 669 -       {0x0000a1f8, 0x00000396},
 670 -       {0x0000a1fc, 0x00000296},
 671 -};
 672 -
 673 -static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
 674 -       /*   Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
 675 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
 676 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
 677 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
 678 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
 679 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
 680 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
 681 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
 682 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
 683 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
 684 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
 685 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
 686 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
 687 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
 688 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
 689 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
 690 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
 691 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
 692 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
 693 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
 694 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
 695 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
 696 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
 697 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
 698 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
 699 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
 700 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
 701 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
 702 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 703 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 704 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 705 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 706 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 707 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 708 -       {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
 709 -};
 710 -
 711 -static const u32 ar9485_1_0[][2] = {
 712 -       /*  Addr      allmodes */
 713 -       {0x0000a580, 0x00000000},
 714 -       {0x0000a584, 0x00000000},
 715 -       {0x0000a588, 0x00000000},
 716 -       {0x0000a58c, 0x00000000},
 717 -       {0x0000a590, 0x00000000},
 718 -       {0x0000a594, 0x00000000},
 719 -       {0x0000a598, 0x00000000},
 720 -       {0x0000a59c, 0x00000000},
 721 -       {0x0000a5a0, 0x00000000},
 722 -       {0x0000a5a4, 0x00000000},
 723 -       {0x0000a5a8, 0x00000000},
 724 -       {0x0000a5ac, 0x00000000},
 725 -       {0x0000a5b0, 0x00000000},
 726 -       {0x0000a5b4, 0x00000000},
 727 -       {0x0000a5b8, 0x00000000},
 728 -       {0x0000a5bc, 0x00000000},
 729 -};
 730 -
 731 -static const u32 ar9485_1_0_radio_core[][2] = {
 732 -       /*   Addr     allmodes */
 733 -       {0x00016000, 0x36db6db6},
 734 -       {0x00016004, 0x6db6db40},
 735 -       {0x00016008, 0x73800000},
 736 -       {0x0001600c, 0x00000000},
 737 -       {0x00016040, 0x7f80fff8},
 738 -       {0x00016048, 0x6c92426e},
 739 -       {0x0001604c, 0x000f0278},
 740 -       {0x00016050, 0x6db6db6c},
 741 -       {0x00016054, 0x6db60000},
 742 -       {0x00016080, 0x00080000},
 743 -       {0x00016084, 0x0e48048c},
 744 -       {0x00016088, 0x14214514},
 745 -       {0x0001608c, 0x119f081e},
 746 -       {0x00016090, 0x24926490},
 747 -       {0x00016098, 0xd28b3330},
 748 -       {0x000160a0, 0xc2108ffe},
 749 -       {0x000160a4, 0x812fc370},
 750 -       {0x000160a8, 0x423c8000},
 751 -       {0x000160b4, 0x92480040},
 752 -       {0x000160c0, 0x006db6db},
 753 -       {0x000160c4, 0x0186db60},
 754 -       {0x000160c8, 0x6db6db6c},
 755 -       {0x000160cc, 0x6de6fbe0},
 756 -       {0x000160d0, 0xf7dfcf3c},
 757 -       {0x00016100, 0x04cb0001},
 758 -       {0x00016104, 0xfff80015},
 759 -       {0x00016108, 0x00080010},
 760 -       {0x00016144, 0x01884080},
 761 -       {0x00016148, 0x00008040},
 762 -       {0x00016180, 0x08453333},
 763 -       {0x00016184, 0x18e82f01},
 764 -       {0x00016188, 0x00000000},
 765 -       {0x0001618c, 0x00000000},
 766 -       {0x00016240, 0x08400000},
 767 -       {0x00016244, 0x1bf90f00},
 768 -       {0x00016248, 0x00000000},
 769 -       {0x0001624c, 0x00000000},
 770 -       {0x00016280, 0x01000015},
 771 -       {0x00016284, 0x00d30000},
 772 -       {0x00016288, 0x00318000},
 773 -       {0x0001628c, 0x50000000},
 774 -       {0x00016290, 0x4b96210f},
 775 -       {0x00016380, 0x00000000},
 776 -       {0x00016384, 0x00000000},
 777 -       {0x00016388, 0x00800700},
 778 -       {0x0001638c, 0x00800700},
 779 -       {0x00016390, 0x00800700},
 780 -       {0x00016394, 0x00000000},
 781 -       {0x00016398, 0x00000000},
 782 -       {0x0001639c, 0x00000000},
 783 -       {0x000163a0, 0x00000001},
 784 -       {0x000163a4, 0x00000001},
 785 -       {0x000163a8, 0x00000000},
 786 -       {0x000163ac, 0x00000000},
 787 -       {0x000163b0, 0x00000000},
 788 -       {0x000163b4, 0x00000000},
 789 -       {0x000163b8, 0x00000000},
 790 -       {0x000163bc, 0x00000000},
 791 -       {0x000163c0, 0x000000a0},
 792 -       {0x000163c4, 0x000c0000},
 793 -       {0x000163c8, 0x14021402},
 794 -       {0x000163cc, 0x00001402},
 795 -       {0x000163d0, 0x00000000},
 796 -       {0x000163d4, 0x00000000},
 797 -       {0x00016c40, 0x1319c178},
 798 -       {0x00016c44, 0x10000000},
 799 -};
 800 -
 801 -static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
 802 -       /*  Addr       5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
 803 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
 804 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
 805 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
 806 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
 807 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
 808 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
 809 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
 810 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
 811 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
 812 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
 813 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
 814 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
 815 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
 816 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
 817 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
 818 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
 819 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
 820 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
 821 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
 822 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
 823 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
 824 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
 825 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
 826 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
 827 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
 828 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
 829 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
 830 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 831 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 832 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 833 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 834 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 835 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
 836 -       {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
 837 -};
 838 -
 839 -static const u32 ar9485_1_0_baseband_core[][2] = {
 840 -       /* Addr      allmodes  */
 841 -       {0x00009800, 0xafe68e30},
 842 -       {0x00009804, 0xfd14e000},
 843 -       {0x00009808, 0x9c0a8f6b},
 844 -       {0x0000980c, 0x04800000},
 845 -       {0x00009814, 0x9280c00a},
 846 -       {0x00009818, 0x00000000},
 847 -       {0x0000981c, 0x00020028},
 848 -       {0x00009834, 0x5f3ca3de},
 849 -       {0x00009838, 0x0108ecff},
 850 -       {0x0000983c, 0x14750600},
 851 -       {0x00009880, 0x201fff00},
 852 -       {0x00009884, 0x00001042},
 853 -       {0x000098a4, 0x00200400},
 854 -       {0x000098b0, 0x52440bbe},
 855 -       {0x000098bc, 0x00000002},
 856 -       {0x000098d0, 0x004b6a8e},
 857 -       {0x000098d4, 0x00000820},
 858 -       {0x000098dc, 0x00000000},
 859 -       {0x000098f0, 0x00000000},
 860 -       {0x000098f4, 0x00000000},
 861 -       {0x00009c04, 0x00000000},
 862 -       {0x00009c08, 0x03200000},
 863 -       {0x00009c0c, 0x00000000},
 864 -       {0x00009c10, 0x00000000},
 865 -       {0x00009c14, 0x00046384},
 866 -       {0x00009c18, 0x05b6b440},
 867 -       {0x00009c1c, 0x00b6b440},
 868 -       {0x00009d00, 0xc080a333},
 869 -       {0x00009d04, 0x40206c10},
 870 -       {0x00009d08, 0x009c4060},
 871 -       {0x00009d0c, 0x1883800a},
 872 -       {0x00009d10, 0x01834061},
 873 -       {0x00009d14, 0x00c00400},
 874 -       {0x00009d18, 0x00000000},
 875 -       {0x00009d1c, 0x00000000},
 876 -       {0x00009e08, 0x0038233c},
 877 -       {0x00009e24, 0x990bb515},
 878 -       {0x00009e28, 0x0a6f0000},
 879 -       {0x00009e30, 0x06336f77},
 880 -       {0x00009e34, 0x6af6532f},
 881 -       {0x00009e38, 0x0cc80c00},
 882 -       {0x00009e40, 0x0d261820},
 883 -       {0x00009e4c, 0x00001004},
 884 -       {0x00009e50, 0x00ff03f1},
 885 -       {0x00009fc0, 0x80be4788},
 886 -       {0x00009fc4, 0x0001efb5},
 887 -       {0x00009fcc, 0x40000014},
 888 -       {0x0000a20c, 0x00000000},
 889 -       {0x0000a210, 0x00000000},
 890 -       {0x0000a220, 0x00000000},
 891 -       {0x0000a224, 0x00000000},
 892 -       {0x0000a228, 0x10002310},
 893 -       {0x0000a23c, 0x00000000},
 894 -       {0x0000a244, 0x0c000000},
 895 -       {0x0000a2a0, 0x00000001},
 896 -       {0x0000a2c0, 0x00000001},
 897 -       {0x0000a2c8, 0x00000000},
 898 -       {0x0000a2cc, 0x18c43433},
 899 -       {0x0000a2d4, 0x00000000},
 900 -       {0x0000a2dc, 0x00000000},
 901 -       {0x0000a2e0, 0x00000000},
 902 -       {0x0000a2e4, 0x00000000},
 903 -       {0x0000a2e8, 0x00000000},
 904 -       {0x0000a2ec, 0x00000000},
 905 -       {0x0000a2f0, 0x00000000},
 906 -       {0x0000a2f4, 0x00000000},
 907 -       {0x0000a2f8, 0x00000000},
 908 -       {0x0000a344, 0x00000000},
 909 -       {0x0000a34c, 0x00000000},
 910 -       {0x0000a350, 0x0000a000},
 911 -       {0x0000a364, 0x00000000},
 912 -       {0x0000a370, 0x00000000},
 913 -       {0x0000a390, 0x00000001},
 914 -       {0x0000a394, 0x00000444},
 915 -       {0x0000a398, 0x001f0e0f},
 916 -       {0x0000a39c, 0x0075393f},
 917 -       {0x0000a3a0, 0xb79f6427},
 918 -       {0x0000a3a4, 0x00000000},
 919 -       {0x0000a3a8, 0xaaaaaaaa},
 920 -       {0x0000a3ac, 0x3c466478},
 921 -       {0x0000a3c0, 0x20202020},
 922 -       {0x0000a3c4, 0x22222220},
 923 -       {0x0000a3c8, 0x20200020},
 924 -       {0x0000a3cc, 0x20202020},
 925 -       {0x0000a3d0, 0x20202020},
 926 -       {0x0000a3d4, 0x20202020},
 927 -       {0x0000a3d8, 0x20202020},
 928 -       {0x0000a3dc, 0x20202020},
 929 -       {0x0000a3e0, 0x20202020},
 930 -       {0x0000a3e4, 0x20202020},
 931 -       {0x0000a3e8, 0x20202020},
 932 -       {0x0000a3ec, 0x20202020},
 933 -       {0x0000a3f0, 0x00000000},
 934 -       {0x0000a3f4, 0x00000006},
 935 -       {0x0000a3f8, 0x0cdbd380},
 936 -       {0x0000a3fc, 0x000f0f01},
 937 -       {0x0000a400, 0x8fa91f01},
 938 -       {0x0000a404, 0x00000000},
 939 -       {0x0000a408, 0x0e79e5c6},
 940 -       {0x0000a40c, 0x00820820},
 941 -       {0x0000a414, 0x1ce739ce},
 942 -       {0x0000a418, 0x2d0011ce},
 943 -       {0x0000a41c, 0x1ce739ce},
 944 -       {0x0000a420, 0x000001ce},
 945 -       {0x0000a424, 0x1ce739ce},
 946 -       {0x0000a428, 0x000001ce},
 947 -       {0x0000a42c, 0x1ce739ce},
 948 -       {0x0000a430, 0x1ce739ce},
 949 -       {0x0000a434, 0x00000000},
 950 -       {0x0000a438, 0x00001801},
 951 -       {0x0000a43c, 0x00000000},
 952 -       {0x0000a440, 0x00000000},
 953 -       {0x0000a444, 0x00000000},
 954 -       {0x0000a448, 0x04000000},
 955 -       {0x0000a44c, 0x00000001},
 956 -       {0x0000a450, 0x00010000},
 957 -       {0x0000a458, 0x00000000},
 958 -       {0x0000a5c4, 0x3fad9d74},
 959 -       {0x0000a5c8, 0x0048060a},
 960 -       {0x0000a5cc, 0x00000637},
 961 -       {0x0000a760, 0x03020100},
 962 -       {0x0000a764, 0x09080504},
 963 -       {0x0000a768, 0x0d0c0b0a},
 964 -       {0x0000a76c, 0x13121110},
 965 -       {0x0000a770, 0x31301514},
 966 -       {0x0000a774, 0x35343332},
 967 -       {0x0000a778, 0x00000036},
 968 -       {0x0000a780, 0x00000838},
 969 -       {0x0000a7c0, 0x00000000},
 970 -       {0x0000a7c4, 0xfffffffc},
 971 -       {0x0000a7c8, 0x00000000},
 972 -       {0x0000a7cc, 0x00000000},
 973 -       {0x0000a7d0, 0x00000000},
 974 -       {0x0000a7d4, 0x00000004},
 975 -       {0x0000a7dc, 0x00000001},
 976 -};
 977 -
 978 -static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
 979 -       /* Addr        5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
 980 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
 981 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
 982 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
 983 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
 984 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
 985 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
 986 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
 987 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
 988 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
 989 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
 990 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
 991 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
 992 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
 993 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
 994 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
 995 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
 996 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
 997 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
 998 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
 999 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
1000 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
1001 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
1002 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
1003 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
1004 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
1005 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
1006 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
1007 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1008 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1009 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1010 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1011 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1012 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1013 -       {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
1014 -};
1015 -
1016 -static const u32 ar9485Common_rx_gain_1_0[][2] = {
1017 -       /* Addr      allmodes  */
1018 -       {0x0000a000, 0x00010000},
1019 -       {0x0000a004, 0x00030002},
1020 -       {0x0000a008, 0x00050004},
1021 -       {0x0000a00c, 0x00810080},
1022 -       {0x0000a010, 0x01800082},
1023 -       {0x0000a014, 0x01820181},
1024 -       {0x0000a018, 0x01840183},
1025 -       {0x0000a01c, 0x01880185},
1026 -       {0x0000a020, 0x018a0189},
1027 -       {0x0000a024, 0x02850284},
1028 -       {0x0000a028, 0x02890288},
1029 -       {0x0000a02c, 0x03850384},
1030 -       {0x0000a030, 0x03890388},
1031 -       {0x0000a034, 0x038b038a},
1032 -       {0x0000a038, 0x038d038c},
1033 -       {0x0000a03c, 0x03910390},
1034 -       {0x0000a040, 0x03930392},
1035 -       {0x0000a044, 0x03950394},
1036 -       {0x0000a048, 0x00000396},
1037 -       {0x0000a04c, 0x00000000},
1038 -       {0x0000a050, 0x00000000},
1039 -       {0x0000a054, 0x00000000},
1040 -       {0x0000a058, 0x00000000},
1041 -       {0x0000a05c, 0x00000000},
1042 -       {0x0000a060, 0x00000000},
1043 -       {0x0000a064, 0x00000000},
1044 -       {0x0000a068, 0x00000000},
1045 -       {0x0000a06c, 0x00000000},
1046 -       {0x0000a070, 0x00000000},
1047 -       {0x0000a074, 0x00000000},
1048 -       {0x0000a078, 0x00000000},
1049 -       {0x0000a07c, 0x00000000},
1050 -       {0x0000a080, 0x28282828},
1051 -       {0x0000a084, 0x28282828},
1052 -       {0x0000a088, 0x28282828},
1053 -       {0x0000a08c, 0x28282828},
1054 -       {0x0000a090, 0x28282828},
1055 -       {0x0000a094, 0x21212128},
1056 -       {0x0000a098, 0x171c1c1c},
1057 -       {0x0000a09c, 0x02020212},
1058 -       {0x0000a0a0, 0x00000202},
1059 -       {0x0000a0a4, 0x00000000},
1060 -       {0x0000a0a8, 0x00000000},
1061 -       {0x0000a0ac, 0x00000000},
1062 -       {0x0000a0b0, 0x00000000},
1063 -       {0x0000a0b4, 0x00000000},
1064 -       {0x0000a0b8, 0x00000000},
1065 -       {0x0000a0bc, 0x00000000},
1066 -       {0x0000a0c0, 0x001f0000},
1067 -       {0x0000a0c4, 0x111f1100},
1068 -       {0x0000a0c8, 0x111d111e},
1069 -       {0x0000a0cc, 0x111b111c},
1070 -       {0x0000a0d0, 0x22032204},
1071 -       {0x0000a0d4, 0x22012202},
1072 -       {0x0000a0d8, 0x221f2200},
1073 -       {0x0000a0dc, 0x221d221e},
1074 -       {0x0000a0e0, 0x33013302},
1075 -       {0x0000a0e4, 0x331f3300},
1076 -       {0x0000a0e8, 0x4402331e},
1077 -       {0x0000a0ec, 0x44004401},
1078 -       {0x0000a0f0, 0x441e441f},
1079 -       {0x0000a0f4, 0x55015502},
1080 -       {0x0000a0f8, 0x551f5500},
1081 -       {0x0000a0fc, 0x6602551e},
1082 -       {0x0000a100, 0x66006601},
1083 -       {0x0000a104, 0x661e661f},
1084 -       {0x0000a108, 0x7703661d},
1085 -       {0x0000a10c, 0x77017702},
1086 -       {0x0000a110, 0x00007700},
1087 -       {0x0000a114, 0x00000000},
1088 -       {0x0000a118, 0x00000000},
1089 -       {0x0000a11c, 0x00000000},
1090 -       {0x0000a120, 0x00000000},
1091 -       {0x0000a124, 0x00000000},
1092 -       {0x0000a128, 0x00000000},
1093 -       {0x0000a12c, 0x00000000},
1094 -       {0x0000a130, 0x00000000},
1095 -       {0x0000a134, 0x00000000},
1096 -       {0x0000a138, 0x00000000},
1097 -       {0x0000a13c, 0x00000000},
1098 -       {0x0000a140, 0x001f0000},
1099 -       {0x0000a144, 0x111f1100},
1100 -       {0x0000a148, 0x111d111e},
1101 -       {0x0000a14c, 0x111b111c},
1102 -       {0x0000a150, 0x22032204},
1103 -       {0x0000a154, 0x22012202},
1104 -       {0x0000a158, 0x221f2200},
1105 -       {0x0000a15c, 0x221d221e},
1106 -       {0x0000a160, 0x33013302},
1107 -       {0x0000a164, 0x331f3300},
1108 -       {0x0000a168, 0x4402331e},
1109 -       {0x0000a16c, 0x44004401},
1110 -       {0x0000a170, 0x441e441f},
1111 -       {0x0000a174, 0x55015502},
1112 -       {0x0000a178, 0x551f5500},
1113 -       {0x0000a17c, 0x6602551e},
1114 -       {0x0000a180, 0x66006601},
1115 -       {0x0000a184, 0x661e661f},
1116 -       {0x0000a188, 0x7703661d},
1117 -       {0x0000a18c, 0x77017702},
1118 -       {0x0000a190, 0x00007700},
1119 -       {0x0000a194, 0x00000000},
1120 -       {0x0000a198, 0x00000000},
1121 -       {0x0000a19c, 0x00000000},
1122 -       {0x0000a1a0, 0x00000000},
1123 -       {0x0000a1a4, 0x00000000},
1124 -       {0x0000a1a8, 0x00000000},
1125 -       {0x0000a1ac, 0x00000000},
1126 -       {0x0000a1b0, 0x00000000},
1127 -       {0x0000a1b4, 0x00000000},
1128 -       {0x0000a1b8, 0x00000000},
1129 -       {0x0000a1bc, 0x00000000},
1130 -       {0x0000a1c0, 0x00000000},
1131 -       {0x0000a1c4, 0x00000000},
1132 -       {0x0000a1c8, 0x00000000},
1133 -       {0x0000a1cc, 0x00000000},
1134 -       {0x0000a1d0, 0x00000000},
1135 -       {0x0000a1d4, 0x00000000},
1136 -       {0x0000a1d8, 0x00000000},
1137 -       {0x0000a1dc, 0x00000000},
1138 -       {0x0000a1e0, 0x00000000},
1139 -       {0x0000a1e4, 0x00000000},
1140 -       {0x0000a1e8, 0x00000000},
1141 -       {0x0000a1ec, 0x00000000},
1142 -       {0x0000a1f0, 0x00000396},
1143 -       {0x0000a1f4, 0x00000396},
1144 -       {0x0000a1f8, 0x00000396},
1145 -       {0x0000a1fc, 0x00000296},
1146 -};
1147 -
1148 -static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
1149 -       /*   Addr    allmodes  */
1150 -       {0x00018c00, 0x10252e5e},
1151 -       {0x00018c04, 0x000801d8},
1152 -       {0x00018c08, 0x0000580c},
1153 -};
1154 -
1155 -static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
1156 -       /*  Addr    allmodes   */
1157 -       {0x00018c00, 0x10253e5e},
1158 -       {0x00018c04, 0x000801d8},
1159 -       {0x00018c08, 0x0000580c},
1160 -};
1161 -
1162 -static const u32 ar9485_1_0_soc_preamble[][2] = {
1163 -       /*   Addr     allmodes */
1164 -       {0x00004090, 0x00aa10aa},
1165 -       {0x000040a4, 0x00a0c9c9},
1166 -       {0x00007048, 0x00000004},
1167 -};
1168 -
1169 -static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
1170 -       /*   Addr      5G_HT20     5G_HT40 */
1171 -       {0x00009e00, 0x03721821, 0x03721821},
1172 -       {0x0000a230, 0x0000400b, 0x00004016},
1173 -       {0x0000a254, 0x00000898, 0x00001130},
1174 -};
1175 -
1176 -static const u32 ar9485_1_0_baseband_postamble[][5] = {
1177 -       /* Addr        5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
1178 -       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
1179 -       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
1180 -       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
1181 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
1182 -       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
1183 -       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
1184 -       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
1185 -       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
1186 -       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
1187 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
1188 -       {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
1189 -       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
1190 -       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1191 -       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
1192 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
1193 -       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
1194 -       {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
1195 -       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
1196 -       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
1197 -       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
1198 -       {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
1199 -       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
1200 -       {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
1201 -       {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
1202 -       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
1203 -       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
1204 -       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
1205 -       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
1206 -       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
1207 -       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
1208 -       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
1209 -       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
1210 -       {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
1211 -       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1212 -       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1213 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
1214 -       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
1215 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
1216 -       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1217 -       {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
1218 -       {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1219 -};
1220 -
1221 -static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
1222 -       /*  Addr      5G_HT20    5G_HT40     2G_HT40     2G_HT20   */
1223 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
1224 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
1225 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
1226 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
1227 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
1228 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
1229 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
1230 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
1231 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
1232 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
1233 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
1234 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
1235 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
1236 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
1237 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
1238 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
1239 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
1240 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
1241 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
1242 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
1243 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
1244 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
1245 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
1246 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
1247 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
1248 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
1249 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
1250 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1251 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1252 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1253 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1254 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1255 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
1256 -       {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
1257 -};
1258 -
1259 -static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
1260 -       /*   Addr     allmodes */
1261 -       {0x00018c00, 0x10213e5e},
1262 -       {0x00018c04, 0x000801d8},
1263 -       {0x00018c08, 0x0000580c},
1264 -};
1265 -
1266 -static const u32 ar9485_1_0_radio_postamble[][2] = {
1267 -       /*   Addr     allmodes */
1268 -       {0x0001609c, 0x0b283f31},
1269 -       {0x000160ac, 0x24611800},
1270 -       {0x000160b0, 0x03284f3e},
1271 -       {0x0001610c, 0x00170000},
1272 -       {0x00016140, 0x10804008},
1273 -};
1274 -
1275 -static const u32 ar9485_1_0_mac_core[][2] = {
1276 -       /*  Addr      allmodes */
1277 -       {0x00000008, 0x00000000},
1278 -       {0x00000030, 0x00020085},
1279 -       {0x00000034, 0x00000005},
1280 -       {0x00000040, 0x00000000},
1281 -       {0x00000044, 0x00000000},
1282 -       {0x00000048, 0x00000008},
1283 -       {0x0000004c, 0x00000010},
1284 -       {0x00000050, 0x00000000},
1285 -       {0x00001040, 0x002ffc0f},
1286 -       {0x00001044, 0x002ffc0f},
1287 -       {0x00001048, 0x002ffc0f},
1288 -       {0x0000104c, 0x002ffc0f},
1289 -       {0x00001050, 0x002ffc0f},
1290 -       {0x00001054, 0x002ffc0f},
1291 -       {0x00001058, 0x002ffc0f},
1292 -       {0x0000105c, 0x002ffc0f},
1293 -       {0x00001060, 0x002ffc0f},
1294 -       {0x00001064, 0x002ffc0f},
1295 -       {0x000010f0, 0x00000100},
1296 -       {0x00001270, 0x00000000},
1297 -       {0x000012b0, 0x00000000},
1298 -       {0x000012f0, 0x00000000},
1299 -       {0x0000143c, 0x00000000},
1300 -       {0x0000147c, 0x00000000},
1301 -       {0x00008000, 0x00000000},
1302 -       {0x00008004, 0x00000000},
1303 -       {0x00008008, 0x00000000},
1304 -       {0x0000800c, 0x00000000},
1305 -       {0x00008018, 0x00000000},
1306 -       {0x00008020, 0x00000000},
1307 -       {0x00008038, 0x00000000},
1308 -       {0x0000803c, 0x00000000},
1309 -       {0x00008040, 0x00000000},
1310 -       {0x00008044, 0x00000000},
1311 -       {0x00008048, 0x00000000},
1312 -       {0x0000804c, 0xffffffff},
1313 -       {0x00008054, 0x00000000},
1314 -       {0x00008058, 0x00000000},
1315 -       {0x0000805c, 0x000fc78f},
1316 -       {0x00008060, 0x0000000f},
1317 -       {0x00008064, 0x00000000},
1318 -       {0x00008070, 0x00000310},
1319 -       {0x00008074, 0x00000020},
1320 -       {0x00008078, 0x00000000},
1321 -       {0x0000809c, 0x0000000f},
1322 -       {0x000080a0, 0x00000000},
1323 -       {0x000080a4, 0x02ff0000},
1324 -       {0x000080a8, 0x0e070605},
1325 -       {0x000080ac, 0x0000000d},
1326 -       {0x000080b0, 0x00000000},
1327 -       {0x000080b4, 0x00000000},
1328 -       {0x000080b8, 0x00000000},
1329 -       {0x000080bc, 0x00000000},
1330 -       {0x000080c0, 0x2a800000},
1331 -       {0x000080c4, 0x06900168},
1332 -       {0x000080c8, 0x13881c20},
1333 -       {0x000080cc, 0x01f40000},
1334 -       {0x000080d0, 0x00252500},
1335 -       {0x000080d4, 0x00a00000},
1336 -       {0x000080d8, 0x00400000},
1337 -       {0x000080dc, 0x00000000},
1338 -       {0x000080e0, 0xffffffff},
1339 -       {0x000080e4, 0x0000ffff},
1340 -       {0x000080e8, 0x3f3f3f3f},
1341 -       {0x000080ec, 0x00000000},
1342 -       {0x000080f0, 0x00000000},
1343 -       {0x000080f4, 0x00000000},
1344 -       {0x000080fc, 0x00020000},
1345 -       {0x00008100, 0x00000000},
1346 -       {0x00008108, 0x00000052},
1347 -       {0x0000810c, 0x00000000},
1348 -       {0x00008110, 0x00000000},
1349 -       {0x00008114, 0x000007ff},
1350 -       {0x00008118, 0x000000aa},
1351 -       {0x0000811c, 0x00003210},
1352 -       {0x00008124, 0x00000000},
1353 -       {0x00008128, 0x00000000},
1354 -       {0x0000812c, 0x00000000},
1355 -       {0x00008130, 0x00000000},
1356 -       {0x00008134, 0x00000000},
1357 -       {0x00008138, 0x00000000},
1358 -       {0x0000813c, 0x0000ffff},
1359 -       {0x00008144, 0xffffffff},
1360 -       {0x00008168, 0x00000000},
1361 -       {0x0000816c, 0x00000000},
1362 -       {0x00008170, 0x18486200},
1363 -       {0x00008174, 0x33332210},
1364 -       {0x00008178, 0x00000000},
1365 -       {0x0000817c, 0x00020000},
1366 -       {0x000081c0, 0x00000000},
1367 -       {0x000081c4, 0x33332210},
1368 -       {0x000081c8, 0x00000000},
1369 -       {0x000081cc, 0x00000000},
1370 -       {0x000081d4, 0x00000000},
1371 -       {0x000081ec, 0x00000000},
1372 -       {0x000081f0, 0x00000000},
1373 -       {0x000081f4, 0x00000000},
1374 -       {0x000081f8, 0x00000000},
1375 -       {0x000081fc, 0x00000000},
1376 -       {0x00008240, 0x00100000},
1377 -       {0x00008244, 0x0010f400},
1378 -       {0x00008248, 0x00000800},
1379 -       {0x0000824c, 0x0001e800},
1380 -       {0x00008250, 0x00000000},
1381 -       {0x00008254, 0x00000000},
1382 -       {0x00008258, 0x00000000},
1383 -       {0x0000825c, 0x40000000},
1384 -       {0x00008260, 0x00080922},
1385 -       {0x00008264, 0x9ca00010},
1386 -       {0x00008268, 0xffffffff},
1387 -       {0x0000826c, 0x0000ffff},
1388 -       {0x00008270, 0x00000000},
1389 -       {0x00008274, 0x40000000},
1390 -       {0x00008278, 0x003e4180},
1391 -       {0x0000827c, 0x00000004},
1392 -       {0x00008284, 0x0000002c},
1393 -       {0x00008288, 0x0000002c},
1394 -       {0x0000828c, 0x000000ff},
1395 -       {0x00008294, 0x00000000},
1396 -       {0x00008298, 0x00000000},
1397 -       {0x0000829c, 0x00000000},
1398 -       {0x00008300, 0x00000140},
1399 -       {0x00008314, 0x00000000},
1400 -       {0x0000831c, 0x0000010d},
1401 -       {0x00008328, 0x00000000},
1402 -       {0x0000832c, 0x00000007},
1403 -       {0x00008330, 0x00000302},
1404 -       {0x00008334, 0x00000700},
1405 -       {0x00008338, 0x00ff0000},
1406 -       {0x0000833c, 0x02400000},
1407 -       {0x00008340, 0x000107ff},
1408 -       {0x00008344, 0xa248105b},
1409 -       {0x00008348, 0x008f0000},
1410 -       {0x0000835c, 0x00000000},
1411 -       {0x00008360, 0xffffffff},
1412 -       {0x00008364, 0xffffffff},
1413 -       {0x00008368, 0x00000000},
1414 -       {0x00008370, 0x00000000},
1415 -       {0x00008374, 0x000000ff},
1416 -       {0x00008378, 0x00000000},
1417 -       {0x0000837c, 0x00000000},
1418 -       {0x00008380, 0xffffffff},
1419 -       {0x00008384, 0xffffffff},
1420 -       {0x00008390, 0xffffffff},
1421 -       {0x00008394, 0xffffffff},
1422 -       {0x00008398, 0x00000000},
1423 -       {0x0000839c, 0x00000000},
1424 -       {0x000083a0, 0x00000000},
1425 -       {0x000083a4, 0x0000fa14},
1426 -       {0x000083a8, 0x000f0c00},
1427 -       {0x000083ac, 0x33332210},
1428 -       {0x000083b0, 0x33332210},
1429 -       {0x000083b4, 0x33332210},
1430 -       {0x000083b8, 0x33332210},
1431 -       {0x000083bc, 0x00000000},
1432 -       {0x000083c0, 0x00000000},
1433 -       {0x000083c4, 0x00000000},
1434 -       {0x000083c8, 0x00000000},
1435 -       {0x000083cc, 0x00000200},
1436 -       {0x000083d0, 0x000301ff},
1437 -};
1438 -
1439  static const u32 ar9485_1_1_mac_core[][2] = {
1440         /*  Addr       allmodes */
1441         {0x00000008, 0x00000000},