package/mac80211/patches/303-rt2x00-Implement-support-for-rt2800usb.patch

   1 From b249bc450f982cd2491448c91faf797ed37b69b8 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Tue, 3 Mar 2009 19:25:49 +0100
   4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
   5
   6 Add support for the rt2800usb chipset.
   7
   8 Includes various patches from Mattias, Felix, Xose and Axel.
   9
  10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  12 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
  13 Signed-off-by: Axel Kollhofer <rain_maker@root-forum.org>
  14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  15 ---
  16  drivers/net/wireless/rt2x00/Kconfig     |   14 +
  17  drivers/net/wireless/rt2x00/Makefile    |    1 +
  18  drivers/net/wireless/rt2x00/rt2800usb.c | 3032 +++++++++++++++++++++++++++++++
  19  drivers/net/wireless/rt2x00/rt2800usb.h | 1932 ++++++++++++++++++++
  20  drivers/net/wireless/rt2x00/rt2x00.h    |    7 +
  21  5 files changed, 4986 insertions(+), 0 deletions(-)
  22  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
  23  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
  24
  25 --- a/drivers/net/wireless/rt2x00/Makefile
  26 +++ b/drivers/net/wireless/rt2x00/Makefile
  27 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI)                 += rt61pci.o
  28  obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  29  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  30  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  31 +obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  32 --- /dev/null
  33 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
  34 @@ -0,0 +1,3032 @@
  35 +/*
  36 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  37 +       <http://rt2x00.serialmonkey.com>
  38 +
  39 +       This program is free software; you can redistribute it and/or modify
  40 +       it under the terms of the GNU General Public License as published by
  41 +       the Free Software Foundation; either version 2 of the License, or
  42 +       (at your option) any later version.
  43 +
  44 +       This program is distributed in the hope that it will be useful,
  45 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  46 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  47 +       GNU General Public License for more details.
  48 +
  49 +       You should have received a copy of the GNU General Public License
  50 +       along with this program; if not, write to the
  51 +       Free Software Foundation, Inc.,
  52 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  53 + */
  54 +
  55 +/*
  56 +       Module: rt2800usb
  57 +       Abstract: rt2800usb device specific routines.
  58 +       Supported chipsets: RT2800U.
  59 + */
  60 +
  61 +#include <linux/crc-ccitt.h>
  62 +#include <linux/delay.h>
  63 +#include <linux/etherdevice.h>
  64 +#include <linux/init.h>
  65 +#include <linux/kernel.h>
  66 +#include <linux/module.h>
  67 +#include <linux/usb.h>
  68 +
  69 +#include "rt2x00.h"
  70 +#include "rt2x00usb.h"
  71 +#include "rt2800usb.h"
  72 +
  73 +/*
  74 + * Allow hardware encryption to be disabled.
  75 + */
  76 +static int modparam_nohwcrypt = 0;
  77 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  78 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  79 +
  80 +/*
  81 + * Register access.
  82 + * All access to the CSR registers will go through the methods
  83 + * rt2x00usb_register_read and rt2x00usb_register_write.
  84 + * BBP and RF register require indirect register access,
  85 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
  86 + * These indirect registers work with busy bits,
  87 + * and we will try maximal REGISTER_BUSY_COUNT times to access
  88 + * the register while taking a REGISTER_BUSY_DELAY us delay
  89 + * between each attampt. When the busy bit is still set at that time,
  90 + * the access attempt is considered to have failed,
  91 + * and we will print an error.
  92 + * The _lock versions must be used if you already hold the csr_mutex
  93 + */
  94 +#define WAIT_FOR_BBP(__dev, __reg) \
  95 +       rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  96 +#define WAIT_FOR_RFCSR(__dev, __reg) \
  97 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  98 +#define WAIT_FOR_RF(__dev, __reg) \
  99 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 100 +#define WAIT_FOR_MCU(__dev, __reg) \
 101 +       rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
 102 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 103 +
 104 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 105 +                               const unsigned int word, const u8 value)
 106 +{
 107 +       u32 reg;
 108 +
 109 +       mutex_lock(&rt2x00dev->csr_mutex);
 110 +
 111 +       /*
 112 +        * Wait until the BBP becomes available, afterwards we
 113 +        * can safely write the new data into the register.
 114 +        */
 115 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 116 +               reg = 0;
 117 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 118 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 119 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 120 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 121 +
 122 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 123 +       }
 124 +
 125 +       mutex_unlock(&rt2x00dev->csr_mutex);
 126 +}
 127 +
 128 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 129 +                              const unsigned int word, u8 *value)
 130 +{
 131 +       u32 reg;
 132 +
 133 +       mutex_lock(&rt2x00dev->csr_mutex);
 134 +
 135 +       /*
 136 +        * Wait until the BBP becomes available, afterwards we
 137 +        * can safely write the read request into the register.
 138 +        * After the data has been written, we wait until hardware
 139 +        * returns the correct value, if at any time the register
 140 +        * doesn't become available in time, reg will be 0xffffffff
 141 +        * which means we return 0xff to the caller.
 142 +        */
 143 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 144 +               reg = 0;
 145 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 146 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 147 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 148 +
 149 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 150 +
 151 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 152 +       }
 153 +
 154 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 155 +
 156 +       mutex_unlock(&rt2x00dev->csr_mutex);
 157 +}
 158 +
 159 +static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 160 +                                 const unsigned int word, const u8 value)
 161 +{
 162 +       u32 reg;
 163 +
 164 +       mutex_lock(&rt2x00dev->csr_mutex);
 165 +
 166 +       /*
 167 +        * Wait until the RFCSR becomes available, afterwards we
 168 +        * can safely write the new data into the register.
 169 +        */
 170 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 171 +               reg = 0;
 172 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 173 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 174 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 175 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 176 +
 177 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 178 +       }
 179 +
 180 +       mutex_unlock(&rt2x00dev->csr_mutex);
 181 +}
 182 +
 183 +static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 184 +                                const unsigned int word, u8 *value)
 185 +{
 186 +       u32 reg;
 187 +
 188 +       mutex_lock(&rt2x00dev->csr_mutex);
 189 +
 190 +       /*
 191 +        * Wait until the RFCSR becomes available, afterwards we
 192 +        * can safely write the read request into the register.
 193 +        * After the data has been written, we wait until hardware
 194 +        * returns the correct value, if at any time the register
 195 +        * doesn't become available in time, reg will be 0xffffffff
 196 +        * which means we return 0xff to the caller.
 197 +        */
 198 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 199 +               reg = 0;
 200 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 201 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 202 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 203 +
 204 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 205 +
 206 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 207 +       }
 208 +
 209 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 210 +
 211 +       mutex_unlock(&rt2x00dev->csr_mutex);
 212 +}
 213 +
 214 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 215 +                              const unsigned int word, const u32 value)
 216 +{
 217 +       u32 reg;
 218 +
 219 +       mutex_lock(&rt2x00dev->csr_mutex);
 220 +
 221 +       /*
 222 +        * Wait until the RF becomes available, afterwards we
 223 +        * can safely write the new data into the register.
 224 +        */
 225 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 226 +               reg = 0;
 227 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 228 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 229 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 230 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 231 +
 232 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 233 +               rt2x00_rf_write(rt2x00dev, word, value);
 234 +       }
 235 +
 236 +       mutex_unlock(&rt2x00dev->csr_mutex);
 237 +}
 238 +
 239 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 240 +                                 const u8 command, const u8 token,
 241 +                                 const u8 arg0, const u8 arg1)
 242 +{
 243 +       u32 reg;
 244 +
 245 +       mutex_lock(&rt2x00dev->csr_mutex);
 246 +
 247 +       /*
 248 +        * Wait until the MCU becomes available, afterwards we
 249 +        * can safely write the new data into the register.
 250 +        */
 251 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 252 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 253 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 254 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 255 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 256 +               rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 257 +
 258 +               reg = 0;
 259 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 260 +               rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 261 +       }
 262 +
 263 +       mutex_unlock(&rt2x00dev->csr_mutex);
 264 +}
 265 +
 266 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 267 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
 268 +       .owner  = THIS_MODULE,
 269 +       .csr    = {
 270 +               .read           = rt2x00usb_register_read,
 271 +               .write          = rt2x00usb_register_write,
 272 +               .flags          = RT2X00DEBUGFS_OFFSET,
 273 +               .word_base      = CSR_REG_BASE,
 274 +               .word_size      = sizeof(u32),
 275 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 276 +       },
 277 +       .eeprom = {
 278 +               .read           = rt2x00_eeprom_read,
 279 +               .write          = rt2x00_eeprom_write,
 280 +               .word_base      = EEPROM_BASE,
 281 +               .word_size      = sizeof(u16),
 282 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 283 +       },
 284 +       .bbp    = {
 285 +               .read           = rt2800usb_bbp_read,
 286 +               .write          = rt2800usb_bbp_write,
 287 +               .word_base      = BBP_BASE,
 288 +               .word_size      = sizeof(u8),
 289 +               .word_count     = BBP_SIZE / sizeof(u8),
 290 +       },
 291 +       .rf     = {
 292 +               .read           = rt2x00_rf_read,
 293 +               .write          = rt2800usb_rf_write,
 294 +               .word_base      = RF_BASE,
 295 +               .word_size      = sizeof(u32),
 296 +               .word_count     = RF_SIZE / sizeof(u32),
 297 +       },
 298 +};
 299 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 300 +
 301 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 302 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 303 +{
 304 +       u32 reg;
 305 +
 306 +       rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 307 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 308 +}
 309 +#else
 310 +#define rt2800usb_rfkill_poll  NULL
 311 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 312 +
 313 +#ifdef CONFIG_RT2X00_LIB_LEDS
 314 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 315 +                                    enum led_brightness brightness)
 316 +{
 317 +       struct rt2x00_led *led =
 318 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 319 +       unsigned int enabled = brightness != LED_OFF;
 320 +       unsigned int bg_mode =
 321 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 322 +       unsigned int polarity =
 323 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 324 +                                  EEPROM_FREQ_LED_POLARITY);
 325 +       unsigned int ledmode =
 326 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 327 +                                  EEPROM_FREQ_LED_MODE);
 328 +
 329 +       if (led->type == LED_TYPE_RADIO) {
 330 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 331 +                                     enabled ? 0x20 : 0);
 332 +       } else if (led->type == LED_TYPE_ASSOC) {
 333 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 334 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 335 +       } else if (led->type == LED_TYPE_QUALITY) {
 336 +               /*
 337 +                * The brightness is divided into 6 levels (0 - 5),
 338 +                * The specs tell us the following levels:
 339 +                *      0, 1 ,3, 7, 15, 31
 340 +                * to determine the level in a simple way we can simply
 341 +                * work with bitshifting:
 342 +                *      (1 << level) - 1
 343 +                */
 344 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 345 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 346 +                                     polarity);
 347 +       }
 348 +}
 349 +
 350 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 351 +                              unsigned long *delay_on,
 352 +                              unsigned long *delay_off)
 353 +{
 354 +       struct rt2x00_led *led =
 355 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 356 +       u32 reg;
 357 +
 358 +       rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
 359 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 360 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 361 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 362 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 363 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 364 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 365 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 366 +       rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
 367 +
 368 +       return 0;
 369 +}
 370 +
 371 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 372 +                              struct rt2x00_led *led,
 373 +                              enum led_type type)
 374 +{
 375 +       led->rt2x00dev = rt2x00dev;
 376 +       led->type = type;
 377 +       led->led_dev.brightness_set = rt2800usb_brightness_set;
 378 +       led->led_dev.blink_set = rt2800usb_blink_set;
 379 +       led->flags = LED_INITIALIZED;
 380 +}
 381 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 382 +
 383 +/*
 384 + * Configuration handlers.
 385 + */
 386 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 387 +                                      struct rt2x00lib_crypto *crypto,
 388 +                                      struct ieee80211_key_conf *key)
 389 +{
 390 +       struct mac_wcid_entry wcid_entry;
 391 +       struct mac_iveiv_entry iveiv_entry;
 392 +       u32 offset;
 393 +       u32 reg;
 394 +
 395 +       offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 396 +
 397 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 398 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 399 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 400 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
 401 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 402 +                          (crypto->cmd == SET_KEY) * crypto->bssidx);
 403 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 404 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 405 +
 406 +       offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 407 +
 408 +       memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 409 +       if ((crypto->cipher == CIPHER_TKIP) ||
 410 +           (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 411 +           (crypto->cipher == CIPHER_AES))
 412 +               iveiv_entry.iv[3] |= 0x20;
 413 +       iveiv_entry.iv[3] |= key->keyidx << 6;
 414 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 415 +                                     &iveiv_entry, sizeof(iveiv_entry));
 416 +
 417 +       offset = MAC_WCID_ENTRY(key->hw_key_idx);
 418 +
 419 +       memset(&wcid_entry, 0, sizeof(wcid_entry));
 420 +       if (crypto->cmd == SET_KEY)
 421 +               memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 422 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 423 +                                     &wcid_entry, sizeof(wcid_entry));
 424 +}
 425 +
 426 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 427 +                                      struct rt2x00lib_crypto *crypto,
 428 +                                      struct ieee80211_key_conf *key)
 429 +{
 430 +       struct hw_key_entry key_entry;
 431 +       struct rt2x00_field32 field;
 432 +       int timeout;
 433 +       u32 offset;
 434 +       u32 reg;
 435 +
 436 +       if (crypto->cmd == SET_KEY) {
 437 +               key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 438 +
 439 +               memcpy(key_entry.key, crypto->key,
 440 +                      sizeof(key_entry.key));
 441 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 442 +                      sizeof(key_entry.tx_mic));
 443 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 444 +                      sizeof(key_entry.rx_mic));
 445 +
 446 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 447 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 448 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 449 +                                                   USB_VENDOR_REQUEST_OUT,
 450 +                                                   offset, &key_entry,
 451 +                                                   sizeof(key_entry),
 452 +                                                   timeout);
 453 +       }
 454 +
 455 +       /*
 456 +        * The cipher types are stored over multiple registers
 457 +        * starting with SHARED_KEY_MODE_BASE each word will have
 458 +        * 32 bits and contains the cipher types for 2 bssidx each.
 459 +        * Using the correct defines correctly will cause overhead,
 460 +        * so just calculate the correct offset.
 461 +        */
 462 +       field.bit_offset = (4 * key->keyidx) + (16 * (crypto->bssidx & 1));
 463 +       field.bit_mask = 0x7 << field.bit_offset;
 464 +
 465 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 2);
 466 +
 467 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 468 +       rt2x00_set_field32(&reg, field,
 469 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 470 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 471 +
 472 +       /*
 473 +        * Update WCID information
 474 +        */
 475 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 476 +
 477 +       return 0;
 478 +}
 479 +
 480 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 481 +                                        struct rt2x00lib_crypto *crypto,
 482 +                                        struct ieee80211_key_conf *key)
 483 +{
 484 +       struct hw_key_entry key_entry;
 485 +       int timeout;
 486 +       u32 offset;
 487 +
 488 +       if (crypto->cmd == SET_KEY) {
 489 +               /*
 490 +                * 1 pairwise key is possible per AID, this means that the AID
 491 +                * equals our hw_key_idx.
 492 +                */
 493 +               key->hw_key_idx = crypto->aid;
 494 +
 495 +               memcpy(key_entry.key, crypto->key,
 496 +                      sizeof(key_entry.key));
 497 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 498 +                      sizeof(key_entry.tx_mic));
 499 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 500 +                      sizeof(key_entry.rx_mic));
 501 +
 502 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 503 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 504 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 505 +                                                   USB_VENDOR_REQUEST_OUT,
 506 +                                                   offset, &key_entry,
 507 +                                                   sizeof(key_entry),
 508 +                                                   timeout);
 509 +       }
 510 +
 511 +       /*
 512 +        * Update WCID information
 513 +        */
 514 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 515 +
 516 +       return 0;
 517 +}
 518 +
 519 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 520 +                                   const unsigned int filter_flags)
 521 +{
 522 +       u32 reg;
 523 +
 524 +       /*
 525 +        * Start configuration steps.
 526 +        * Note that the version error will always be dropped
 527 +        * and broadcast frames will always be accepted since
 528 +        * there is no filter for it at this time.
 529 +        */
 530 +       rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 531 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 532 +                          !(filter_flags & FIF_FCSFAIL));
 533 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 534 +                          !(filter_flags & FIF_PLCPFAIL));
 535 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 536 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 537 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 538 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 539 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 540 +                          !(filter_flags & FIF_ALLMULTI));
 541 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 542 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 543 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 544 +                          !(filter_flags & FIF_CONTROL));
 545 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 546 +                          !(filter_flags & FIF_CONTROL));
 547 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 548 +                          !(filter_flags & FIF_CONTROL));
 549 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 550 +                          !(filter_flags & FIF_CONTROL));
 551 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 552 +                          !(filter_flags & FIF_CONTROL));
 553 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 554 +                          !(filter_flags & FIF_CONTROL));
 555 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 556 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 557 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 558 +                          !(filter_flags & FIF_CONTROL));
 559 +       rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 560 +}
 561 +
 562 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 563 +                                 struct rt2x00_intf *intf,
 564 +                                 struct rt2x00intf_conf *conf,
 565 +                                 const unsigned int flags)
 566 +{
 567 +       unsigned int beacon_base;
 568 +       u32 reg;
 569 +
 570 +       if (flags & CONFIG_UPDATE_TYPE) {
 571 +               /*
 572 +                * Clear current synchronisation setup.
 573 +                * For the Beacon base registers we only need to clear
 574 +                * the first byte since that byte contains the VALID and OWNER
 575 +                * bits which (when set to 0) will invalidate the entire beacon.
 576 +                */
 577 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 578 +               rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 579 +
 580 +               /*
 581 +                * Enable synchronisation.
 582 +                */
 583 +               rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 584 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 585 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 586 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 587 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 588 +       }
 589 +
 590 +       if (flags & CONFIG_UPDATE_MAC) {
 591 +               reg = le32_to_cpu(conf->mac[1]);
 592 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 593 +               conf->mac[1] = cpu_to_le32(reg);
 594 +
 595 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 596 +                                             conf->mac, sizeof(conf->mac));
 597 +       }
 598 +
 599 +       if (flags & CONFIG_UPDATE_BSSID) {
 600 +               reg = le32_to_cpu(conf->bssid[1]);
 601 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 602 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 603 +               conf->bssid[1] = cpu_to_le32(reg);
 604 +
 605 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 606 +                                             conf->bssid, sizeof(conf->bssid));
 607 +       }
 608 +}
 609 +
 610 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 611 +                                struct rt2x00lib_erp *erp)
 612 +{
 613 +       u32 reg;
 614 +
 615 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 616 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 617 +                          DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
 618 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 619 +
 620 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 621 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 622 +                          !!erp->short_preamble);
 623 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 624 +                          !!erp->short_preamble);
 625 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 626 +
 627 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 628 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 629 +                          erp->cts_protection ? 2 : 0);
 630 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 631 +
 632 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 633 +                                erp->basic_rates);
 634 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 635 +
 636 +       rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 637 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 638 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 639 +       rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 640 +
 641 +       rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 642 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 643 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 644 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 645 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 646 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 647 +       rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 648 +}
 649 +
 650 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 651 +                                struct antenna_setup *ant)
 652 +{
 653 +       u16 eeprom;
 654 +       u8 r1;
 655 +       u8 r3;
 656 +
 657 +       /*
 658 +        * FIXME: Use requested antenna configuration.
 659 +        */
 660 +
 661 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 662 +
 663 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 664 +       rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 665 +
 666 +       /*
 667 +        * Configure the TX antenna.
 668 +        */
 669 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 670 +       case 1:
 671 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 672 +               break;
 673 +       case 2:
 674 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 675 +               break;
 676 +       case 3:
 677 +               /* Do nothing */
 678 +               break;
 679 +       }
 680 +
 681 +       /*
 682 +        * Configure the RX antenna.
 683 +        */
 684 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 685 +       case 1:
 686 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 687 +               break;
 688 +       case 2:
 689 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 690 +               break;
 691 +       case 3:
 692 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 693 +               break;
 694 +       }
 695 +
 696 +       rt2800usb_bbp_write(rt2x00dev, 3, r3);
 697 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 698 +}
 699 +
 700 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 701 +                                     struct rt2x00lib_conf *libconf)
 702 +{
 703 +       u16 eeprom;
 704 +       short lna_gain;
 705 +
 706 +       if (libconf->rf.channel <= 14) {
 707 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 708 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 709 +       } else if (libconf->rf.channel <= 64) {
 710 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 711 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 712 +       } else if (libconf->rf.channel <= 128) {
 713 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 714 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 715 +       } else {
 716 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 717 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 718 +       }
 719 +
 720 +       rt2x00dev->lna_gain = lna_gain;
 721 +}
 722 +
 723 +static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 724 +                                         struct ieee80211_conf *conf,
 725 +                                         struct rf_channel *rf,
 726 +                                         struct channel_info *info)
 727 +{
 728 +       u16 eeprom;
 729 +
 730 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 731 +
 732 +       /*
 733 +        * Determine antenna settings from EEPROM
 734 +        */
 735 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 736 +
 737 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
 738 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 739 +
 740 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 741 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 742 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 743 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 744 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 745 +
 746 +       if (rf->channel > 14) {
 747 +               /*
 748 +                * When TX power is below 0, we should increase it by 7 to
 749 +                * make it a positive value (Minumum value is -7).
 750 +                * However this means that values between 0 and 7 have
 751 +                * double meaning, and we should set a 7DBm boost flag.
 752 +                */
 753 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 754 +                                  (info->tx_power1 >= 0));
 755 +
 756 +               if (info->tx_power1 < 0)
 757 +                       info->tx_power1 += 7;
 758 +
 759 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 760 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 761 +
 762 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 763 +                                  (info->tx_power2 >= 0));
 764 +
 765 +               if (info->tx_power2 < 0)
 766 +                       info->tx_power2 += 7;
 767 +
 768 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 769 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 770 +       } else {
 771 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 772 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 773 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 774 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 775 +       }
 776 +
 777 +       rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 778 +
 779 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 780 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 781 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 782 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 783 +
 784 +       udelay(200);
 785 +
 786 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 787 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 788 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 789 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 790 +
 791 +       udelay(200);
 792 +
 793 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 794 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 795 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 796 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 797 +}
 798 +
 799 +static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 800 +                                         struct ieee80211_conf *conf,
 801 +                                         struct rf_channel *rf,
 802 +                                         struct channel_info *info)
 803 +{
 804 +       u8 rfcsr;
 805 +
 806 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 807 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 808 +
 809 +       rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 810 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 811 +       rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 812 +
 813 +       rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 814 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 815 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 816 +       rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 817 +
 818 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 819 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 820 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 821 +
 822 +       if (conf_is_ht40(conf))
 823 +               rt2800usb_rfcsr_write(rt2x00dev, 24,
 824 +                                     rt2x00dev->calibration_bw40);
 825 +       else
 826 +               rt2800usb_rfcsr_write(rt2x00dev, 24,
 827 +                                     rt2x00dev->calibration_bw20);
 828 +
 829 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 830 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 831 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 832 +}
 833 +
 834 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 835 +                                    struct ieee80211_conf *conf,
 836 +                                    struct rf_channel *rf,
 837 +                                    struct channel_info *info)
 838 +{
 839 +       u32 reg;
 840 +       unsigned int tx_pin;
 841 +       u16 eeprom;
 842 +       u8 bbp;
 843 +
 844 +       /*
 845 +        * Determine antenna settings from EEPROM
 846 +        */
 847 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 848 +
 849 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 850 +               rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 851 +       else
 852 +               rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 853 +
 854 +       /*
 855 +        * Change BBP settings
 856 +        */
 857 +       rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 858 +       rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 859 +       rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 860 +       rt2800usb_bbp_write(rt2x00dev, 86, 0);
 861 +
 862 +       if (rf->channel <= 14) {
 863 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 864 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 865 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 866 +               } else {
 867 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 868 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 869 +               }
 870 +       } else {
 871 +               rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 872 +
 873 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 874 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 875 +               else
 876 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 877 +       }
 878 +
 879 +       rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 880 +       rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 881 +       rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 882 +       rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 883 +       rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 884 +
 885 +       tx_pin = 0;
 886 +
 887 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 888 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
 889 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 890 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 891 +       }
 892 +
 893 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 894 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
 895 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 896 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 897 +       }
 898 +
 899 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 900 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 901 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 902 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 903 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 904 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 905 +
 906 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 907 +
 908 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
 909 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 910 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
 911 +
 912 +       rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
 913 +       rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 914 +       rt2800usb_bbp_write(rt2x00dev, 3, bbp);
 915 +
 916 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 917 +               if (conf_is_ht40(conf)) {
 918 +                       rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
 919 +                       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
 920 +                       rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
 921 +               } else {
 922 +                       rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
 923 +                       rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
 924 +                       rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
 925 +               }
 926 +       }
 927 +
 928 +       msleep(1);
 929 +}
 930 +
 931 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 932 +                                    const int txpower)
 933 +{
 934 +       u32 reg;
 935 +       u32 value = TXPOWER_G_TO_DEV(txpower);
 936 +       u8 r1;
 937 +
 938 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 939 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 940 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 941 +
 942 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 943 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 944 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 945 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 946 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 947 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 948 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 949 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 950 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 951 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 952 +
 953 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 954 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 955 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 956 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 957 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 958 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 959 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 960 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 961 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 962 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 963 +
 964 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 965 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 966 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 967 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 968 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 969 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 970 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 971 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 972 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 973 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 974 +
 975 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 976 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 977 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 978 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 979 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 980 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 981 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 982 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 983 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 984 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 985 +
 986 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 987 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 988 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 989 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 990 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 991 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 992 +}
 993 +
 994 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 995 +                                        struct rt2x00lib_conf *libconf)
 996 +{
 997 +       u32 reg;
 998 +
 999 +       rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1000 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1001 +                          libconf->conf->short_frame_max_tx_count);
1002 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1003 +                          libconf->conf->long_frame_max_tx_count);
1004 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1005 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1006 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1007 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1008 +       rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
1009 +}
1010 +
1011 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
1012 +                                     struct rt2x00lib_conf *libconf)
1013 +{
1014 +       u32 reg;
1015 +
1016 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1017 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1018 +                          libconf->conf->beacon_int * 16);
1019 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1020 +}
1021 +
1022 +static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
1023 +                               struct rt2x00lib_conf *libconf)
1024 +{
1025 +       enum dev_state state =
1026 +           (libconf->conf->flags & IEEE80211_CONF_PS) ?
1027 +               STATE_SLEEP : STATE_AWAKE;
1028 +       u32 reg;
1029 +
1030 +       if (state == STATE_SLEEP) {
1031 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1032 +
1033 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1034 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1035 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1036 +                                  libconf->conf->listen_interval - 1);
1037 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1038 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1039 +
1040 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
1041 +       } else {
1042 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1043 +
1044 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1045 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1046 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1047 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1048 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1049 +       }
1050 +}
1051 +
1052 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1053 +                            struct rt2x00lib_conf *libconf,
1054 +                            const unsigned int flags)
1055 +{
1056 +       /* Always recalculate LNA gain before changing configuration */
1057 +       rt2800usb_config_lna_gain(rt2x00dev, libconf);
1058 +
1059 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1060 +               rt2800usb_config_channel(rt2x00dev, libconf->conf,
1061 +                                        &libconf->rf, &libconf->channel);
1062 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1063 +               rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1064 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1065 +               rt2800usb_config_retry_limit(rt2x00dev, libconf);
1066 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1067 +               rt2800usb_config_duration(rt2x00dev, libconf);
1068 +       if (flags & IEEE80211_CONF_CHANGE_PS)
1069 +               rt2800usb_config_ps(rt2x00dev, libconf);
1070 +}
1071 +
1072 +/*
1073 + * Link tuning
1074 + */
1075 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1076 +                                struct link_qual *qual)
1077 +{
1078 +       u32 reg;
1079 +
1080 +       /*
1081 +        * Update FCS error count from register.
1082 +        */
1083 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1084 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1085 +}
1086 +
1087 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1088 +{
1089 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1090 +               if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1091 +                       return 0x1c + (2 * rt2x00dev->lna_gain);
1092 +               else
1093 +                       return 0x2e + rt2x00dev->lna_gain;
1094 +       }
1095 +
1096 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1097 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1098 +       else
1099 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1100 +}
1101 +
1102 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1103 +                                    struct link_qual *qual, u8 vgc_level)
1104 +{
1105 +       if (qual->vgc_level != vgc_level) {
1106 +               rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1107 +               qual->vgc_level = vgc_level;
1108 +               qual->vgc_level_reg = vgc_level;
1109 +       }
1110 +}
1111 +
1112 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1113 +                                 struct link_qual *qual)
1114 +{
1115 +       rt2800usb_set_vgc(rt2x00dev, qual,
1116 +                         rt2800usb_get_default_vgc(rt2x00dev));
1117 +}
1118 +
1119 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1120 +                                struct link_qual *qual, const u32 count)
1121 +{
1122 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1123 +               return;
1124 +
1125 +       /*
1126 +        * When RSSI is better then -80 increase VGC level with 0x10
1127 +        */
1128 +       rt2800usb_set_vgc(rt2x00dev, qual,
1129 +                         rt2800usb_get_default_vgc(rt2x00dev) +
1130 +                         ((qual->rssi > -80) * 0x10));
1131 +}
1132 +
1133 +/*
1134 + * Firmware functions
1135 + */
1136 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1137 +{
1138 +       return FIRMWARE_RT2870;
1139 +}
1140 +
1141 +static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1142 +{
1143 +       u16 fw_crc;
1144 +       u16 crc;
1145 +
1146 +       /*
1147 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1148 +        * this means that we should never pass those 2 bytes to the crc
1149 +        * algorithm.
1150 +        */
1151 +       fw_crc = (data[len - 2] << 8 | data[len - 1]);
1152 +
1153 +       /*
1154 +        * Use the crc ccitt algorithm.
1155 +        * This will return the same value as the legacy driver which
1156 +        * used bit ordering reversion on the both the firmware bytes
1157 +        * before input input as well as on the final output.
1158 +        * Obviously using crc ccitt directly is much more efficient.
1159 +        */
1160 +       crc = crc_ccitt(~0, data, len - 2);
1161 +
1162 +       /*
1163 +        * There is a small difference between the crc-itu-t + bitrev and
1164 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1165 +        * will be swapped, use swab16 to convert the crc to the correct
1166 +        * value.
1167 +        */
1168 +       crc = swab16(crc);
1169 +
1170 +       return fw_crc == crc;
1171 +}
1172 +
1173 +static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1174 +                                   const u8 *data, const size_t len)
1175 +{
1176 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1177 +       size_t offset = 0;
1178 +
1179 +       /*
1180 +        * Firmware files:
1181 +        * There are 2 variations of the rt2870 firmware.
1182 +        * a) size: 4kb
1183 +        * b) size: 8kb
1184 +        * Note that (b) contains 2 seperate firmware blobs of 4k
1185 +        * within the file. The first blob is the same firmware as (a),
1186 +        * but the second blob is for the additional chipsets.
1187 +        */
1188 +       if (len != 4096 && len != 8192)
1189 +               return FW_BAD_LENGTH;
1190 +
1191 +       /*
1192 +        * Check if we need the upper 4kb firmware data or not.
1193 +        */
1194 +       if ((len == 4096) &&
1195 +           (chipset != 0x2860) &&
1196 +           (chipset != 0x2872) &&
1197 +           (chipset != 0x3070))
1198 +               return FW_BAD_VERSION;
1199 +
1200 +       /*
1201 +        * 8kb firmware files must be checked as if it were
1202 +        * 2 seperate firmware files.
1203 +        */
1204 +       while (offset < len) {
1205 +               if (!rt2800usb_check_crc(data + offset, 4096))
1206 +                       return FW_BAD_CRC;
1207 +
1208 +               offset += 4096;
1209 +       }
1210 +
1211 +       return FW_OK;
1212 +}
1213 +
1214 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1215 +                                  const u8 *data, const size_t len)
1216 +{
1217 +       unsigned int i;
1218 +       int status;
1219 +       u32 reg;
1220 +       u32 offset;
1221 +       u32 length;
1222 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1223 +
1224 +       /*
1225 +        * Check which section of the firmware we need.
1226 +        */
1227 +       if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1228 +               offset = 0;
1229 +               length = 4096;
1230 +       } else {
1231 +               offset = 4096;
1232 +               length = 4096;
1233 +       }
1234 +
1235 +       /*
1236 +        * Wait for stable hardware.
1237 +        */
1238 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1239 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1240 +               if (reg && reg != ~0)
1241 +                       break;
1242 +               msleep(1);
1243 +       }
1244 +
1245 +       if (i == REGISTER_BUSY_COUNT) {
1246 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1247 +               return -EBUSY;
1248 +       }
1249 +
1250 +       /*
1251 +        * Write firmware to device.
1252 +        */
1253 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1254 +                                           USB_VENDOR_REQUEST_OUT,
1255 +                                           FIRMWARE_IMAGE_BASE,
1256 +                                           data + offset, length,
1257 +                                           REGISTER_TIMEOUT32(length));
1258 +
1259 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1260 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1261 +
1262 +       /*
1263 +        * Send firmware request to device to load firmware,
1264 +        * we need to specify a long timeout time.
1265 +        */
1266 +       status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1267 +                                            0, USB_MODE_FIRMWARE,
1268 +                                            REGISTER_TIMEOUT_FIRMWARE);
1269 +       if (status < 0) {
1270 +               ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1271 +               return status;
1272 +       }
1273 +
1274 +       /*
1275 +        * Wait for device to stabilize.
1276 +        */
1277 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1278 +               rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1279 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1280 +                       break;
1281 +               msleep(1);
1282 +       }
1283 +
1284 +       if (i == REGISTER_BUSY_COUNT) {
1285 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1286 +               return -EBUSY;
1287 +       }
1288 +
1289 +       /*
1290 +        * Initialize firmware.
1291 +        */
1292 +       rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1293 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1294 +       msleep(1);
1295 +
1296 +       return 0;
1297 +}
1298 +
1299 +/*
1300 + * Initialization functions.
1301 + */
1302 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1303 +{
1304 +       u32 reg;
1305 +       unsigned int i;
1306 +
1307 +       /*
1308 +        * Wait untill BBP and RF are ready.
1309 +        */
1310 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1311 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1312 +               if (reg && reg != ~0)
1313 +                       break;
1314 +               msleep(1);
1315 +       }
1316 +
1317 +       if (i == REGISTER_BUSY_COUNT) {
1318 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1319 +               return -EBUSY;
1320 +       }
1321 +
1322 +       rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1323 +       rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1324 +
1325 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1326 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1327 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1328 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1329 +
1330 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1331 +
1332 +       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1333 +                                   USB_MODE_RESET, REGISTER_TIMEOUT);
1334 +
1335 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1336 +
1337 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1338 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1339 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1340 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1341 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1342 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1343 +
1344 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1345 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1346 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1347 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1348 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1349 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1350 +
1351 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1352 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1353 +
1354 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1355 +
1356 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1357 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1358 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1359 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1360 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1361 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1362 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1363 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1364 +
1365 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1366 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1367 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1368 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1369 +       } else {
1370 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1371 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1372 +       }
1373 +
1374 +       rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1375 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1376 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1377 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1378 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1379 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1380 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1381 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1382 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1383 +       rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1384 +
1385 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1386 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1387 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1388 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1389 +
1390 +       rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1391 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1392 +       if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1393 +           rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1394 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1395 +       else
1396 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1397 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1398 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1399 +       rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1400 +
1401 +       rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1402 +
1403 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1404 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1405 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1406 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1407 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1408 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1409 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1410 +
1411 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1412 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1413 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1414 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1415 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1416 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1417 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1418 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1419 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1420 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1421 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1422 +
1423 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1424 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1425 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1426 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1427 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1428 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1429 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1430 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1431 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1432 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1433 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1434 +
1435 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1436 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1437 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1438 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1439 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1440 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1441 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1442 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1443 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1444 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1445 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1446 +
1447 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1448 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1449 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1450 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1451 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1452 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1453 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1454 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1455 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1456 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1457 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1458 +
1459 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1460 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1461 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1462 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1463 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1464 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1465 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1466 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1467 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1468 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1469 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1470 +
1471 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1472 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1473 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1474 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1475 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1476 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1477 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1478 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1479 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1480 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1481 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1482 +
1483 +       rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1484 +
1485 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1486 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1487 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1488 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1489 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1490 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1491 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1492 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1493 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1494 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1495 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1496 +
1497 +       rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1498 +       rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1499 +
1500 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1501 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1502 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1503 +                          IEEE80211_MAX_RTS_THRESHOLD);
1504 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1505 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1506 +
1507 +       rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1508 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1509 +
1510 +       /*
1511 +        * ASIC will keep garbage value after boot, clear encryption keys.
1512 +        */
1513 +       for (i = 0; i < 256; i++) {
1514 +               u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1515 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1516 +                                             wcid, sizeof(wcid));
1517 +
1518 +               rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1519 +               rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1520 +       }
1521 +
1522 +       for (i = 0; i < 16; i++)
1523 +               rt2x00usb_register_write(rt2x00dev,
1524 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1525 +
1526 +       /*
1527 +        * Clear all beacons
1528 +        * For the Beacon base registers we only need to clear
1529 +        * the first byte since that byte contains the VALID and OWNER
1530 +        * bits which (when set to 0) will invalidate the entire beacon.
1531 +        */
1532 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1533 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1534 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1535 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1536 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1537 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1538 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1539 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1540 +
1541 +       rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1542 +       rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1543 +       rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1544 +
1545 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1546 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1547 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1548 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1549 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1550 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1551 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1552 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1553 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1554 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1555 +
1556 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1557 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1558 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1559 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1560 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1561 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1562 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1563 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1564 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1565 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1566 +
1567 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1568 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1569 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1570 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1571 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1572 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1573 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1574 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1575 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1576 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1577 +
1578 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1579 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1580 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1581 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1582 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1583 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1584 +
1585 +       /*
1586 +        * We must clear the error counters.
1587 +        * These registers are cleared on read,
1588 +        * so we may pass a useless variable to store the value.
1589 +        */
1590 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1591 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1592 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1593 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1594 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1595 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1596 +
1597 +       return 0;
1598 +}
1599 +
1600 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1601 +{
1602 +       unsigned int i;
1603 +       u32 reg;
1604 +
1605 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1606 +               rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1607 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1608 +                       return 0;
1609 +
1610 +               udelay(REGISTER_BUSY_DELAY);
1611 +       }
1612 +
1613 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1614 +       return -EACCES;
1615 +}
1616 +
1617 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1618 +{
1619 +       unsigned int i;
1620 +       u8 value;
1621 +
1622 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1623 +               rt2800usb_bbp_read(rt2x00dev, 0, &value);
1624 +               if ((value != 0xff) && (value != 0x00))
1625 +                       return 0;
1626 +               udelay(REGISTER_BUSY_DELAY);
1627 +       }
1628 +
1629 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1630 +       return -EACCES;
1631 +}
1632 +
1633 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1634 +{
1635 +       unsigned int i;
1636 +       u16 eeprom;
1637 +       u8 reg_id;
1638 +       u8 value;
1639 +
1640 +       if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1641 +                    rt2800usb_wait_bbp_ready(rt2x00dev)))
1642 +               return -EACCES;
1643 +
1644 +       rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1645 +       rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1646 +       rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1647 +       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1648 +       rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1649 +       rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1650 +       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1651 +       rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1652 +       rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1653 +       rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1654 +       rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1655 +       rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1656 +       rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1657 +       rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1658 +
1659 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1660 +               rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1661 +               rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1662 +       }
1663 +
1664 +       if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1665 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1666 +       }
1667 +
1668 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1669 +               rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1670 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1671 +               rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1672 +       }
1673 +
1674 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1675 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1676 +
1677 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1678 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1679 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1680 +                       rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1681 +               }
1682 +       }
1683 +
1684 +       return 0;
1685 +}
1686 +
1687 +static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1688 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
1689 +{
1690 +       unsigned int i;
1691 +       u8 bbp;
1692 +       u8 rfcsr;
1693 +       u8 passband;
1694 +       u8 stopband;
1695 +       u8 overtuned = 0;
1696 +
1697 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1698 +
1699 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1700 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1701 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1702 +
1703 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1704 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1705 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1706 +
1707 +       /*
1708 +        * Set power & frequency of passband test tone
1709 +        */
1710 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1711 +
1712 +       for (i = 0; i < 100; i++) {
1713 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1714 +               msleep(1);
1715 +
1716 +               rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1717 +               if (passband)
1718 +                       break;
1719 +       }
1720 +
1721 +       /*
1722 +        * Set power & frequency of stopband test tone
1723 +        */
1724 +       rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1725 +
1726 +       for (i = 0; i < 100; i++) {
1727 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1728 +               msleep(1);
1729 +
1730 +               rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1731 +
1732 +               if ((passband - stopband) <= filter_target) {
1733 +                       rfcsr24++;
1734 +                       overtuned += ((passband - stopband) == filter_target);
1735 +               } else
1736 +                       break;
1737 +
1738 +               rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1739 +       }
1740 +
1741 +       rfcsr24 -= !!overtuned;
1742 +
1743 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1744 +       return rfcsr24;
1745 +}
1746 +
1747 +static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1748 +{
1749 +       u8 rfcsr;
1750 +       u8 bbp;
1751 +
1752 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1753 +               return 0;
1754 +
1755 +       /*
1756 +        * Init RF calibration.
1757 +        */
1758 +       rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1759 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1760 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1761 +       msleep(1);
1762 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1763 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1764 +
1765 +       rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1766 +       rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1767 +       rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1768 +       rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1769 +       rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1770 +       rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1771 +       rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1772 +       rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1773 +       rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1774 +       rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1775 +       rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1776 +       rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1777 +       rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1778 +       rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1779 +       rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1780 +       rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1781 +       rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1782 +       rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1783 +       rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1784 +       rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1785 +
1786 +       /*
1787 +        * Set RX Filter calibration for 20MHz and 40MHz
1788 +        */
1789 +       rt2x00dev->calibration_bw20 =
1790 +           rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1791 +       rt2x00dev->calibration_bw40 =
1792 +           rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1793 +
1794 +       /*
1795 +        * Set back to initial state
1796 +        */
1797 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1798 +
1799 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1800 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1801 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1802 +
1803 +       /*
1804 +        * set BBP back to BW20
1805 +        */
1806 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1807 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1808 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1809 +
1810 +       return 0;
1811 +}
1812 +
1813 +/*
1814 + * Device state switch handlers.
1815 + */
1816 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1817 +                               enum dev_state state)
1818 +{
1819 +       u32 reg;
1820 +
1821 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1822 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1823 +                          (state == STATE_RADIO_RX_ON) ||
1824 +                          (state == STATE_RADIO_RX_ON_LINK));
1825 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1826 +}
1827 +
1828 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1829 +{
1830 +       unsigned int i;
1831 +       u32 reg;
1832 +
1833 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1834 +               rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1835 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1836 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1837 +                       return 0;
1838 +
1839 +               msleep(1);
1840 +       }
1841 +
1842 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1843 +       return -EACCES;
1844 +}
1845 +
1846 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1847 +{
1848 +       u32 reg;
1849 +       u16 word;
1850 +
1851 +       /*
1852 +        * Initialize all registers.
1853 +        */
1854 +       if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1855 +                    rt2800usb_init_registers(rt2x00dev) ||
1856 +                    rt2800usb_init_bbp(rt2x00dev) ||
1857 +                    rt2800usb_init_rfcsr(rt2x00dev)))
1858 +               return -EIO;
1859 +
1860 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1861 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1862 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1863 +
1864 +       udelay(50);
1865 +
1866 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1867 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1868 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1869 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1870 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1871 +
1872 +
1873 +       rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1874 +       rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1875 +       /* Don't use bulk in aggregation when working with USB 1.1 */
1876 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1877 +                          (rt2x00dev->rx->usb_maxpacket == 512));
1878 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1879 +       /* FIXME: Calculate this value based on Aggregation defines */
1880 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1881 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1882 +       rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1883 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1884 +
1885 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1886 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1887 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1888 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1889 +
1890 +       /*
1891 +        * Send signal to firmware during boot time.
1892 +        */
1893 +       rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1894 +
1895 +       /*
1896 +        * Initialize LED control
1897 +        */
1898 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1899 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1900 +                             word & 0xff, (word >> 8) & 0xff);
1901 +
1902 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1903 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1904 +                             word & 0xff, (word >> 8) & 0xff);
1905 +
1906 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1907 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1908 +                             word & 0xff, (word >> 8) & 0xff);
1909 +
1910 +       return 0;
1911 +}
1912 +
1913 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1914 +{
1915 +       u32 reg;
1916 +
1917 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1918 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1919 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1920 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1921 +
1922 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1923 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1924 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1925 +
1926 +       /* Wait for DMA, ignore error */
1927 +       rt2800usb_wait_wpdma_ready(rt2x00dev);
1928 +
1929 +       rt2x00usb_disable_radio(rt2x00dev);
1930 +}
1931 +
1932 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1933 +                              enum dev_state state)
1934 +{
1935 +       rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1936 +
1937 +       if (state == STATE_AWAKE)
1938 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1939 +       else
1940 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1941 +
1942 +       return 0;
1943 +}
1944 +
1945 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1946 +                                     enum dev_state state)
1947 +{
1948 +       int retval = 0;
1949 +
1950 +       switch (state) {
1951 +       case STATE_RADIO_ON:
1952 +               /*
1953 +                * Before the radio can be enabled, the device first has
1954 +                * to be woken up. After that it needs a bit of time
1955 +                * to be fully awake and the radio can be enabled.
1956 +                */
1957 +               rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1958 +               msleep(1);
1959 +               retval = rt2800usb_enable_radio(rt2x00dev);
1960 +               break;
1961 +       case STATE_RADIO_OFF:
1962 +               /*
1963 +                * After the radio has been disablee, the device should
1964 +                * be put to sleep for powersaving.
1965 +                */
1966 +               rt2800usb_disable_radio(rt2x00dev);
1967 +               rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1968 +               break;
1969 +       case STATE_RADIO_RX_ON:
1970 +       case STATE_RADIO_RX_ON_LINK:
1971 +       case STATE_RADIO_RX_OFF:
1972 +       case STATE_RADIO_RX_OFF_LINK:
1973 +               rt2800usb_toggle_rx(rt2x00dev, state);
1974 +               break;
1975 +       case STATE_RADIO_IRQ_ON:
1976 +       case STATE_RADIO_IRQ_OFF:
1977 +               /* No support, but no error either */
1978 +               break;
1979 +       case STATE_DEEP_SLEEP:
1980 +       case STATE_SLEEP:
1981 +       case STATE_STANDBY:
1982 +       case STATE_AWAKE:
1983 +               retval = rt2800usb_set_state(rt2x00dev, state);
1984 +               break;
1985 +       default:
1986 +               retval = -ENOTSUPP;
1987 +               break;
1988 +       }
1989 +
1990 +       if (unlikely(retval))
1991 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1992 +                     state, retval);
1993 +
1994 +       return retval;
1995 +}
1996 +
1997 +/*
1998 + * TX descriptor initialization
1999 + */
2000 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2001 +                                   struct sk_buff *skb,
2002 +                                   struct txentry_desc *txdesc)
2003 +{
2004 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2005 +       __le32 *txi = skbdesc->desc;
2006 +       __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
2007 +       u32 word;
2008 +
2009 +       /*
2010 +        * Initialize TX Info descriptor
2011 +        */
2012 +       rt2x00_desc_read(txwi, 0, &word);
2013 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
2014 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2015 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2016 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2017 +       rt2x00_set_field32(&word, TXWI_W0_TS,
2018 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2019 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2020 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2021 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2022 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2023 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2024 +       rt2x00_set_field32(&word, TXWI_W0_BW,
2025 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2026 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2027 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2028 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2029 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2030 +       rt2x00_desc_write(txwi, 0, word);
2031 +
2032 +       rt2x00_desc_read(txwi, 1, &word);
2033 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2034 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2035 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2036 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2037 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2038 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2039 +                          test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2040 +                              txdesc->key_idx : 0xff);
2041 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2042 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2043 +                          skbdesc->entry->entry_idx);
2044 +       rt2x00_desc_write(txwi, 1, word);
2045 +
2046 +       /*
2047 +        * Always write 0 to IV/EIV fields, hardware will insert the IV
2048 +        * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2049 +        * When TXINFO_W0_WIV is set to 1 it will use the IV data
2050 +        * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2051 +        * crypto entry in the registers should be used to encrypt the frame.
2052 +        */
2053 +       _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2054 +       _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2055 +
2056 +       /*
2057 +        * Initialize TX descriptor
2058 +        */
2059 +       rt2x00_desc_read(txi, 0, &word);
2060 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2061 +                          skb->len + TXWI_DESC_SIZE);
2062 +       rt2x00_set_field32(&word, TXINFO_W0_WIV,
2063 +                          !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2064 +       rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2065 +       rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2066 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2067 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2068 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2069 +       rt2x00_desc_write(txi, 0, word);
2070 +}
2071 +
2072 +/*
2073 + * TX data initialization
2074 + */
2075 +static void rt2800usb_write_beacon(struct queue_entry *entry)
2076 +{
2077 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2078 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2079 +       unsigned int beacon_base;
2080 +       u32 reg;
2081 +
2082 +       /*
2083 +        * Add the descriptor in front of the skb.
2084 +        */
2085 +       skb_push(entry->skb, entry->queue->desc_size);
2086 +       memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2087 +       skbdesc->desc = entry->skb->data;
2088 +
2089 +       /*
2090 +        * Disable beaconing while we are reloading the beacon data,
2091 +        * otherwise we might be sending out invalid data.
2092 +        */
2093 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2094 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2095 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2096 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2097 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2098 +
2099 +       /*
2100 +        * Write entire beacon with descriptor to register.
2101 +        */
2102 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2103 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2104 +                                           USB_VENDOR_REQUEST_OUT, beacon_base,
2105 +                                           entry->skb->data, entry->skb->len,
2106 +                                           REGISTER_TIMEOUT32(entry->skb->len));
2107 +
2108 +       /*
2109 +        * Clean up the beacon skb.
2110 +        */
2111 +       dev_kfree_skb(entry->skb);
2112 +       entry->skb = NULL;
2113 +}
2114 +
2115 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2116 +{
2117 +       int length;
2118 +
2119 +       /*
2120 +        * The length _must_ include 4 bytes padding,
2121 +        * it should always be multiple of 4,
2122 +        * but it must _not_ be a multiple of the USB packet size.
2123 +        */
2124 +       length = roundup(entry->skb->len + 4, 4);
2125 +       length += (4 * !(length % entry->queue->usb_maxpacket));
2126 +
2127 +       return length;
2128 +}
2129 +
2130 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2131 +                                   const enum data_queue_qid queue)
2132 +{
2133 +       u32 reg;
2134 +
2135 +       if (queue != QID_BEACON) {
2136 +               rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2137 +               return;
2138 +       }
2139 +
2140 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2141 +       if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2142 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2143 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2144 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2145 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2146 +       }
2147 +}
2148 +
2149 +/*
2150 + * RX control handlers
2151 + */
2152 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2153 +                                 struct rxdone_entry_desc *rxdesc)
2154 +{
2155 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2156 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2157 +       __le32 *rxd = (__le32 *)entry->skb->data;
2158 +       __le32 *rxwi;
2159 +       u32 rxd0;
2160 +       u32 rxwi0;
2161 +       u32 rxwi1;
2162 +       u32 rxwi2;
2163 +       u32 rxwi3;
2164 +
2165 +       /*
2166 +        * Copy descriptor to the skbdesc->desc buffer, making it safe from
2167 +        * moving of frame data in rt2x00usb.
2168 +        */
2169 +       memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2170 +       rxd = (__le32 *)skbdesc->desc;
2171 +       rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2172 +
2173 +       /*
2174 +        * It is now safe to read the descriptor on all architectures.
2175 +        */
2176 +       rt2x00_desc_read(rxd, 0, &rxd0);
2177 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2178 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2179 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2180 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2181 +
2182 +       if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2183 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2184 +
2185 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2186 +               /*
2187 +                * Unfortunately we don't know the cipher type used during
2188 +                * decryption. This prevents us from correct providing
2189 +                * correct statistics through debugfs.
2190 +                */
2191 +               rxdesc->cipher = CIPHER_NONE;
2192 +               rxdesc->cipher_status =
2193 +                   rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2194 +       }
2195 +
2196 +       if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2197 +               /*
2198 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2199 +                * decryption. Unfortunately the descriptor doesn't contain
2200 +                * any fields with the EIV/IV data either, so they can't
2201 +                * be restored by rt2x00lib.
2202 +                */
2203 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2204 +
2205 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2206 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2207 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2208 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2209 +       }
2210 +
2211 +       if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2212 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2213 +
2214 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2215 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
2216 +
2217 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2218 +               rxdesc->flags |= RX_FLAG_40MHZ;
2219 +
2220 +       /*
2221 +        * Detect RX rate, always use MCS as signal type.
2222 +        */
2223 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2224 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2225 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2226 +
2227 +       /*
2228 +        * Mask of 0x8 bit to remove the short preamble flag.
2229 +        */
2230 +       if (rxdesc->dev_flags == RATE_MODE_CCK)
2231 +               rxdesc->signal &= ~0x8;
2232 +
2233 +       rxdesc->rssi =
2234 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2235 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2236 +
2237 +       rxdesc->noise =
2238 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2239 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2240 +
2241 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2242 +
2243 +       /*
2244 +        * Remove RXWI descriptor from start of buffer.
2245 +        */
2246 +       skb_pull(entry->skb, skbdesc->desc_len);
2247 +       skb_trim(entry->skb, rxdesc->size);
2248 +}
2249 +
2250 +/*
2251 + * Device probe functions.
2252 + */
2253 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2254 +{
2255 +       u16 word;
2256 +       u8 *mac;
2257 +       u8 default_lna_gain;
2258 +
2259 +       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2260 +
2261 +       /*
2262 +        * Start validation of the data that has been read.
2263 +        */
2264 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2265 +       if (!is_valid_ether_addr(mac)) {
2266 +               DECLARE_MAC_BUF(macbuf);
2267 +
2268 +               random_ether_addr(mac);
2269 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2270 +       }
2271 +
2272 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2273 +       if (word == 0xffff) {
2274 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2275 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2276 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2277 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2278 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2279 +       } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2280 +               /*
2281 +                * There is a max of 2 RX streams for RT2860 series
2282 +                */
2283 +               if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2284 +                       rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2285 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2286 +       }
2287 +
2288 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2289 +       if (word == 0xffff) {
2290 +               rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2291 +               rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2292 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2293 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2294 +               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2295 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2296 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2297 +               rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2298 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2299 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2300 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2301 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2302 +       }
2303 +
2304 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2305 +       if ((word & 0x00ff) == 0x00ff) {
2306 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2307 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2308 +                                  LED_MODE_TXRX_ACTIVITY);
2309 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2310 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2311 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2312 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2313 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2314 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2315 +       }
2316 +
2317 +       /*
2318 +        * During the LNA validation we are going to use
2319 +        * lna0 as correct value. Note that EEPROM_LNA
2320 +        * is never validated.
2321 +        */
2322 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2323 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2324 +
2325 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2326 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2327 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2328 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2329 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2330 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2331 +
2332 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2333 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2334 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2335 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2336 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2337 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2338 +                                  default_lna_gain);
2339 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2340 +
2341 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2342 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2343 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2344 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2345 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2346 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2347 +
2348 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2349 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2350 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2351 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2352 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2353 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2354 +                                  default_lna_gain);
2355 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2356 +
2357 +       return 0;
2358 +}
2359 +
2360 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2361 +{
2362 +       u32 reg;
2363 +       u16 value;
2364 +       u16 eeprom;
2365 +
2366 +       /*
2367 +        * Read EEPROM word for configuration.
2368 +        */
2369 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2370 +
2371 +       /*
2372 +        * Identify RF chipset.
2373 +        */
2374 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2375 +       rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2376 +       rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2377 +
2378 +       /*
2379 +        * The check for rt2860 is not a typo, some rt2870 hardware
2380 +        * identifies itself as rt2860 in the CSR register.
2381 +        */
2382 +       if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2383 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
2384 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
2385 +               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2386 +               return -ENODEV;
2387 +       }
2388 +
2389 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2390 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2391 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2392 +           !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2393 +           !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2394 +           !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2395 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2396 +               return -ENODEV;
2397 +       }
2398 +
2399 +       /*
2400 +        * Read frequency offset and RF programming sequence.
2401 +        */
2402 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2403 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2404 +
2405 +       /*
2406 +        * Read external LNA informations.
2407 +        */
2408 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2409 +
2410 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2411 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2412 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2413 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2414 +
2415 +       /*
2416 +        * Detect if this device has an hardware controlled radio.
2417 +        */
2418 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2419 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2420 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2421 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2422 +
2423 +       /*
2424 +        * Store led settings, for correct led behaviour.
2425 +        */
2426 +#ifdef CONFIG_RT2X00_LIB_LEDS
2427 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2428 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2429 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2430 +
2431 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2432 +                          &rt2x00dev->led_mcu_reg);
2433 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2434 +
2435 +       return 0;
2436 +}
2437 +
2438 +/*
2439 + * RF value list for rt2870
2440 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2441 + */
2442 +static const struct rf_channel rf_vals[] = {
2443 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2444 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2445 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2446 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2447 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2448 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2449 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2450 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2451 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2452 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2453 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2454 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2455 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2456 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2457 +
2458 +       /* 802.11 UNI / HyperLan 2 */
2459 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2460 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2461 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2462 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2463 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2464 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2465 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2466 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2467 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2468 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2469 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2470 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2471 +
2472 +       /* 802.11 HyperLan 2 */
2473 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2474 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2475 +       { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2476 +       { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2477 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2478 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2479 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2480 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2481 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2482 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2483 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2484 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2485 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2486 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2487 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2488 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2489 +
2490 +       /* 802.11 UNII */
2491 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2492 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2493 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2494 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2495 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2496 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2497 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2498 +
2499 +       /* 802.11 Japan */
2500 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2501 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2502 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2503 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2504 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2505 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2506 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2507 +};
2508 +
2509 +/*
2510 + * RF value list for rt3070
2511 + * Supports: 2.4 GHz
2512 + */
2513 +static const struct rf_channel rf_vals_3070[] = {
2514 +       {1,  241, 2, 2 },
2515 +       {2,  241, 2, 7 },
2516 +       {3,  242, 2, 2 },
2517 +       {4,  242, 2, 7 },
2518 +       {5,  243, 2, 2 },
2519 +       {6,  243, 2, 7 },
2520 +       {7,  244, 2, 2 },
2521 +       {8,  244, 2, 7 },
2522 +       {9,  245, 2, 2 },
2523 +       {10, 245, 2, 7 },
2524 +       {11, 246, 2, 2 },
2525 +       {12, 246, 2, 7 },
2526 +       {13, 247, 2, 2 },
2527 +       {14, 248, 2, 4 },
2528 +};
2529 +
2530 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2531 +{
2532 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2533 +       struct channel_info *info;
2534 +       char *tx_power1;
2535 +       char *tx_power2;
2536 +       unsigned int i;
2537 +       u16 eeprom;
2538 +
2539 +       /*
2540 +        * Initialize all hw fields.
2541 +        */
2542 +       rt2x00dev->hw->flags =
2543 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2544 +           IEEE80211_HW_SIGNAL_DBM |
2545 +           IEEE80211_HW_SUPPORTS_PS |
2546 +           IEEE80211_HW_PS_NULLFUNC_STACK;
2547 +       rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2548 +
2549 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2550 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2551 +                               rt2x00_eeprom_addr(rt2x00dev,
2552 +                                                  EEPROM_MAC_ADDR_0));
2553 +
2554 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2555 +
2556 +       /*
2557 +        * Initialize HT information.
2558 +        */
2559 +       spec->ht.ht_supported = true;
2560 +       spec->ht.cap =
2561 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2562 +           IEEE80211_HT_CAP_GRN_FLD |
2563 +           IEEE80211_HT_CAP_SGI_20 |
2564 +           IEEE80211_HT_CAP_SGI_40 |
2565 +           IEEE80211_HT_CAP_TX_STBC |
2566 +           IEEE80211_HT_CAP_RX_STBC |
2567 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2568 +       spec->ht.ampdu_factor = 3;
2569 +       spec->ht.ampdu_density = 4;
2570 +       spec->ht.mcs.tx_params =
2571 +           IEEE80211_HT_MCS_TX_DEFINED |
2572 +           IEEE80211_HT_MCS_TX_RX_DIFF |
2573 +           ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2574 +               IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2575 +
2576 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2577 +       case 3:
2578 +               spec->ht.mcs.rx_mask[2] = 0xff;
2579 +       case 2:
2580 +               spec->ht.mcs.rx_mask[1] = 0xff;
2581 +       case 1:
2582 +               spec->ht.mcs.rx_mask[0] = 0xff;
2583 +               spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2584 +               break;
2585 +       }
2586 +
2587 +       /*
2588 +        * Initialize hw_mode information.
2589 +        */
2590 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2591 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2592 +
2593 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2594 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2595 +               spec->num_channels = 14;
2596 +               spec->channels = rf_vals;
2597 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2598 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2599 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2600 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2601 +               spec->channels = rf_vals;
2602 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2603 +                  rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2604 +               spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2605 +               spec->channels = rf_vals_3070;
2606 +       }
2607 +
2608 +       /*
2609 +        * Create channel information array
2610 +        */
2611 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2612 +       if (!info)
2613 +               return -ENOMEM;
2614 +
2615 +       spec->channels_info = info;
2616 +
2617 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2618 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2619 +
2620 +       for (i = 0; i < 14; i++) {
2621 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2622 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2623 +       }
2624 +
2625 +       if (spec->num_channels > 14) {
2626 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2627 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2628 +
2629 +               for (i = 14; i < spec->num_channels; i++) {
2630 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2631 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2632 +               }
2633 +       }
2634 +
2635 +       return 0;
2636 +}
2637 +
2638 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2639 +{
2640 +       int retval;
2641 +
2642 +       /*
2643 +        * Allocate eeprom data.
2644 +        */
2645 +       retval = rt2800usb_validate_eeprom(rt2x00dev);
2646 +       if (retval)
2647 +               return retval;
2648 +
2649 +       retval = rt2800usb_init_eeprom(rt2x00dev);
2650 +       if (retval)
2651 +               return retval;
2652 +
2653 +       /*
2654 +        * Initialize hw specifications.
2655 +        */
2656 +       retval = rt2800usb_probe_hw_mode(rt2x00dev);
2657 +       if (retval)
2658 +               return retval;
2659 +
2660 +       /*
2661 +        * This device requires firmware.
2662 +        */
2663 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2664 +       __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2665 +       if (!modparam_nohwcrypt)
2666 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2667 +
2668 +       /*
2669 +        * Set the rssi offset.
2670 +        */
2671 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2672 +
2673 +       return 0;
2674 +}
2675 +
2676 +/*
2677 + * IEEE80211 stack callback functions.
2678 + */
2679 +static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2680 +                                  u32 *iv32, u16 *iv16)
2681 +{
2682 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2683 +       struct mac_iveiv_entry iveiv_entry;
2684 +       u32 offset;
2685 +
2686 +       offset = MAC_IVEIV_ENTRY(hw_key_idx);
2687 +       rt2x00usb_register_multiread(rt2x00dev, offset,
2688 +                                     &iveiv_entry, sizeof(iveiv_entry));
2689 +
2690 +       memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2691 +       memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2692 +}
2693 +
2694 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2695 +{
2696 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2697 +       u32 reg;
2698 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2699 +
2700 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2701 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2702 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2703 +
2704 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2705 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2706 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2707 +
2708 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2709 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2710 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2711 +
2712 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2713 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2714 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2715 +
2716 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2717 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2718 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2719 +
2720 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2721 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2722 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2723 +
2724 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2725 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2726 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2727 +
2728 +       return 0;
2729 +}
2730 +
2731 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2732 +                            const struct ieee80211_tx_queue_params *params)
2733 +{
2734 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2735 +       struct data_queue *queue;
2736 +       struct rt2x00_field32 field;
2737 +       int retval;
2738 +       u32 reg;
2739 +       u32 offset;
2740 +
2741 +       /*
2742 +        * First pass the configuration through rt2x00lib, that will
2743 +        * update the queue settings and validate the input. After that
2744 +        * we are free to update the registers based on the value
2745 +        * in the queue parameter.
2746 +        */
2747 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2748 +       if (retval)
2749 +               return retval;
2750 +
2751 +       /*
2752 +        * We only need to perform additional register initialization
2753 +        * for WMM queues/
2754 +        */
2755 +       if (queue_idx >= 4)
2756 +               return 0;
2757 +
2758 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2759 +
2760 +       /* Update WMM TXOP register */
2761 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2762 +       field.bit_offset = (queue_idx & 1) * 16;
2763 +       field.bit_mask = 0xffff << field.bit_offset;
2764 +
2765 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2766 +       rt2x00_set_field32(&reg, field, queue->txop);
2767 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2768 +
2769 +       /* Update WMM registers */
2770 +       field.bit_offset = queue_idx * 4;
2771 +       field.bit_mask = 0xf << field.bit_offset;
2772 +
2773 +       rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2774 +       rt2x00_set_field32(&reg, field, queue->aifs);
2775 +       rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2776 +
2777 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2778 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2779 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2780 +
2781 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2782 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2783 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2784 +
2785 +       /* Update EDCA registers */
2786 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2787 +
2788 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2789 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2790 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2791 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2792 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2793 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2794 +
2795 +       return 0;
2796 +}
2797 +
2798 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2799 +{
2800 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2801 +       u64 tsf;
2802 +       u32 reg;
2803 +
2804 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2805 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2806 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2807 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2808 +
2809 +       return tsf;
2810 +}
2811 +
2812 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2813 +       .tx                     = rt2x00mac_tx,
2814 +       .start                  = rt2x00mac_start,
2815 +       .stop                   = rt2x00mac_stop,
2816 +       .add_interface          = rt2x00mac_add_interface,
2817 +       .remove_interface       = rt2x00mac_remove_interface,
2818 +       .config                 = rt2x00mac_config,
2819 +       .config_interface       = rt2x00mac_config_interface,
2820 +       .configure_filter       = rt2x00mac_configure_filter,
2821 +       .set_key                = rt2x00mac_set_key,
2822 +       .get_stats              = rt2x00mac_get_stats,
2823 +       .get_tkip_seq           = rt2800usb_get_tkip_seq,
2824 +       .set_rts_threshold      = rt2800usb_set_rts_threshold,
2825 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2826 +       .conf_tx                = rt2800usb_conf_tx,
2827 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2828 +       .get_tsf                = rt2800usb_get_tsf,
2829 +};
2830 +
2831 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2832 +       .probe_hw               = rt2800usb_probe_hw,
2833 +       .get_firmware_name      = rt2800usb_get_firmware_name,
2834 +       .check_firmware         = rt2800usb_check_firmware,
2835 +       .load_firmware          = rt2800usb_load_firmware,
2836 +       .initialize             = rt2x00usb_initialize,
2837 +       .uninitialize           = rt2x00usb_uninitialize,
2838 +       .clear_entry            = rt2x00usb_clear_entry,
2839 +       .set_device_state       = rt2800usb_set_device_state,
2840 +       .rfkill_poll            = rt2800usb_rfkill_poll,
2841 +       .link_stats             = rt2800usb_link_stats,
2842 +       .reset_tuner            = rt2800usb_reset_tuner,
2843 +       .link_tuner             = rt2800usb_link_tuner,
2844 +       .write_tx_desc          = rt2800usb_write_tx_desc,
2845 +       .write_tx_data          = rt2x00usb_write_tx_data,
2846 +       .write_beacon           = rt2800usb_write_beacon,
2847 +       .get_tx_data_len        = rt2800usb_get_tx_data_len,
2848 +       .kick_tx_queue          = rt2800usb_kick_tx_queue,
2849 +       .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2850 +       .fill_rxdone            = rt2800usb_fill_rxdone,
2851 +       .config_shared_key      = rt2800usb_config_shared_key,
2852 +       .config_pairwise_key    = rt2800usb_config_pairwise_key,
2853 +       .config_filter          = rt2800usb_config_filter,
2854 +       .config_intf            = rt2800usb_config_intf,
2855 +       .config_erp             = rt2800usb_config_erp,
2856 +       .config_ant             = rt2800usb_config_ant,
2857 +       .config                 = rt2800usb_config,
2858 +};
2859 +
2860 +static const struct data_queue_desc rt2800usb_queue_rx = {
2861 +       .entry_num              = RX_ENTRIES,
2862 +       .data_size              = AGGREGATION_SIZE,
2863 +       .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2864 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2865 +};
2866 +
2867 +static const struct data_queue_desc rt2800usb_queue_tx = {
2868 +       .entry_num              = TX_ENTRIES,
2869 +       .data_size              = AGGREGATION_SIZE,
2870 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2871 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2872 +};
2873 +
2874 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2875 +       .entry_num              = 8 * BEACON_ENTRIES,
2876 +       .data_size              = MGMT_FRAME_SIZE,
2877 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2878 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2879 +};
2880 +
2881 +static const struct rt2x00_ops rt2800usb_ops = {
2882 +       .name           = KBUILD_MODNAME,
2883 +       .max_sta_intf   = 1,
2884 +       .max_ap_intf    = 8,
2885 +       .eeprom_size    = EEPROM_SIZE,
2886 +       .rf_size        = RF_SIZE,
2887 +       .tx_queues      = NUM_TX_QUEUES,
2888 +       .rx             = &rt2800usb_queue_rx,
2889 +       .tx             = &rt2800usb_queue_tx,
2890 +       .bcn            = &rt2800usb_queue_bcn,
2891 +       .lib            = &rt2800usb_rt2x00_ops,
2892 +       .hw             = &rt2800usb_mac80211_ops,
2893 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2894 +       .debugfs        = &rt2800usb_rt2x00debug,
2895 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2896 +};
2897 +
2898 +/*
2899 + * rt2800usb module information.
2900 + */
2901 +static struct usb_device_id rt2800usb_device_table[] = {
2902 +       /* Abocom */
2903 +       { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 +       { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 +       { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2906 +       { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 +       { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 +       { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 +       /* AirTies */
2910 +       { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 +       /* Amigo */
2912 +       { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 +       { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 +       /* Amit */
2915 +       { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 +       /* ASUS */
2917 +       { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2918 +       { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 +       { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2920 +       { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 +       { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 +       /* AzureWave */
2923 +       { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 +       { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 +       { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 +       /* Belkin */
2927 +       { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 +       { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 +       { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2930 +       /* Buffalo */
2931 +       { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 +       /* Conceptronic */
2933 +       { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 +       { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2935 +       { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2936 +       { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 +       { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 +       { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 +       { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2940 +       { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 +       /* Corega */
2942 +       { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 +       { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 +       { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 +       { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2946 +       { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 +       /* D-Link */
2948 +       { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 +       { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2950 +       { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2951 +       { USB_DEVICE(0x2001, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 +       { USB_DEVICE(0x2001, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2953 +       /* Edimax */
2954 +       { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2955 +       { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 +       { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 +       /* EnGenius */
2958 +       { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2959 +       { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2960 +       { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2961 +       /* Gemtek */
2962 +       { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 +       /* Gigabyte */
2964 +       { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2965 +       { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 +       { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2967 +       /* Hawking */
2968 +       { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 +       { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 +       { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2971 +       { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 +       /* LevelOne */
2973 +       { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 +       { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 +       /* Linksys */
2976 +       { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2977 +       /* Logitec */
2978 +       { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2979 +       { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 +       { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2981 +       /* Pegatron */
2982 +       { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2983 +       /* Philips */
2984 +       { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2985 +       /* Planex */
2986 +       { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2987 +       { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 +       { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2989 +       /* Qcom */
2990 +       { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2991 +       /* Quanta */
2992 +       { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2993 +       /* Ralink */
2994 +       { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 +       { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 +       { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 +       { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 +       { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 +       { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 +       /* Samsung */
3001 +       { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3002 +       /* Siemens */
3003 +       { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3004 +       /* Sitecom */
3005 +       { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3006 +       { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3007 +       { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 +       { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 +       { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 +       { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 +       { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 +       { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 +       { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 +       { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 +       /* SMC */
3016 +       { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 +       { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3018 +       { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3019 +       { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 +       { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 +       { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 +       { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 +       /* Sparklan */
3024 +       { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 +       /* U-Media*/
3026 +       { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3027 +       /* ZCOM */
3028 +       { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3029 +       { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3030 +       /* Zinwell */
3031 +       { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3032 +       { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 +       /* Zyxel */
3034 +       { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3035 +       { 0, }
3036 +};
3037 +
3038 +MODULE_AUTHOR(DRV_PROJECT);
3039 +MODULE_VERSION(DRV_VERSION);
3040 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3041 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3042 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3043 +MODULE_FIRMWARE(FIRMWARE_RT2870);
3044 +MODULE_LICENSE("GPL");
3045 +
3046 +static struct usb_driver rt2800usb_driver = {
3047 +       .name           = KBUILD_MODNAME,
3048 +       .id_table       = rt2800usb_device_table,
3049 +       .probe          = rt2x00usb_probe,
3050 +       .disconnect     = rt2x00usb_disconnect,
3051 +       .suspend        = rt2x00usb_suspend,
3052 +       .resume         = rt2x00usb_resume,
3053 +};
3054 +
3055 +static int __init rt2800usb_init(void)
3056 +{
3057 +       return usb_register(&rt2800usb_driver);
3058 +}
3059 +
3060 +static void __exit rt2800usb_exit(void)
3061 +{
3062 +       usb_deregister(&rt2800usb_driver);
3063 +}
3064 +
3065 +module_init(rt2800usb_init);
3066 +module_exit(rt2800usb_exit);
3067 --- /dev/null
3068 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
3069 @@ -0,0 +1,1932 @@
3070 +/*
3071 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3072 +       <http://rt2x00.serialmonkey.com>
3073 +
3074 +       This program is free software; you can redistribute it and/or modify
3075 +       it under the terms of the GNU General Public License as published by
3076 +       the Free Software Foundation; either version 2 of the License, or
3077 +       (at your option) any later version.
3078 +
3079 +       This program is distributed in the hope that it will be useful,
3080 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
3081 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3082 +       GNU General Public License for more details.
3083 +
3084 +       You should have received a copy of the GNU General Public License
3085 +       along with this program; if not, write to the
3086 +       Free Software Foundation, Inc.,
3087 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3088 + */
3089 +
3090 +/*
3091 +       Module: rt2800usb
3092 +       Abstract: Data structures and registers for the rt2800usb module.
3093 +       Supported chipsets: RT2800U.
3094 + */
3095 +
3096 +#ifndef RT2800USB_H
3097 +#define RT2800USB_H
3098 +
3099 +/*
3100 + * RF chip defines.
3101 + *
3102 + * RF2820 2.4G 2T3R
3103 + * RF2850 2.4G/5G 2T3R
3104 + * RF2720 2.4G 1T2R
3105 + * RF2750 2.4G/5G 1T2R
3106 + * RF3020 2.4G 1T1R
3107 + * RF2020 2.4G B/G
3108 + */
3109 +#define RF2820                         0x0001
3110 +#define RF2850                         0x0002
3111 +#define RF2720                         0x0003
3112 +#define RF2750                         0x0004
3113 +#define RF3020                         0x0005
3114 +#define RF2020                         0x0006
3115 +
3116 +/*
3117 + * RT2870 version
3118 + */
3119 +#define RT2860C_VERSION                        0x28600100
3120 +#define RT2860D_VERSION                        0x28600101
3121 +#define RT2880E_VERSION                        0x28720200
3122 +#define RT2883_VERSION                 0x28830300
3123 +#define RT3070_VERSION                 0x30700200
3124 +
3125 +/*
3126 + * Signal information.
3127 + * Defaul offset is required for RSSI <-> dBm conversion.
3128 + */
3129 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
3130 +
3131 +/*
3132 + * Register layout information.
3133 + */
3134 +#define CSR_REG_BASE                   0x1000
3135 +#define CSR_REG_SIZE                   0x0800
3136 +#define EEPROM_BASE                    0x0000
3137 +#define EEPROM_SIZE                    0x0110
3138 +#define BBP_BASE                       0x0000
3139 +#define BBP_SIZE                       0x0080
3140 +#define RF_BASE                                0x0004
3141 +#define RF_SIZE                                0x0010
3142 +
3143 +/*
3144 + * Number of TX queues.
3145 + */
3146 +#define NUM_TX_QUEUES                  4
3147 +
3148 +/*
3149 + * USB registers.
3150 + */
3151 +
3152 +/*
3153 + * HOST-MCU shared memory
3154 + */
3155 +#define HOST_CMD_CSR                   0x0404
3156 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
3157 +
3158 +/*
3159 + * INT_SOURCE_CSR: Interrupt source register.
3160 + * Write one to clear corresponding bit.
3161 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3162 + */
3163 +#define INT_SOURCE_CSR                 0x0200
3164 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
3165 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
3166 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
3167 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
3168 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
3169 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
3170 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
3171 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
3172 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
3173 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
3174 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
3175 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
3176 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
3177 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
3178 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
3179 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
3180 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
3181 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
3182 +
3183 +/*
3184 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3185 + */
3186 +#define INT_MASK_CSR                   0x0204
3187 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
3188 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
3189 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
3190 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
3191 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
3192 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
3193 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
3194 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
3195 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
3196 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
3197 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
3198 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
3199 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
3200 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
3201 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
3202 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
3203 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
3204 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
3205 +
3206 +/*
3207 + * WPDMA_GLO_CFG
3208 + */
3209 +#define WPDMA_GLO_CFG                  0x0208
3210 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
3211 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
3212 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
3213 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
3214 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
3215 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
3216 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
3217 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
3218 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
3219 +
3220 +/*
3221 + * WPDMA_RST_IDX
3222 + */
3223 +#define WPDMA_RST_IDX                  0x020c
3224 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
3225 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
3226 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
3227 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
3228 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
3229 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
3230 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
3231 +
3232 +/*
3233 + * DELAY_INT_CFG
3234 + */
3235 +#define DELAY_INT_CFG                  0x0210
3236 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
3237 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
3238 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
3239 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
3240 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
3241 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
3242 +
3243 +/*
3244 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3245 + * AIFSN0: AC_BE
3246 + * AIFSN1: AC_BK
3247 + * AIFSN1: AC_VI
3248 + * AIFSN1: AC_VO
3249 + */
3250 +#define WMM_AIFSN_CFG                  0x0214
3251 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3252 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3253 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3254 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3255 +
3256 +/*
3257 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3258 + * CWMIN0: AC_BE
3259 + * CWMIN1: AC_BK
3260 + * CWMIN1: AC_VI
3261 + * CWMIN1: AC_VO
3262 + */
3263 +#define WMM_CWMIN_CFG                  0x0218
3264 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3265 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3266 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3267 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3268 +
3269 +/*
3270 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3271 + * CWMAX0: AC_BE
3272 + * CWMAX1: AC_BK
3273 + * CWMAX1: AC_VI
3274 + * CWMAX1: AC_VO
3275 + */
3276 +#define WMM_CWMAX_CFG                  0x021c
3277 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3278 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3279 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3280 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3281 +
3282 +/*
3283 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3284 + * AC0TXOP: AC_BK in unit of 32us
3285 + * AC1TXOP: AC_BE in unit of 32us
3286 + */
3287 +#define WMM_TXOP0_CFG                  0x0220
3288 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3289 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3290 +
3291 +/*
3292 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3293 + * AC2TXOP: AC_VI in unit of 32us
3294 + * AC3TXOP: AC_VO in unit of 32us
3295 + */
3296 +#define WMM_TXOP1_CFG                  0x0224
3297 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3298 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3299 +
3300 +/*
3301 + * GPIO_CTRL_CFG:
3302 + */
3303 +#define GPIO_CTRL_CFG                  0x0228
3304 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3305 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3306 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3307 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3308 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3309 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3310 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3311 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3312 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3313 +
3314 +/*
3315 + * MCU_CMD_CFG
3316 + */
3317 +#define MCU_CMD_CFG                    0x022c
3318 +
3319 +/*
3320 + * AC_BK register offsets
3321 + */
3322 +#define TX_BASE_PTR0                   0x0230
3323 +#define TX_MAX_CNT0                    0x0234
3324 +#define TX_CTX_IDX0                    0x0238
3325 +#define TX_DTX_IDX0                    0x023c
3326 +
3327 +/*
3328 + * AC_BE register offsets
3329 + */
3330 +#define TX_BASE_PTR1                   0x0240
3331 +#define TX_MAX_CNT1                    0x0244
3332 +#define TX_CTX_IDX1                    0x0248
3333 +#define TX_DTX_IDX1                    0x024c
3334 +
3335 +/*
3336 + * AC_VI register offsets
3337 + */
3338 +#define TX_BASE_PTR2                   0x0250
3339 +#define TX_MAX_CNT2                    0x0254
3340 +#define TX_CTX_IDX2                    0x0258
3341 +#define TX_DTX_IDX2                    0x025c
3342 +
3343 +/*
3344 + * AC_VO register offsets
3345 + */
3346 +#define TX_BASE_PTR3                   0x0260
3347 +#define TX_MAX_CNT3                    0x0264
3348 +#define TX_CTX_IDX3                    0x0268
3349 +#define TX_DTX_IDX3                    0x026c
3350 +
3351 +/*
3352 + * HCCA register offsets
3353 + */
3354 +#define TX_BASE_PTR4                   0x0270
3355 +#define TX_MAX_CNT4                    0x0274
3356 +#define TX_CTX_IDX4                    0x0278
3357 +#define TX_DTX_IDX4                    0x027c
3358 +
3359 +/*
3360 + * MGMT register offsets
3361 + */
3362 +#define TX_BASE_PTR5                   0x0280
3363 +#define TX_MAX_CNT5                    0x0284
3364 +#define TX_CTX_IDX5                    0x0288
3365 +#define TX_DTX_IDX5                    0x028c
3366 +
3367 +/*
3368 + * RX register offsets
3369 + */
3370 +#define RX_BASE_PTR                    0x0290
3371 +#define RX_MAX_CNT                     0x0294
3372 +#define RX_CRX_IDX                     0x0298
3373 +#define RX_DRX_IDX                     0x029c
3374 +
3375 +/*
3376 + * USB_DMA_CFG
3377 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
3378 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
3379 + * PHY_CLEAR: phy watch dog enable.
3380 + * TX_CLEAR: Clear USB DMA TX path.
3381 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
3382 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
3383 + * RX_BULK_EN: Enable USB DMA Rx.
3384 + * TX_BULK_EN: Enable USB DMA Tx.
3385 + * EP_OUT_VALID: OUT endpoint data valid.
3386 + * RX_BUSY: USB DMA RX FSM busy.
3387 + * TX_BUSY: USB DMA TX FSM busy.
3388 + */
3389 +#define USB_DMA_CFG                    0x02a0
3390 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT        FIELD32(0x000000ff)
3391 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT  FIELD32(0x0000ff00)
3392 +#define USB_DMA_CFG_PHY_CLEAR          FIELD32(0x00010000)
3393 +#define USB_DMA_CFG_TX_CLEAR           FIELD32(0x00080000)
3394 +#define USB_DMA_CFG_TXOP_HALT          FIELD32(0x00100000)
3395 +#define USB_DMA_CFG_RX_BULK_AGG_EN     FIELD32(0x00200000)
3396 +#define USB_DMA_CFG_RX_BULK_EN         FIELD32(0x00400000)
3397 +#define USB_DMA_CFG_TX_BULK_EN         FIELD32(0x00800000)
3398 +#define USB_DMA_CFG_EP_OUT_VALID       FIELD32(0x3f000000)
3399 +#define USB_DMA_CFG_RX_BUSY            FIELD32(0x40000000)
3400 +#define USB_DMA_CFG_TX_BUSY            FIELD32(0x80000000)
3401 +
3402 +/*
3403 + * USB_CYC_CFG
3404 + */
3405 +#define USB_CYC_CFG                    0x02a4
3406 +#define USB_CYC_CFG_CLOCK_CYCLE                FIELD32(0x000000ff)
3407 +
3408 +/*
3409 + * PBF_SYS_CTRL
3410 + * HOST_RAM_WRITE: enable Host program ram write selection
3411 + */
3412 +#define PBF_SYS_CTRL                   0x0400
3413 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3414 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3415 +
3416 +/*
3417 + * PBF registers
3418 + * Most are for debug. Driver doesn't touch PBF register.
3419 + */
3420 +#define PBF_CFG                                0x0408
3421 +#define PBF_MAX_PCNT                   0x040c
3422 +#define PBF_CTRL                       0x0410
3423 +#define PBF_INT_STA                    0x0414
3424 +#define PBF_INT_ENA                    0x0418
3425 +
3426 +/*
3427 + * BCN_OFFSET0:
3428 + */
3429 +#define BCN_OFFSET0                    0x042c
3430 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3431 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3432 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3433 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3434 +
3435 +/*
3436 + * BCN_OFFSET1:
3437 + */
3438 +#define BCN_OFFSET1                    0x0430
3439 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3440 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3441 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3442 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3443 +
3444 +/*
3445 + * PBF registers
3446 + * Most are for debug. Driver doesn't touch PBF register.
3447 + */
3448 +#define TXRXQ_PCNT                     0x0438
3449 +#define PBF_DBG                                0x043c
3450 +
3451 +/*
3452 + * RF registers
3453 + */
3454 +#define        RF_CSR_CFG                      0x0500
3455 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
3456 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
3457 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
3458 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
3459 +
3460 +/*
3461 + * MAC Control/Status Registers(CSR).
3462 + * Some values are set in TU, whereas 1 TU == 1024 us.
3463 + */
3464 +
3465 +/*
3466 + * MAC_CSR0: ASIC revision number.
3467 + * ASIC_REV: 0
3468 + * ASIC_VER: 2870
3469 + */
3470 +#define MAC_CSR0                       0x1000
3471 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3472 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3473 +
3474 +/*
3475 + * MAC_SYS_CTRL:
3476 + */
3477 +#define MAC_SYS_CTRL                   0x1004
3478 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3479 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3480 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3481 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3482 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3483 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3484 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3485 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3486 +
3487 +/*
3488 + * MAC_ADDR_DW0: STA MAC register 0
3489 + */
3490 +#define MAC_ADDR_DW0                   0x1008
3491 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3492 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3493 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3494 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3495 +
3496 +/*
3497 + * MAC_ADDR_DW1: STA MAC register 1
3498 + * UNICAST_TO_ME_MASK:
3499 + * Used to mask off bits from byte 5 of the MAC address
3500 + * to determine the UNICAST_TO_ME bit for RX frames.
3501 + * The full mask is complemented by BSS_ID_MASK:
3502 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3503 + */
3504 +#define MAC_ADDR_DW1                   0x100c
3505 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3506 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3507 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3508 +
3509 +/*
3510 + * MAC_BSSID_DW0: BSSID register 0
3511 + */
3512 +#define MAC_BSSID_DW0                  0x1010
3513 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3514 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3515 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3516 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3517 +
3518 +/*
3519 + * MAC_BSSID_DW1: BSSID register 1
3520 + * BSS_ID_MASK:
3521 + *     0: 1-BSSID mode (BSS index = 0)
3522 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3523 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3524 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3525 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3526 + * BSSID. This will make sure that those bits will be ignored
3527 + * when determining the MY_BSS of RX frames.
3528 + */
3529 +#define MAC_BSSID_DW1                  0x1014
3530 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3531 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3532 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3533 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3534 +
3535 +/*
3536 + * MAX_LEN_CFG: Maximum frame length register.
3537 + * MAX_MPDU: rt2860b max 16k bytes
3538 + * MAX_PSDU: Maximum PSDU length
3539 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3540 + */
3541 +#define MAX_LEN_CFG                    0x1018
3542 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3543 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3544 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3545 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3546 +
3547 +/*
3548 + * BBP_CSR_CFG: BBP serial control register
3549 + * VALUE: Register value to program into BBP
3550 + * REG_NUM: Selected BBP register
3551 + * READ_CONTROL: 0 write BBP, 1 read BBP
3552 + * BUSY: ASIC is busy executing BBP commands
3553 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3554 + * BBP_RW_MODE: 0 serial, 1 paralell
3555 + */
3556 +#define BBP_CSR_CFG                    0x101c
3557 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3558 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3559 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3560 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3561 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3562 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3563 +
3564 +/*
3565 + * RF_CSR_CFG0: RF control register
3566 + * REGID_AND_VALUE: Register value to program into RF
3567 + * BITWIDTH: Selected RF register
3568 + * STANDBYMODE: 0 high when standby, 1 low when standby
3569 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3570 + * BUSY: ASIC is busy executing RF commands
3571 + */
3572 +#define RF_CSR_CFG0                    0x1020
3573 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3574 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3575 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3576 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3577 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3578 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3579 +
3580 +/*
3581 + * RF_CSR_CFG1: RF control register
3582 + * REGID_AND_VALUE: Register value to program into RF
3583 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3584 + *        0: 3 system clock cycle (37.5usec)
3585 + *        1: 5 system clock cycle (62.5usec)
3586 + */
3587 +#define RF_CSR_CFG1                    0x1024
3588 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3589 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3590 +
3591 +/*
3592 + * RF_CSR_CFG2: RF control register
3593 + * VALUE: Register value to program into RF
3594 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3595 + *        0: 3 system clock cycle (37.5usec)
3596 + *        1: 5 system clock cycle (62.5usec)
3597 + */
3598 +#define RF_CSR_CFG2                    0x1028
3599 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3600 +
3601 +/*
3602 + * LED_CFG: LED control
3603 + * color LED's:
3604 + *   0: off
3605 + *   1: blinking upon TX2
3606 + *   2: periodic slow blinking
3607 + *   3: always on
3608 + * LED polarity:
3609 + *   0: active low
3610 + *   1: active high
3611 + */
3612 +#define LED_CFG                                0x102c
3613 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3614 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3615 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3616 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3617 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3618 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3619 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3620 +
3621 +/*
3622 + * XIFS_TIME_CFG: MAC timing
3623 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3624 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3625 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3626 + *     when MAC doesn't reference BBP signal BBRXEND
3627 + * EIFS: unit 1us
3628 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3629 + *
3630 + */
3631 +#define XIFS_TIME_CFG                  0x1100
3632 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3633 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3634 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3635 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3636 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3637 +
3638 +/*
3639 + * BKOFF_SLOT_CFG:
3640 + */
3641 +#define BKOFF_SLOT_CFG                 0x1104
3642 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3643 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3644 +
3645 +/*
3646 + * NAV_TIME_CFG:
3647 + */
3648 +#define NAV_TIME_CFG                   0x1108
3649 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3650 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3651 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3652 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3653 +
3654 +/*
3655 + * CH_TIME_CFG: count as channel busy
3656 + */
3657 +#define CH_TIME_CFG                    0x110c
3658 +
3659 +/*
3660 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3661 + */
3662 +#define PBF_LIFE_TIMER                 0x1110
3663 +
3664 +/*
3665 + * BCN_TIME_CFG:
3666 + * BEACON_INTERVAL: in unit of 1/16 TU
3667 + * TSF_TICKING: Enable TSF auto counting
3668 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3669 + * BEACON_GEN: Enable beacon generator
3670 + */
3671 +#define BCN_TIME_CFG                   0x1114
3672 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3673 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3674 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3675 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3676 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3677 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3678 +
3679 +/*
3680 + * TBTT_SYNC_CFG:
3681 + */
3682 +#define TBTT_SYNC_CFG                  0x1118
3683 +
3684 +/*
3685 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3686 + */
3687 +#define TSF_TIMER_DW0                  0x111c
3688 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3689 +
3690 +/*
3691 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3692 + */
3693 +#define TSF_TIMER_DW1                  0x1120
3694 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3695 +
3696 +/*
3697 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3698 + */
3699 +#define TBTT_TIMER                     0x1124
3700 +
3701 +/*
3702 + * INT_TIMER_CFG:
3703 + */
3704 +#define INT_TIMER_CFG                  0x1128
3705 +
3706 +/*
3707 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3708 + */
3709 +#define INT_TIMER_EN                   0x112c
3710 +
3711 +/*
3712 + * CH_IDLE_STA: channel idle time
3713 + */
3714 +#define CH_IDLE_STA                    0x1130
3715 +
3716 +/*
3717 + * CH_BUSY_STA: channel busy time
3718 + */
3719 +#define CH_BUSY_STA                    0x1134
3720 +
3721 +/*
3722 + * MAC_STATUS_CFG:
3723 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3724 + *     if 1 or higher one of the 2 registers is busy.
3725 + */
3726 +#define MAC_STATUS_CFG                 0x1200
3727 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3728 +
3729 +/*
3730 + * PWR_PIN_CFG:
3731 + */
3732 +#define PWR_PIN_CFG                    0x1204
3733 +
3734 +/*
3735 + * AUTOWAKEUP_CFG: Manual power control / status register
3736 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3737 + * AUTOWAKE: 0:sleep, 1:awake
3738 + */
3739 +#define AUTOWAKEUP_CFG                 0x1208
3740 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3741 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3742 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3743 +
3744 +/*
3745 + * EDCA_AC0_CFG:
3746 + */
3747 +#define EDCA_AC0_CFG                   0x1300
3748 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
3749 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3750 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3751 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3752 +
3753 +/*
3754 + * EDCA_AC1_CFG:
3755 + */
3756 +#define EDCA_AC1_CFG                   0x1304
3757 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
3758 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3759 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3760 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3761 +
3762 +/*
3763 + * EDCA_AC2_CFG:
3764 + */
3765 +#define EDCA_AC2_CFG                   0x1308
3766 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
3767 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3768 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3769 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3770 +
3771 +/*
3772 + * EDCA_AC3_CFG:
3773 + */
3774 +#define EDCA_AC3_CFG                   0x130c
3775 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
3776 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3777 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3778 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3779 +
3780 +/*
3781 + * EDCA_TID_AC_MAP:
3782 + */
3783 +#define EDCA_TID_AC_MAP                        0x1310
3784 +
3785 +/*
3786 + * TX_PWR_CFG_0:
3787 + */
3788 +#define TX_PWR_CFG_0                   0x1314
3789 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3790 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3791 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3792 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3793 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3794 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3795 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3796 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3797 +
3798 +/*
3799 + * TX_PWR_CFG_1:
3800 + */
3801 +#define TX_PWR_CFG_1                   0x1318
3802 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3803 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3804 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3805 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3806 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3807 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3808 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3809 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3810 +
3811 +/*
3812 + * TX_PWR_CFG_2:
3813 + */
3814 +#define TX_PWR_CFG_2                   0x131c
3815 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3816 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3817 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3818 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3819 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3820 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3821 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3822 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3823 +
3824 +/*
3825 + * TX_PWR_CFG_3:
3826 + */
3827 +#define TX_PWR_CFG_3                   0x1320
3828 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3829 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3830 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3831 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3832 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3833 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3834 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3835 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3836 +
3837 +/*
3838 + * TX_PWR_CFG_4:
3839 + */
3840 +#define TX_PWR_CFG_4                   0x1324
3841 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3842 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3843 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3844 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3845 +
3846 +/*
3847 + * TX_PIN_CFG:
3848 + */
3849 +#define TX_PIN_CFG                     0x1328
3850 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3851 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3852 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3853 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3854 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3855 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3856 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3857 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3858 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3859 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3860 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3861 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3862 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3863 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3864 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3865 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3866 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3867 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3868 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3869 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3870 +
3871 +/*
3872 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3873 + */
3874 +#define TX_BAND_CFG                    0x132c
3875 +#define TX_BAND_CFG_HT40_PLUS          FIELD32(0x00000001)
3876 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3877 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3878 +
3879 +/*
3880 + * TX_SW_CFG0:
3881 + */
3882 +#define TX_SW_CFG0                     0x1330
3883 +
3884 +/*
3885 + * TX_SW_CFG1:
3886 + */
3887 +#define TX_SW_CFG1                     0x1334
3888 +
3889 +/*
3890 + * TX_SW_CFG2:
3891 + */
3892 +#define TX_SW_CFG2                     0x1338
3893 +
3894 +/*
3895 + * TXOP_THRES_CFG:
3896 + */
3897 +#define TXOP_THRES_CFG                 0x133c
3898 +
3899 +/*
3900 + * TXOP_CTRL_CFG:
3901 + */
3902 +#define TXOP_CTRL_CFG                  0x1340
3903 +
3904 +/*
3905 + * TX_RTS_CFG:
3906 + * RTS_THRES: unit:byte
3907 + * RTS_FBK_EN: enable rts rate fallback
3908 + */
3909 +#define TX_RTS_CFG                     0x1344
3910 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3911 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3912 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3913 +
3914 +/*
3915 + * TX_TIMEOUT_CFG:
3916 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3917 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3918 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3919 + *                it is recommended that:
3920 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3921 + */
3922 +#define TX_TIMEOUT_CFG                 0x1348
3923 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3924 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3925 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3926 +
3927 +/*
3928 + * TX_RTY_CFG:
3929 + * SHORT_RTY_LIMIT: short retry limit
3930 + * LONG_RTY_LIMIT: long retry limit
3931 + * LONG_RTY_THRE: Long retry threshoold
3932 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3933 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3934 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3935 + *               0:expired by retry limit, 1: expired by mpdu life timer
3936 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3937 + */
3938 +#define TX_RTY_CFG                     0x134c
3939 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3940 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3941 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3942 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3943 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3944 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3945 +
3946 +/*
3947 + * TX_LINK_CFG:
3948 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3949 + * MFB_ENABLE: TX apply remote MFB 1:enable
3950 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3951 + *                     0: not apply remote remote unsolicit (MFS=7)
3952 + * TX_MRQ_EN: MCS request TX enable
3953 + * TX_RDG_EN: RDG TX enable
3954 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3955 + * REMOTE_MFB: remote MCS feedback
3956 + * REMOTE_MFS: remote MCS feedback sequence number
3957 + */
3958 +#define TX_LINK_CFG                    0x1350
3959 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3960 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3961 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3962 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3963 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3964 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3965 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3966 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3967 +
3968 +/*
3969 + * HT_FBK_CFG0:
3970 + */
3971 +#define HT_FBK_CFG0                    0x1354
3972 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3973 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3974 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3975 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3976 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3977 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3978 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3979 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3980 +
3981 +/*
3982 + * HT_FBK_CFG1:
3983 + */
3984 +#define HT_FBK_CFG1                    0x1358
3985 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3986 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3987 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3988 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3989 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3990 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3991 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3992 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3993 +
3994 +/*
3995 + * LG_FBK_CFG0:
3996 + */
3997 +#define LG_FBK_CFG0                    0x135c
3998 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
3999 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
4000 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
4001 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
4002 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
4003 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
4004 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
4005 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
4006 +
4007 +/*
4008 + * LG_FBK_CFG1:
4009 + */
4010 +#define LG_FBK_CFG1                    0x1360
4011 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
4012 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
4013 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
4014 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
4015 +
4016 +/*
4017 + * CCK_PROT_CFG: CCK Protection
4018 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4019 + * PROTECT_CTRL: Protection control frame type for CCK TX
4020 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
4021 + * PROTECT_NAV: TXOP protection type for CCK TX
4022 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4023 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4024 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4025 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4026 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4027 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4028 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4029 + * RTS_TH_EN: RTS threshold enable on CCK TX
4030 + */
4031 +#define CCK_PROT_CFG                   0x1364
4032 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
4033 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
4034 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
4035 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
4036 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
4037 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
4038 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
4039 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
4040 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
4041 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
4042 +
4043 +/*
4044 + * OFDM_PROT_CFG: OFDM Protection
4045 + */
4046 +#define OFDM_PROT_CFG                  0x1368
4047 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4048 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4049 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4050 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4051 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4052 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4053 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4054 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4055 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4056 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4057 +
4058 +/*
4059 + * MM20_PROT_CFG: MM20 Protection
4060 + */
4061 +#define MM20_PROT_CFG                  0x136c
4062 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4063 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4064 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4065 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4066 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4067 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4068 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4069 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4070 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4071 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4072 +
4073 +/*
4074 + * MM40_PROT_CFG: MM40 Protection
4075 + */
4076 +#define MM40_PROT_CFG                  0x1370
4077 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4078 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4079 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4080 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4081 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4082 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4083 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4084 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4085 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4086 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4087 +
4088 +/*
4089 + * GF20_PROT_CFG: GF20 Protection
4090 + */
4091 +#define GF20_PROT_CFG                  0x1374
4092 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4093 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4094 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4095 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4096 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4097 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4098 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4099 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4100 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4101 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4102 +
4103 +/*
4104 + * GF40_PROT_CFG: GF40 Protection
4105 + */
4106 +#define GF40_PROT_CFG                  0x1378
4107 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4108 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4109 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4110 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4111 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4112 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4113 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4114 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4115 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4116 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4117 +
4118 +/*
4119 + * EXP_CTS_TIME:
4120 + */
4121 +#define EXP_CTS_TIME                   0x137c
4122 +
4123 +/*
4124 + * EXP_ACK_TIME:
4125 + */
4126 +#define EXP_ACK_TIME                   0x1380
4127 +
4128 +/*
4129 + * RX_FILTER_CFG: RX configuration register.
4130 + */
4131 +#define RX_FILTER_CFG                  0x1400
4132 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
4133 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
4134 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
4135 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4136 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
4137 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
4138 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
4139 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
4140 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
4141 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
4142 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
4143 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
4144 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
4145 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
4146 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
4147 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
4148 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
4149 +
4150 +/*
4151 + * AUTO_RSP_CFG:
4152 + * AUTORESPONDER: 0: disable, 1: enable
4153 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4154 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4155 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4156 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4157 + * DUAL_CTS_EN: Power bit value in control frame
4158 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4159 + */
4160 +#define AUTO_RSP_CFG                   0x1404
4161 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
4162 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
4163 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
4164 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
4165 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
4166 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
4167 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
4168 +
4169 +/*
4170 + * LEGACY_BASIC_RATE:
4171 + */
4172 +#define LEGACY_BASIC_RATE              0x1408
4173 +
4174 +/*
4175 + * HT_BASIC_RATE:
4176 + */
4177 +#define HT_BASIC_RATE                  0x140c
4178 +
4179 +/*
4180 + * HT_CTRL_CFG:
4181 + */
4182 +#define HT_CTRL_CFG                    0x1410
4183 +
4184 +/*
4185 + * SIFS_COST_CFG:
4186 + */
4187 +#define SIFS_COST_CFG                  0x1414
4188 +
4189 +/*
4190 + * RX_PARSER_CFG:
4191 + * Set NAV for all received frames
4192 + */
4193 +#define RX_PARSER_CFG                  0x1418
4194 +
4195 +/*
4196 + * TX_SEC_CNT0:
4197 + */
4198 +#define TX_SEC_CNT0                    0x1500
4199 +
4200 +/*
4201 + * RX_SEC_CNT0:
4202 + */
4203 +#define RX_SEC_CNT0                    0x1504
4204 +
4205 +/*
4206 + * CCMP_FC_MUTE:
4207 + */
4208 +#define CCMP_FC_MUTE                   0x1508
4209 +
4210 +/*
4211 + * TXOP_HLDR_ADDR0:
4212 + */
4213 +#define TXOP_HLDR_ADDR0                        0x1600
4214 +
4215 +/*
4216 + * TXOP_HLDR_ADDR1:
4217 + */
4218 +#define TXOP_HLDR_ADDR1                        0x1604
4219 +
4220 +/*
4221 + * TXOP_HLDR_ET:
4222 + */
4223 +#define TXOP_HLDR_ET                   0x1608
4224 +
4225 +/*
4226 + * QOS_CFPOLL_RA_DW0:
4227 + */
4228 +#define QOS_CFPOLL_RA_DW0              0x160c
4229 +
4230 +/*
4231 + * QOS_CFPOLL_RA_DW1:
4232 + */
4233 +#define QOS_CFPOLL_RA_DW1              0x1610
4234 +
4235 +/*
4236 + * QOS_CFPOLL_QC:
4237 + */
4238 +#define QOS_CFPOLL_QC                  0x1614
4239 +
4240 +/*
4241 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4242 + */
4243 +#define RX_STA_CNT0                    0x1700
4244 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
4245 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
4246 +
4247 +/*
4248 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4249 + */
4250 +#define RX_STA_CNT1                    0x1704
4251 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
4252 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
4253 +
4254 +/*
4255 + * RX_STA_CNT2:
4256 + */
4257 +#define RX_STA_CNT2                    0x1708
4258 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
4259 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
4260 +
4261 +/*
4262 + * TX_STA_CNT0: TX Beacon count
4263 + */
4264 +#define TX_STA_CNT0                    0x170c
4265 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
4266 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
4267 +
4268 +/*
4269 + * TX_STA_CNT1: TX tx count
4270 + */
4271 +#define TX_STA_CNT1                    0x1710
4272 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
4273 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
4274 +
4275 +/*
4276 + * TX_STA_CNT2: TX tx count
4277 + */
4278 +#define TX_STA_CNT2                    0x1714
4279 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
4280 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
4281 +
4282 +/*
4283 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4284 + */
4285 +#define TX_STA_FIFO                    0x1718
4286 +#define TX_STA_FIFO_VALID              FIELD32(0x00000001)
4287 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
4288 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
4289 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4290 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4291 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4292 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4293 +
4294 +/*
4295 + * TX_AGG_CNT: Debug counter
4296 + */
4297 +#define TX_AGG_CNT                     0x171c
4298 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4299 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4300 +
4301 +/*
4302 + * TX_AGG_CNT0:
4303 + */
4304 +#define TX_AGG_CNT0                    0x1720
4305 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4306 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4307 +
4308 +/*
4309 + * TX_AGG_CNT1:
4310 + */
4311 +#define TX_AGG_CNT1                    0x1724
4312 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4313 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4314 +
4315 +/*
4316 + * TX_AGG_CNT2:
4317 + */
4318 +#define TX_AGG_CNT2                    0x1728
4319 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4320 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4321 +
4322 +/*
4323 + * TX_AGG_CNT3:
4324 + */
4325 +#define TX_AGG_CNT3                    0x172c
4326 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4327 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4328 +
4329 +/*
4330 + * TX_AGG_CNT4:
4331 + */
4332 +#define TX_AGG_CNT4                    0x1730
4333 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4334 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4335 +
4336 +/*
4337 + * TX_AGG_CNT5:
4338 + */
4339 +#define TX_AGG_CNT5                    0x1734
4340 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4341 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4342 +
4343 +/*
4344 + * TX_AGG_CNT6:
4345 + */
4346 +#define TX_AGG_CNT6                    0x1738
4347 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4348 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4349 +
4350 +/*
4351 + * TX_AGG_CNT7:
4352 + */
4353 +#define TX_AGG_CNT7                    0x173c
4354 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4355 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4356 +
4357 +/*
4358 + * MPDU_DENSITY_CNT:
4359 + * TX_ZERO_DEL: TX zero length delimiter count
4360 + * RX_ZERO_DEL: RX zero length delimiter count
4361 + */
4362 +#define MPDU_DENSITY_CNT               0x1740
4363 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4364 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4365 +
4366 +/*
4367 + * Security key table memory.
4368 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4369 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4370 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4371 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4372 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4373 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4374 + */
4375 +#define MAC_WCID_BASE                  0x1800
4376 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4377 +#define MAC_IVEIV_TABLE_BASE           0x6000
4378 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4379 +#define SHARED_KEY_TABLE_BASE          0x6c00
4380 +#define SHARED_KEY_MODE_BASE           0x7000
4381 +
4382 +#define MAC_WCID_ENTRY(__idx) \
4383 +       ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4384 +#define PAIRWISE_KEY_ENTRY(__idx) \
4385 +       ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4386 +#define MAC_IVEIV_ENTRY(__idx) \
4387 +       ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4388 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4389 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4390 +#define SHARED_KEY_ENTRY(__idx) \
4391 +       ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4392 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4393 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4394 +
4395 +struct mac_wcid_entry {
4396 +       u8 mac[6];
4397 +       u8 reserved[2];
4398 +} __attribute__ ((packed));
4399 +
4400 +struct hw_key_entry {
4401 +       u8 key[16];
4402 +       u8 tx_mic[8];
4403 +       u8 rx_mic[8];
4404 +} __attribute__ ((packed));
4405 +
4406 +struct mac_iveiv_entry {
4407 +       u8 iv[8];
4408 +} __attribute__ ((packed));
4409 +
4410 +/*
4411 + * MAC_WCID_ATTRIBUTE:
4412 + */
4413 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4414 +#define MAC_WCID_ATTRIBUTE_CIPHER      FIELD32(0x0000000e)
4415 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4416 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4417 +
4418 +/*
4419 + * SHARED_KEY_MODE:
4420 + */
4421 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4422 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4423 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4424 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4425 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4426 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4427 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4428 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4429 +
4430 +/*
4431 + * HOST-MCU communication
4432 + */
4433 +
4434 +/*
4435 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4436 + */
4437 +#define H2M_MAILBOX_CSR                        0x7010
4438 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4439 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4440 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4441 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4442 +
4443 +/*
4444 + * H2M_MAILBOX_CID:
4445 + */
4446 +#define H2M_MAILBOX_CID                        0x7014
4447 +
4448 +/*
4449 + * H2M_MAILBOX_STATUS:
4450 + */
4451 +#define H2M_MAILBOX_STATUS             0x701c
4452 +
4453 +/*
4454 + * H2M_INT_SRC:
4455 + */
4456 +#define H2M_INT_SRC                    0x7024
4457 +
4458 +/*
4459 + * H2M_BBP_AGENT:
4460 + */
4461 +#define H2M_BBP_AGENT                  0x7028
4462 +
4463 +/*
4464 + * MCU_LEDCS: LED control for MCU Mailbox.
4465 + */
4466 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4467 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4468 +
4469 +/*
4470 + * HW_CS_CTS_BASE:
4471 + * Carrier-sense CTS frame base address.
4472 + * It's where mac stores carrier-sense frame for carrier-sense function.
4473 + */
4474 +#define HW_CS_CTS_BASE                 0x7700
4475 +
4476 +/*
4477 + * HW_DFS_CTS_BASE:
4478 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4479 + */
4480 +#define HW_DFS_CTS_BASE                        0x7780
4481 +
4482 +/*
4483 + * TXRX control registers - base address 0x3000
4484 + */
4485 +
4486 +/*
4487 + * TXRX_CSR1:
4488 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4489 + */
4490 +#define TXRX_CSR1                      0x77d0
4491 +
4492 +/*
4493 + * HW_DEBUG_SETTING_BASE:
4494 + * since NULL frame won't be that long (256 byte)
4495 + * We steal 16 tail bytes to save debugging settings
4496 + */
4497 +#define HW_DEBUG_SETTING_BASE          0x77f0
4498 +#define HW_DEBUG_SETTING_BASE2         0x7770
4499 +
4500 +/*
4501 + * HW_BEACON_BASE
4502 + * In order to support maximum 8 MBSS and its maximum length
4503 + * is 512 bytes for each beacon
4504 + * Three section discontinue memory segments will be used.
4505 + * 1. The original region for BCN 0~3
4506 + * 2. Extract memory from FCE table for BCN 4~5
4507 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4508 + *    It occupied those memory of wcid 238~253 for BCN 6
4509 + *    and wcid 222~237 for BCN 7
4510 + *
4511 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4512 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4513 + */
4514 +#define HW_BEACON_BASE0                        0x7800
4515 +#define HW_BEACON_BASE1                        0x7a00
4516 +#define HW_BEACON_BASE2                        0x7c00
4517 +#define HW_BEACON_BASE3                        0x7e00
4518 +#define HW_BEACON_BASE4                        0x7200
4519 +#define HW_BEACON_BASE5                        0x7400
4520 +#define HW_BEACON_BASE6                        0x5dc0
4521 +#define HW_BEACON_BASE7                        0x5bc0
4522 +
4523 +#define HW_BEACON_OFFSET(__index) \
4524 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4525 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4526 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4527 +
4528 +/*
4529 + * 8051 firmware image.
4530 + */
4531 +#define FIRMWARE_RT2870                        "rt2870.bin"
4532 +#define FIRMWARE_IMAGE_BASE            0x3000
4533 +
4534 +/*
4535 + * BBP registers.
4536 + * The wordsize of the BBP is 8 bits.
4537 + */
4538 +
4539 +/*
4540 + * BBP 1: TX Antenna
4541 + */
4542 +#define BBP1_TX_POWER                  FIELD8(0x07)
4543 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4544 +
4545 +/*
4546 + * BBP 3: RX Antenna
4547 + */
4548 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4549 +#define BBP3_HT40_PLUS                 FIELD8(0x20)
4550 +
4551 +/*
4552 + * BBP 4: Bandwidth
4553 + */
4554 +#define BBP4_TX_BF                     FIELD8(0x01)
4555 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
4556 +
4557 +/*
4558 + * RFCSR registers
4559 + * The wordsize of the RFCSR is 8 bits.
4560 + */
4561 +
4562 +/*
4563 + * RFCSR 6:
4564 + */
4565 +#define RFCSR6_R                       FIELD8(0x03)
4566 +
4567 +/*
4568 + * RFCSR 7:
4569 + */
4570 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
4571 +
4572 +/*
4573 + * RFCSR 12:
4574 + */
4575 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
4576 +
4577 +/*
4578 + * RFCSR 22:
4579 + */
4580 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
4581 +
4582 +/*
4583 + * RFCSR 23:
4584 + */
4585 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
4586 +
4587 +/*
4588 + * RFCSR 30:
4589 + */
4590 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
4591 +
4592 +/*
4593 + * RF registers
4594 + */
4595 +
4596 +/*
4597 + * RF 2
4598 + */
4599 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4600 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4601 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4602 +
4603 +/*
4604 + * RF 3
4605 + */
4606 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4607 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4608 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4609 +
4610 +/*
4611 + * RF 4
4612 + */
4613 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4614 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4615 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4616 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4617 +#define RF4_HT40                       FIELD32(0x00200000)
4618 +
4619 +/*
4620 + * EEPROM content.
4621 + * The wordsize of the EEPROM is 16 bits.
4622 + */
4623 +
4624 +/*
4625 + * EEPROM Version
4626 + */
4627 +#define EEPROM_VERSION                 0x0001
4628 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4629 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4630 +
4631 +/*
4632 + * HW MAC address.
4633 + */
4634 +#define EEPROM_MAC_ADDR_0              0x0002
4635 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4636 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4637 +#define EEPROM_MAC_ADDR_1              0x0003
4638 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4639 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4640 +#define EEPROM_MAC_ADDR_2              0x0004
4641 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4642 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4643 +
4644 +/*
4645 + * EEPROM ANTENNA config
4646 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4647 + * TXPATH: 1: 1T, 2: 2T
4648 + */
4649 +#define        EEPROM_ANTENNA                  0x001a
4650 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4651 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4652 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4653 +
4654 +/*
4655 + * EEPROM NIC config
4656 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4657 + */
4658 +#define        EEPROM_NIC                      0x001b
4659 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4660 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4661 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4662 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4663 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4664 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4665 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4666 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4667 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4668 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4669 +
4670 +/*
4671 + * EEPROM frequency
4672 + */
4673 +#define        EEPROM_FREQ                     0x001d
4674 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4675 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4676 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4677 +
4678 +/*
4679 + * EEPROM LED
4680 + * POLARITY_RDY_G: Polarity RDY_G setting.
4681 + * POLARITY_RDY_A: Polarity RDY_A setting.
4682 + * POLARITY_ACT: Polarity ACT setting.
4683 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4684 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4685 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4686 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4687 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4688 + * LED_MODE: Led mode.
4689 + */
4690 +#define EEPROM_LED1                    0x001e
4691 +#define EEPROM_LED2                    0x001f
4692 +#define EEPROM_LED3                    0x0020
4693 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4694 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4695 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4696 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4697 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4698 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4699 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4700 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4701 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4702 +
4703 +/*
4704 + * EEPROM LNA
4705 + */
4706 +#define EEPROM_LNA                     0x0022
4707 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4708 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4709 +
4710 +/*
4711 + * EEPROM RSSI BG offset
4712 + */
4713 +#define EEPROM_RSSI_BG                 0x0023
4714 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4715 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4716 +
4717 +/*
4718 + * EEPROM RSSI BG2 offset
4719 + */
4720 +#define EEPROM_RSSI_BG2                        0x0024
4721 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4722 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4723 +
4724 +/*
4725 + * EEPROM RSSI A offset
4726 + */
4727 +#define EEPROM_RSSI_A                  0x0025
4728 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4729 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4730 +
4731 +/*
4732 + * EEPROM RSSI A2 offset
4733 + */
4734 +#define EEPROM_RSSI_A2                 0x0026
4735 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4736 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4737 +
4738 +/*
4739 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4740 + *     This is delta in 40MHZ.
4741 + * VALUE: Tx Power dalta value (MAX=4)
4742 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4743 + * TXPOWER: Enable:
4744 + */
4745 +#define EEPROM_TXPOWER_DELTA           0x0028
4746 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4747 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4748 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4749 +
4750 +/*
4751 + * EEPROM TXPOWER 802.11BG
4752 + */
4753 +#define        EEPROM_TXPOWER_BG1              0x0029
4754 +#define        EEPROM_TXPOWER_BG2              0x0030
4755 +#define EEPROM_TXPOWER_BG_SIZE         7
4756 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4757 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4758 +
4759 +/*
4760 + * EEPROM TXPOWER 802.11A
4761 + */
4762 +#define EEPROM_TXPOWER_A1              0x003c
4763 +#define EEPROM_TXPOWER_A2              0x0053
4764 +#define EEPROM_TXPOWER_A_SIZE          6
4765 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4766 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4767 +
4768 +/*
4769 + * EEPROM TXpower byrate: 20MHZ power
4770 + */
4771 +#define EEPROM_TXPOWER_BYRATE          0x006f
4772 +
4773 +/*
4774 + * EEPROM BBP.
4775 + */
4776 +#define        EEPROM_BBP_START                0x0078
4777 +#define EEPROM_BBP_SIZE                        16
4778 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4779 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4780 +
4781 +/*
4782 + * MCU mailbox commands.
4783 + */
4784 +#define MCU_SLEEP                      0x30
4785 +#define MCU_WAKEUP                     0x31
4786 +#define MCU_LED                                0x50
4787 +#define MCU_LED_STRENGTH               0x51
4788 +#define MCU_LED_1                      0x52
4789 +#define MCU_LED_2                      0x53
4790 +#define MCU_LED_3                      0x54
4791 +#define MCU_RADAR                      0x60
4792 +#define MCU_BOOT_SIGNAL                        0x72
4793 +
4794 +/*
4795 + * DMA descriptor defines.
4796 + */
4797 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4798 +#define TXINFO_DESC_SIZE               ( 1 * sizeof(__le32) )
4799 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4800 +#define RXD_DESC_SIZE                  ( 1 * sizeof(__le32) )
4801 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4802 +
4803 +/*
4804 + * TX descriptor format for TX, PRIO and Beacon Ring.
4805 + */
4806 +
4807 +/*
4808 + * Word0
4809 + */
4810 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4811 +
4812 +/*
4813 + * Word1
4814 + */
4815 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4816 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4817 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4818 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4819 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4820 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4821 +
4822 +/*
4823 + * Word2
4824 + */
4825 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4826 +
4827 +/*
4828 + * Word3
4829 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4830 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4831 + *       0:MGMT, 1:HCCA 2:EDCA
4832 + */
4833 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4834 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4835 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4836 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4837 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4838 +
4839 +/*
4840 + * TX Info structure
4841 + */
4842 +
4843 +/*
4844 + * Word0
4845 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4846 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4847 + *       0:MGMT, 1:HCCA 2:EDCA
4848 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4849 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4850 + *               Force USB DMA transmit frame from current selected endpoint
4851 + */
4852 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN   FIELD32(0x0000ffff)
4853 +#define TXINFO_W0_WIV                  FIELD32(0x01000000)
4854 +#define TXINFO_W0_QSEL                 FIELD32(0x06000000)
4855 +#define TXINFO_W0_SW_USE_LAST_ROUND    FIELD32(0x08000000)
4856 +#define TXINFO_W0_USB_DMA_NEXT_VALID   FIELD32(0x40000000)
4857 +#define TXINFO_W0_USB_DMA_TX_BURST     FIELD32(0x80000000)
4858 +
4859 +/*
4860 + * TX WI structure
4861 + */
4862 +
4863 +/*
4864 + * Word0
4865 + * FRAG: 1 To inform TKIP engine this is a fragment.
4866 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4867 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4868 + * BW: Channel bandwidth 20MHz or 40 MHz
4869 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4870 + */
4871 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4872 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4873 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4874 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4875 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4876 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4877 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4878 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4879 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4880 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4881 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4882 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4883 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4884 +
4885 +/*
4886 + * Word1
4887 + */
4888 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4889 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4890 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4891 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4892 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4893 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4894 +
4895 +/*
4896 + * Word2
4897 + */
4898 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4899 +
4900 +/*
4901 + * Word3
4902 + */
4903 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4904 +
4905 +/*
4906 + * RX descriptor format for RX Ring.
4907 + */
4908 +
4909 +/*
4910 + * Word0
4911 + * UNICAST_TO_ME: This RX frame is unicast to me.
4912 + * MULTICAST: This is a multicast frame.
4913 + * BROADCAST: This is a broadcast frame.
4914 + * MY_BSS: this frame belongs to the same BSSID.
4915 + * CRC_ERROR: CRC error.
4916 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4917 + * AMSDU: rx with 802.3 header, not 802.11 header.
4918 + */
4919 +
4920 +#define RXD_W0_BA                      FIELD32(0x00000001)
4921 +#define RXD_W0_DATA                    FIELD32(0x00000002)
4922 +#define RXD_W0_NULLDATA                        FIELD32(0x00000004)
4923 +#define RXD_W0_FRAG                    FIELD32(0x00000008)
4924 +#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000010)
4925 +#define RXD_W0_MULTICAST               FIELD32(0x00000020)
4926 +#define RXD_W0_BROADCAST               FIELD32(0x00000040)
4927 +#define RXD_W0_MY_BSS                  FIELD32(0x00000080)
4928 +#define RXD_W0_CRC_ERROR               FIELD32(0x00000100)
4929 +#define RXD_W0_CIPHER_ERROR            FIELD32(0x00000600)
4930 +#define RXD_W0_AMSDU                   FIELD32(0x00000800)
4931 +#define RXD_W0_HTC                     FIELD32(0x00001000)
4932 +#define RXD_W0_RSSI                    FIELD32(0x00002000)
4933 +#define RXD_W0_L2PAD                   FIELD32(0x00004000)
4934 +#define RXD_W0_AMPDU                   FIELD32(0x00008000)
4935 +#define RXD_W0_DECRYPTED               FIELD32(0x00010000)
4936 +#define RXD_W0_PLCP_RSSI               FIELD32(0x00020000)
4937 +#define RXD_W0_CIPHER_ALG              FIELD32(0x00040000)
4938 +#define RXD_W0_LAST_AMSDU              FIELD32(0x00080000)
4939 +#define RXD_W0_PLCP_SIGNAL             FIELD32(0xfff00000)
4940 +
4941 +/*
4942 + * RX WI structure
4943 + */
4944 +
4945 +/*
4946 + * Word0
4947 + */
4948 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4949 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4950 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4951 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4952 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4953 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4954 +
4955 +/*
4956 + * Word1
4957 + */
4958 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4959 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4960 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4961 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4962 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4963 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4964 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4965 +
4966 +/*
4967 + * Word2
4968 + */
4969 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4970 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4971 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4972 +
4973 +/*
4974 + * Word3
4975 + */
4976 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4977 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4978 +
4979 +/*
4980 + * Macro's for converting txpower from EEPROM to mac80211 value
4981 + * and from mac80211 value to register value.
4982 + */
4983 +#define MIN_G_TXPOWER  0
4984 +#define MIN_A_TXPOWER  -7
4985 +#define MAX_G_TXPOWER  31
4986 +#define MAX_A_TXPOWER  15
4987 +#define DEFAULT_TXPOWER        5
4988 +
4989 +#define TXPOWER_G_FROM_DEV(__txpower) \
4990 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4991 +
4992 +#define TXPOWER_G_TO_DEV(__txpower) \
4993 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4994 +
4995 +#define TXPOWER_A_FROM_DEV(__txpower) \
4996 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4997 +
4998 +#define TXPOWER_A_TO_DEV(__txpower) \
4999 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5000 +
5001 +#endif /* RT2800USB_H */
5002 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5003 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5004 @@ -142,6 +142,7 @@ struct rt2x00_chip {
5005  #define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
5006  #define RT2890         0x0701  /* 2.4GHz PCIe */
5007  #define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
5008 +#define RT2870         0x1600
5009
5010         u16 rf;
5011         u32 rev;
5012 @@ -780,6 +781,12 @@ struct rt2x00_dev {
5013         u8 freq_offset;
5014
5015         /*
5016 +        * Calibration information (for rt2800usb).
5017 +        */
5018 +       u8 calibration_bw20;
5019 +       u8 calibration_bw40;
5020 +
5021 +       /*
5022          * Low level statistics which will have
5023          * to be kept up to date while device is running.
5024          */