package/mac80211/patches/303-rt2x00-Implement-support-for-rt2800usb.patch

   1 From ec4f9f97afa3f792cf64035b8458bf2f8648a76f Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Wed, 4 Feb 2009 20:45:56 +0100
   4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
   5
   6 Add support for the rt2800usb chipset.
   7
   8 Includes various patches from Mattias and Felix.
   9
  10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  12 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  13 ---
  14  drivers/net/wireless/rt2x00/Kconfig     |   14 +
  15  drivers/net/wireless/rt2x00/Makefile    |    1 +
  16  drivers/net/wireless/rt2x00/rt2800usb.c | 2928 +++++++++++++++++++++++++++++++
  17  drivers/net/wireless/rt2x00/rt2800usb.h | 1940 ++++++++++++++++++++
  18  drivers/net/wireless/rt2x00/rt2x00.h    |    7 +
  19  5 files changed, 4890 insertions(+), 0 deletions(-)
  20  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
  21  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
  22
  23 --- a/drivers/net/wireless/rt2x00/Makefile
  24 +++ b/drivers/net/wireless/rt2x00/Makefile
  25 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI)                 += rt61pci.o
  26  obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  27  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  28  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  29 +obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  30 --- /dev/null
  31 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
  32 @@ -0,0 +1,2928 @@
  33 +/*
  34 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  35 +       <http://rt2x00.serialmonkey.com>
  36 +
  37 +       This program is free software; you can redistribute it and/or modify
  38 +       it under the terms of the GNU General Public License as published by
  39 +       the Free Software Foundation; either version 2 of the License, or
  40 +       (at your option) any later version.
  41 +
  42 +       This program is distributed in the hope that it will be useful,
  43 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  44 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  45 +       GNU General Public License for more details.
  46 +
  47 +       You should have received a copy of the GNU General Public License
  48 +       along with this program; if not, write to the
  49 +       Free Software Foundation, Inc.,
  50 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  51 + */
  52 +
  53 +/*
  54 +       Module: rt2800usb
  55 +       Abstract: rt2800usb device specific routines.
  56 +       Supported chipsets: RT2800U.
  57 + */
  58 +
  59 +#include <linux/crc-ccitt.h>
  60 +#include <linux/delay.h>
  61 +#include <linux/etherdevice.h>
  62 +#include <linux/init.h>
  63 +#include <linux/kernel.h>
  64 +#include <linux/module.h>
  65 +#include <linux/usb.h>
  66 +
  67 +#include "rt2x00.h"
  68 +#include "rt2x00usb.h"
  69 +#include "rt2800usb.h"
  70 +
  71 +/*
  72 + * Allow hardware encryption to be disabled.
  73 + */
  74 +static int modparam_nohwcrypt = 0;
  75 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  76 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77 +
  78 +/*
  79 + * Register access.
  80 + * All access to the CSR registers will go through the methods
  81 + * rt2x00usb_register_read and rt2x00usb_register_write.
  82 + * BBP and RF register require indirect register access,
  83 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
  84 + * These indirect registers work with busy bits,
  85 + * and we will try maximal REGISTER_BUSY_COUNT times to access
  86 + * the register while taking a REGISTER_BUSY_DELAY us delay
  87 + * between each attampt. When the busy bit is still set at that time,
  88 + * the access attempt is considered to have failed,
  89 + * and we will print an error.
  90 + * The _lock versions must be used if you already hold the csr_mutex
  91 + */
  92 +#define WAIT_FOR_BBP(__dev, __reg) \
  93 +       rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  94 +#define WAIT_FOR_RFCSR(__dev, __reg) \
  95 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  96 +#define WAIT_FOR_RF(__dev, __reg) \
  97 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  98 +#define WAIT_FOR_MCU(__dev, __reg) \
  99 +       rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
 100 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 101 +
 102 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 103 +                               const unsigned int word, const u8 value)
 104 +{
 105 +       u32 reg;
 106 +
 107 +       mutex_lock(&rt2x00dev->csr_mutex);
 108 +
 109 +       /*
 110 +        * Wait until the BBP becomes available, afterwards we
 111 +        * can safely write the new data into the register.
 112 +        */
 113 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 114 +               reg = 0;
 115 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 116 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 117 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 118 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 119 +
 120 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 121 +       }
 122 +
 123 +       mutex_unlock(&rt2x00dev->csr_mutex);
 124 +}
 125 +
 126 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 127 +                              const unsigned int word, u8 *value)
 128 +{
 129 +       u32 reg;
 130 +
 131 +       mutex_lock(&rt2x00dev->csr_mutex);
 132 +
 133 +       /*
 134 +        * Wait until the BBP becomes available, afterwards we
 135 +        * can safely write the read request into the register.
 136 +        * After the data has been written, we wait until hardware
 137 +        * returns the correct value, if at any time the register
 138 +        * doesn't become available in time, reg will be 0xffffffff
 139 +        * which means we return 0xff to the caller.
 140 +        */
 141 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 142 +               reg = 0;
 143 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 144 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 145 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 146 +
 147 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 148 +
 149 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 150 +       }
 151 +
 152 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 153 +
 154 +       mutex_unlock(&rt2x00dev->csr_mutex);
 155 +}
 156 +
 157 +static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 158 +                                 const unsigned int word, const u8 value)
 159 +{
 160 +       u32 reg;
 161 +
 162 +       mutex_lock(&rt2x00dev->csr_mutex);
 163 +
 164 +       /*
 165 +        * Wait until the RFCSR becomes available, afterwards we
 166 +        * can safely write the new data into the register.
 167 +        */
 168 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 169 +               reg = 0;
 170 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 171 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 172 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 173 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 174 +
 175 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 176 +       }
 177 +
 178 +       mutex_unlock(&rt2x00dev->csr_mutex);
 179 +}
 180 +
 181 +static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 182 +                                const unsigned int word, u8 *value)
 183 +{
 184 +       u32 reg;
 185 +
 186 +       mutex_lock(&rt2x00dev->csr_mutex);
 187 +
 188 +       /*
 189 +        * Wait until the RFCSR becomes available, afterwards we
 190 +        * can safely write the read request into the register.
 191 +        * After the data has been written, we wait until hardware
 192 +        * returns the correct value, if at any time the register
 193 +        * doesn't become available in time, reg will be 0xffffffff
 194 +        * which means we return 0xff to the caller.
 195 +        */
 196 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 197 +               reg = 0;
 198 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 199 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 200 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 201 +
 202 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 203 +
 204 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 205 +       }
 206 +
 207 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 208 +
 209 +       mutex_unlock(&rt2x00dev->csr_mutex);
 210 +}
 211 +
 212 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 213 +                              const unsigned int word, const u32 value)
 214 +{
 215 +       u32 reg;
 216 +
 217 +       if (!word)
 218 +               return;
 219 +
 220 +       mutex_lock(&rt2x00dev->csr_mutex);
 221 +
 222 +       /*
 223 +        * Wait until the RF becomes available, afterwards we
 224 +        * can safely write the new data into the register.
 225 +        */
 226 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 227 +               reg = 0;
 228 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 229 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 230 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 231 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 232 +
 233 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 234 +               rt2x00_rf_write(rt2x00dev, word, value);
 235 +       }
 236 +
 237 +       mutex_unlock(&rt2x00dev->csr_mutex);
 238 +}
 239 +
 240 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 241 +                                 const u8 command, const u8 token,
 242 +                                 const u8 arg0, const u8 arg1)
 243 +{
 244 +       u32 reg;
 245 +
 246 +       mutex_lock(&rt2x00dev->csr_mutex);
 247 +
 248 +       /*
 249 +        * Wait until the MCU becomes available, afterwards we
 250 +        * can safely write the new data into the register.
 251 +        */
 252 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 253 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 254 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 255 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 256 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 257 +               rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 258 +
 259 +               reg = 0;
 260 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 261 +               rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 262 +       }
 263 +
 264 +       mutex_unlock(&rt2x00dev->csr_mutex);
 265 +}
 266 +
 267 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 268 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
 269 +       .owner  = THIS_MODULE,
 270 +       .csr    = {
 271 +               .read           = rt2x00usb_register_read,
 272 +               .write          = rt2x00usb_register_write,
 273 +               .flags          = RT2X00DEBUGFS_OFFSET,
 274 +               .word_base      = CSR_REG_BASE,
 275 +               .word_size      = sizeof(u32),
 276 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 277 +       },
 278 +       .eeprom = {
 279 +               .read           = rt2x00_eeprom_read,
 280 +               .write          = rt2x00_eeprom_write,
 281 +               .word_base      = EEPROM_BASE,
 282 +               .word_size      = sizeof(u16),
 283 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 284 +       },
 285 +       .bbp    = {
 286 +               .read           = rt2800usb_bbp_read,
 287 +               .write          = rt2800usb_bbp_write,
 288 +               .word_base      = BBP_BASE,
 289 +               .word_size      = sizeof(u8),
 290 +               .word_count     = BBP_SIZE / sizeof(u8),
 291 +       },
 292 +       .rf     = {
 293 +               .read           = rt2x00_rf_read,
 294 +               .write          = rt2800usb_rf_write,
 295 +               .word_base      = RF_BASE,
 296 +               .word_size      = sizeof(u32),
 297 +               .word_count     = RF_SIZE / sizeof(u32),
 298 +       },
 299 +};
 300 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 301 +
 302 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 303 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 304 +{
 305 +       u32 reg;
 306 +
 307 +       rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 308 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 309 +}
 310 +#else
 311 +#define rt2800usb_rfkill_poll  NULL
 312 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 313 +
 314 +#ifdef CONFIG_RT2X00_LIB_LEDS
 315 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 316 +                                    enum led_brightness brightness)
 317 +{
 318 +       struct rt2x00_led *led =
 319 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 320 +       unsigned int enabled = brightness != LED_OFF;
 321 +       unsigned int bg_mode =
 322 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 323 +       unsigned int polarity =
 324 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 325 +                                  EEPROM_FREQ_LED_POLARITY);
 326 +       unsigned int ledmode =
 327 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 328 +                                  EEPROM_FREQ_LED_MODE);
 329 +
 330 +       if (led->type == LED_TYPE_RADIO) {
 331 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 332 +                                     enabled ? 0x20 : 0);
 333 +       } else if (led->type == LED_TYPE_ASSOC) {
 334 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 335 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 336 +       } else if (led->type == LED_TYPE_QUALITY) {
 337 +               /*
 338 +                * The brightness is divided into 6 levels (0 - 5),
 339 +                * The specs tell us the following levels:
 340 +                *      0, 1 ,3, 7, 15, 31
 341 +                * to determine the level in a simple way we can simply
 342 +                * work with bitshifting:
 343 +                *      (1 << level) - 1
 344 +                */
 345 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 346 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 347 +                                     polarity);
 348 +       }
 349 +}
 350 +
 351 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 352 +                              unsigned long *delay_on,
 353 +                              unsigned long *delay_off)
 354 +{
 355 +       struct rt2x00_led *led =
 356 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 357 +       u32 reg;
 358 +
 359 +       rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
 360 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 361 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 362 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 363 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 364 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 365 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 366 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 367 +       rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
 368 +
 369 +       return 0;
 370 +}
 371 +
 372 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 373 +                              struct rt2x00_led *led,
 374 +                              enum led_type type)
 375 +{
 376 +       led->rt2x00dev = rt2x00dev;
 377 +       led->type = type;
 378 +       led->led_dev.brightness_set = rt2800usb_brightness_set;
 379 +       led->led_dev.blink_set = rt2800usb_blink_set;
 380 +       led->flags = LED_INITIALIZED;
 381 +}
 382 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 383 +
 384 +/*
 385 + * Configuration handlers.
 386 + */
 387 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 388 +                                      struct rt2x00lib_crypto *crypto,
 389 +                                      struct ieee80211_key_conf *key)
 390 +{
 391 +       struct mac_wcid_entry wcid_entry;
 392 +       struct mac_iveiv_entry iveiv_entry;
 393 +       u32 offset;
 394 +       u32 reg;
 395 +
 396 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
 397 +
 398 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 399 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 400 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 401 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
 402 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 403 +                          (crypto->cmd == SET_KEY) * crypto->bssidx);
 404 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 405 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 406 +
 407 +       offset = MAC_IVEIV_ENTRY(crypto->aid);
 408 +
 409 +       memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 410 +       if ((crypto->cipher == CIPHER_TKIP) ||
 411 +           (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 412 +           (crypto->cipher == CIPHER_AES))
 413 +               iveiv_entry.iv[3] |= 0x20;
 414 +       iveiv_entry.iv[3] |= key->keyidx << 6;
 415 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 416 +                                     &iveiv_entry, sizeof(iveiv_entry));
 417 +
 418 +       offset = MAC_WCID_ENTRY(crypto->aid);
 419 +
 420 +       memset(&wcid_entry, 0, sizeof(wcid_entry));
 421 +       if (crypto->cmd == SET_KEY)
 422 +               memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 423 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 424 +                                     &wcid_entry, sizeof(wcid_entry));
 425 +}
 426 +
 427 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 428 +                                      struct rt2x00lib_crypto *crypto,
 429 +                                      struct ieee80211_key_conf *key)
 430 +{
 431 +       struct hw_key_entry key_entry;
 432 +       struct rt2x00_field32 field;
 433 +       int timeout;
 434 +       u32 offset;
 435 +       u32 reg;
 436 +
 437 +       if (crypto->cmd == SET_KEY) {
 438 +               key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 439 +
 440 +               memcpy(key_entry.key, crypto->key,
 441 +                      sizeof(key_entry.key));
 442 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 443 +                      sizeof(key_entry.tx_mic));
 444 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 445 +                      sizeof(key_entry.rx_mic));
 446 +
 447 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 448 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 449 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 450 +                                                   USB_VENDOR_REQUEST_OUT,
 451 +                                                   offset, &key_entry,
 452 +                                                   sizeof(key_entry),
 453 +                                                   timeout);
 454 +       }
 455 +
 456 +       /*
 457 +        * The cipher types are stored over multiple registers
 458 +        * starting with SHARED_KEY_MODE_BASE each word will have
 459 +        * 32 bits and contains the cipher types for 2 bssidx each.
 460 +        * Using the correct defines correctly will cause overhead,
 461 +        * so just calculate the correct offset.
 462 +        */
 463 +       field.bit_offset = (4 * key->keyidx);
 464 +       field.bit_mask = 0x7 << field.bit_offset;
 465 +
 466 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 467 +
 468 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 469 +       rt2x00_set_field32(&reg, field,
 470 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 471 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 472 +
 473 +       /*
 474 +        * Update WCID information
 475 +        */
 476 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 477 +
 478 +       return 0;
 479 +}
 480 +
 481 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 482 +                                        struct rt2x00lib_crypto *crypto,
 483 +                                        struct ieee80211_key_conf *key)
 484 +{
 485 +       struct hw_key_entry key_entry;
 486 +       int timeout;
 487 +       u32 offset;
 488 +
 489 +       if (crypto->cmd == SET_KEY) {
 490 +               /*
 491 +                * 1 pairwise key is possible per AID, this means that the AID
 492 +                * equals our hw_key_idx.
 493 +                */
 494 +               key->hw_key_idx = crypto->aid;
 495 +
 496 +               memcpy(key_entry.key, crypto->key,
 497 +                      sizeof(key_entry.key));
 498 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 499 +                      sizeof(key_entry.tx_mic));
 500 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 501 +                      sizeof(key_entry.rx_mic));
 502 +
 503 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 504 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 505 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 506 +                                                   USB_VENDOR_REQUEST_OUT,
 507 +                                                   offset, &key_entry,
 508 +                                                   sizeof(key_entry),
 509 +                                                   timeout);
 510 +       }
 511 +
 512 +       /*
 513 +        * Update WCID information
 514 +        */
 515 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 516 +
 517 +       return 0;
 518 +}
 519 +
 520 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 521 +                                   const unsigned int filter_flags)
 522 +{
 523 +       u32 reg;
 524 +
 525 +       /*
 526 +        * Start configuration steps.
 527 +        * Note that the version error will always be dropped
 528 +        * and broadcast frames will always be accepted since
 529 +        * there is no filter for it at this time.
 530 +        */
 531 +       rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 532 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 533 +                          !(filter_flags & FIF_FCSFAIL));
 534 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 535 +                          !(filter_flags & FIF_PLCPFAIL));
 536 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 537 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 538 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 539 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 540 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 541 +                          !(filter_flags & FIF_ALLMULTI));
 542 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 543 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 544 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 545 +                          !(filter_flags & FIF_CONTROL));
 546 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 547 +                          !(filter_flags & FIF_CONTROL));
 548 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 549 +                          !(filter_flags & FIF_CONTROL));
 550 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 551 +                          !(filter_flags & FIF_CONTROL));
 552 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 553 +                          !(filter_flags & FIF_CONTROL));
 554 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 555 +                          !(filter_flags & FIF_CONTROL));
 556 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 557 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 558 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 559 +                          !(filter_flags & FIF_CONTROL));
 560 +       rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 561 +}
 562 +
 563 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 564 +                                 struct rt2x00_intf *intf,
 565 +                                 struct rt2x00intf_conf *conf,
 566 +                                 const unsigned int flags)
 567 +{
 568 +       unsigned int beacon_base;
 569 +       u32 reg;
 570 +
 571 +       if (flags & CONFIG_UPDATE_TYPE) {
 572 +               /*
 573 +                * Clear current synchronisation setup.
 574 +                * For the Beacon base registers we only need to clear
 575 +                * the first byte since that byte contains the VALID and OWNER
 576 +                * bits which (when set to 0) will invalidate the entire beacon.
 577 +                */
 578 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 579 +               rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 580 +
 581 +               /*
 582 +                * Enable synchronisation.
 583 +                */
 584 +               rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 585 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 586 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 587 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 588 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 589 +       }
 590 +
 591 +       if (flags & CONFIG_UPDATE_MAC) {
 592 +               reg = le32_to_cpu(conf->mac[1]);
 593 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 594 +               conf->mac[1] = cpu_to_le32(reg);
 595 +
 596 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 597 +                                             conf->mac, sizeof(conf->mac));
 598 +       }
 599 +
 600 +       if (flags & CONFIG_UPDATE_BSSID) {
 601 +               reg = le32_to_cpu(conf->bssid[1]);
 602 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 603 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 604 +               conf->bssid[1] = cpu_to_le32(reg);
 605 +
 606 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 607 +                                             conf->bssid, sizeof(conf->bssid));
 608 +       }
 609 +}
 610 +
 611 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 612 +                                struct rt2x00lib_erp *erp)
 613 +{
 614 +       u32 reg;
 615 +
 616 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 617 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 618 +                          DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
 619 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 620 +
 621 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 622 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 623 +                          !!erp->short_preamble);
 624 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 625 +                          !!erp->short_preamble);
 626 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 627 +
 628 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 629 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 630 +                          erp->cts_protection ? 2 : 0);
 631 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 632 +
 633 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 634 +                                erp->basic_rates);
 635 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 636 +
 637 +       rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 638 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 639 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 640 +       rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 641 +
 642 +       rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 643 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 644 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 645 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 646 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 647 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 648 +       rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 649 +}
 650 +
 651 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 652 +                                struct antenna_setup *ant)
 653 +{
 654 +       u16 eeprom;
 655 +       u8 r1;
 656 +       u8 r3;
 657 +
 658 +       /*
 659 +        * FIXME: Use requested antenna configuration.
 660 +        */
 661 +
 662 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 663 +
 664 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 665 +       rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 666 +
 667 +       /*
 668 +        * Configure the TX antenna.
 669 +        */
 670 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 671 +       case 1:
 672 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 673 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 674 +               break;
 675 +       case 2:
 676 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
 677 +               break;
 678 +       case 3:
 679 +               /* Do nothing */
 680 +               break;
 681 +       }
 682 +
 683 +       /*
 684 +        * Configure the RX antenna.
 685 +        */
 686 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 687 +       case 1:
 688 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 689 +               break;
 690 +       case 2:
 691 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 692 +               break;
 693 +       case 3:
 694 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 695 +               break;
 696 +       }
 697 +
 698 +       rt2800usb_bbp_write(rt2x00dev, 3, r3);
 699 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 700 +}
 701 +
 702 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 703 +                                     struct rt2x00lib_conf *libconf)
 704 +{
 705 +       u16 eeprom;
 706 +       short lna_gain;
 707 +
 708 +       if (libconf->rf.channel <= 14) {
 709 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 710 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 711 +       } else if (libconf->rf.channel <= 64) {
 712 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 713 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 714 +       } else if (libconf->rf.channel <= 128) {
 715 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 716 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 717 +       } else {
 718 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 719 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 720 +       }
 721 +
 722 +       rt2x00dev->lna_gain = lna_gain;
 723 +}
 724 +
 725 +static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 726 +                                         struct rf_channel *rf,
 727 +                                         struct channel_info *info)
 728 +{
 729 +       u16 eeprom;
 730 +
 731 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 732 +
 733 +       /*
 734 +        * Determine antenna settings from EEPROM
 735 +        */
 736 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 737 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
 738 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 739 +
 740 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 741 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 742 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 743 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 744 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 745 +
 746 +       if (rf->channel > 14) {
 747 +               /*
 748 +                * When TX power is below 0, we should increase it by 7 to
 749 +                * make it a positive value (Minumum value is -7).
 750 +                * However this means that values between 0 and 7 have
 751 +                * double meaning, and we should set a 7DBm boost flag.
 752 +                */
 753 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 754 +                                  (info->tx_power1 >= 0));
 755 +
 756 +               if (info->tx_power1 < 0)
 757 +                       info->tx_power1 += 7;
 758 +
 759 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 760 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 761 +
 762 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 763 +                                  (info->tx_power2 >= 0));
 764 +
 765 +               if (info->tx_power2 < 0)
 766 +                       info->tx_power2 += 7;
 767 +
 768 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 769 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 770 +       } else {
 771 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 772 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 773 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 774 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 775 +       }
 776 +
 777 +       rt2x00_set_field32(&rf->rf4, RF4_BW40,
 778 +                          test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
 779 +
 780 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 781 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 782 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 783 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 784 +
 785 +       udelay(200);
 786 +
 787 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 788 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 789 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 790 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 791 +
 792 +       udelay(200);
 793 +
 794 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 795 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 796 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 797 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 798 +}
 799 +
 800 +static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 801 +                                         struct rf_channel *rf,
 802 +                                         struct channel_info *info)
 803 +{
 804 +       u8 rfcsr;
 805 +
 806 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 807 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 808 +
 809 +       rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 810 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 811 +       rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 812 +
 813 +       rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 814 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 815 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 816 +       rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 817 +
 818 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 819 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 820 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 821 +
 822 +       if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 823 +               rt2800usb_rfcsr_write(rt2x00dev, 24, rt2x00dev->calibration_bw40);
 824 +       else
 825 +               rt2800usb_rfcsr_write(rt2x00dev, 24, rt2x00dev->calibration_bw20);
 826 +
 827 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 828 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 829 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 830 +}
 831 +
 832 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 833 +                                    struct rf_channel *rf,
 834 +                                    struct channel_info *info)
 835 +{
 836 +       u32 reg;
 837 +       unsigned int tx_pin;
 838 +       u16 eeprom;
 839 +
 840 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 841 +               rt2800usb_config_channel_rt2x(rt2x00dev, rf, info);
 842 +       else
 843 +               rt2800usb_config_channel_rt3x(rt2x00dev, rf, info);
 844 +
 845 +       tx_pin = 0;
 846 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 847 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 848 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 849 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 850 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 851 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 852 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 853 +
 854 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 855 +
 856 +       /* Turn off unused PA or LNA when only 1T or 1R */
 857 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
 858 +
 859 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
 860 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
 861 +       }
 862 +
 863 +       /* Turn off unused PA or LNA when only 1T or 1R */
 864 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 865 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
 866 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
 867 +       }
 868 +
 869 +       if (rf->channel > 14)
 870 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
 871 +       else
 872 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 873 +
 874 +       /*
 875 +        * Change BBP settings
 876 +        */
 877 +       rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 878 +       rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 879 +       rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 880 +       rt2800usb_bbp_write(rt2x00dev, 86, 0);
 881 +
 882 +       if (rf->channel <= 14) {
 883 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 884 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 885 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 886 +               } else {
 887 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 888 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 889 +               }
 890 +
 891 +               rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 892 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
 893 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
 894 +               rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 895 +       } else {
 896 +               rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 897 +
 898 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 899 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 900 +               else
 901 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 902 +
 903 +               rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 904 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
 905 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
 906 +               rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 907 +       }
 908 +
 909 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 910 +
 911 +       msleep(1);
 912 +}
 913 +
 914 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 915 +                                    const int txpower)
 916 +{
 917 +       u32 reg;
 918 +       u32 value = TXPOWER_G_TO_DEV(txpower);
 919 +       u8 r1;
 920 +
 921 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 922 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 923 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 924 +
 925 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 926 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 927 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 928 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 929 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 930 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 931 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 932 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 933 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 934 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 935 +
 936 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 937 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 938 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 939 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 940 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 941 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 942 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 943 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 944 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 945 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 946 +
 947 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 948 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 949 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 950 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 951 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 952 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 953 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 954 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 955 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 956 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 957 +
 958 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 959 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 960 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 961 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 962 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 963 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 964 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 965 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 966 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 967 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 968 +
 969 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 970 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 971 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 972 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 973 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 974 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 975 +}
 976 +
 977 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 978 +                                        struct rt2x00lib_conf *libconf)
 979 +{
 980 +       u32 reg;
 981 +
 982 +       rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 983 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 984 +                          libconf->conf->short_frame_max_tx_count);
 985 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 986 +                          libconf->conf->long_frame_max_tx_count);
 987 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 988 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 989 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 990 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 991 +       rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
 992 +}
 993 +
 994 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
 995 +                                     struct rt2x00lib_conf *libconf)
 996 +{
 997 +       u32 reg;
 998 +
 999 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1000 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1001 +                          libconf->conf->beacon_int * 16);
1002 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1003 +}
1004 +
1005 +static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
1006 +                               struct rt2x00lib_conf *libconf)
1007 +{
1008 +       enum dev_state state =
1009 +           (libconf->conf->flags & IEEE80211_CONF_PS) ?
1010 +               STATE_SLEEP : STATE_AWAKE;
1011 +       u32 reg;
1012 +
1013 +       if (state == STATE_SLEEP) {
1014 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1015 +
1016 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1017 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1018 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1019 +                                  libconf->conf->listen_interval - 1);
1020 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1021 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1022 +
1023 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
1024 +       } else {
1025 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1026 +
1027 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1028 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1029 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1030 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1031 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1032 +       }
1033 +}
1034 +
1035 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1036 +                            struct rt2x00lib_conf *libconf,
1037 +                            const unsigned int flags)
1038 +{
1039 +       /* Always recalculate LNA gain before changing configuration */
1040 +       rt2800usb_config_lna_gain(rt2x00dev, libconf);
1041 +
1042 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1043 +               rt2800usb_config_channel(rt2x00dev, &libconf->rf,
1044 +                                        &libconf->channel);
1045 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1046 +               rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1047 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1048 +               rt2800usb_config_retry_limit(rt2x00dev, libconf);
1049 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1050 +               rt2800usb_config_duration(rt2x00dev, libconf);
1051 +       if (flags & IEEE80211_CONF_CHANGE_PS)
1052 +               rt2800usb_config_ps(rt2x00dev, libconf);
1053 +}
1054 +
1055 +/*
1056 + * Link tuning
1057 + */
1058 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1059 +                                struct link_qual *qual)
1060 +{
1061 +       u32 reg;
1062 +
1063 +       /*
1064 +        * Update FCS error count from register.
1065 +        */
1066 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1067 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1068 +}
1069 +
1070 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1071 +{
1072 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1073 +               if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1074 +                       return 0x1c + (2 * rt2x00dev->lna_gain);
1075 +               else
1076 +                       return 0x2e + rt2x00dev->lna_gain;
1077 +       }
1078 +
1079 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1080 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1081 +       else
1082 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1083 +}
1084 +
1085 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1086 +                                    struct link_qual *qual, u8 vgc_level)
1087 +{
1088 +       if (qual->vgc_level != vgc_level) {
1089 +               rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1090 +               qual->vgc_level = vgc_level;
1091 +               qual->vgc_level_reg = vgc_level;
1092 +       }
1093 +}
1094 +
1095 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1096 +                                 struct link_qual *qual)
1097 +{
1098 +       rt2800usb_set_vgc(rt2x00dev, qual,
1099 +                         rt2800usb_get_default_vgc(rt2x00dev));
1100 +}
1101 +
1102 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1103 +                                struct link_qual *qual, const u32 count)
1104 +{
1105 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1106 +               return;
1107 +
1108 +       /*
1109 +        * When RSSI is better then -80 increase VGC level with 0x10
1110 +        */
1111 +       rt2800usb_set_vgc(rt2x00dev, qual,
1112 +                         rt2800usb_get_default_vgc(rt2x00dev) +
1113 +                         ((qual->rssi > -80) * 0x10));
1114 +}
1115 +
1116 +/*
1117 + * Firmware functions
1118 + */
1119 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1120 +{
1121 +       return FIRMWARE_RT2870;
1122 +}
1123 +
1124 +static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1125 +{
1126 +       u16 fw_crc;
1127 +       u16 crc;
1128 +
1129 +       /*
1130 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1131 +        * this means that we should never pass those 2 bytes to the crc
1132 +        * algorithm.
1133 +        */
1134 +       fw_crc = (data[len - 2] << 8 | data[len - 1]);
1135 +
1136 +       /*
1137 +        * Use the crc ccitt algorithm.
1138 +        * This will return the same value as the legacy driver which
1139 +        * used bit ordering reversion on the both the firmware bytes
1140 +        * before input input as well as on the final output.
1141 +        * Obviously using crc ccitt directly is much more efficient.
1142 +        */
1143 +       crc = crc_ccitt(~0, data, len - 2);
1144 +
1145 +       /*
1146 +        * There is a small difference between the crc-itu-t + bitrev and
1147 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1148 +        * will be swapped, use swab16 to convert the crc to the correct
1149 +        * value.
1150 +        */
1151 +       crc = swab16(crc);
1152 +
1153 +       return fw_crc == crc;
1154 +}
1155 +
1156 +static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1157 +                                   const u8 *data, const size_t len)
1158 +{
1159 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1160 +       size_t offset = 0;
1161 +
1162 +       /*
1163 +        * Firmware files:
1164 +        * There are 2 variations of the rt2870 firmware.
1165 +        * a) size: 4kb
1166 +        * b) size: 8kb
1167 +        * Note that (b) contains 2 seperate firmware blobs of 4k
1168 +        * within the file. The first blob is the same firmware as (a),
1169 +        * but the second blob is for the additional chipsets.
1170 +        */
1171 +       if (len != 4096 && len != 8192)
1172 +               return FW_BAD_LENGTH;
1173 +
1174 +       /*
1175 +        * Check if we need the upper 4kb firmware data or not.
1176 +        */
1177 +       if ((len == 4096) &&
1178 +           (chipset != 0x2860) &&
1179 +           (chipset != 0x2872) &&
1180 +           (chipset != 0x3070))
1181 +               return FW_BAD_VERSION;
1182 +
1183 +       /*
1184 +        * 8kb firmware files must be checked as if it were
1185 +        * 2 seperate firmware files.
1186 +        */
1187 +       while (offset < len) {
1188 +               if (!rt2800usb_check_crc(data + offset, 4096))
1189 +                       return FW_BAD_CRC;
1190 +
1191 +               offset += 4096;
1192 +       }
1193 +
1194 +       return FW_OK;
1195 +}
1196 +
1197 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1198 +                                  const u8 *data, const size_t len)
1199 +{
1200 +       unsigned int i;
1201 +       int status;
1202 +       u32 reg;
1203 +       u32 offset;
1204 +       u32 length;
1205 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1206 +
1207 +       /*
1208 +        * Check which section of the firmware we need.
1209 +        */
1210 +       if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1211 +               offset = 0;
1212 +               length = 4096;
1213 +       } else {
1214 +               offset = 4096;
1215 +               length = 4096;
1216 +       }
1217 +
1218 +       /*
1219 +        * Wait for stable hardware.
1220 +        */
1221 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1222 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1223 +               if (reg && reg != ~0)
1224 +                       break;
1225 +               msleep(1);
1226 +       }
1227 +
1228 +       if (i == REGISTER_BUSY_COUNT) {
1229 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1230 +               return -EBUSY;
1231 +       }
1232 +
1233 +       /*
1234 +        * Write firmware to device.
1235 +        */
1236 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1237 +                                           USB_VENDOR_REQUEST_OUT,
1238 +                                           FIRMWARE_IMAGE_BASE,
1239 +                                           data + offset, length,
1240 +                                           REGISTER_TIMEOUT32(length));
1241 +
1242 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1243 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1244 +
1245 +       /*
1246 +        * Send firmware request to device to load firmware,
1247 +        * we need to specify a long timeout time.
1248 +        */
1249 +       status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1250 +                                            0, USB_MODE_FIRMWARE,
1251 +                                            REGISTER_TIMEOUT_FIRMWARE);
1252 +       if (status < 0) {
1253 +               ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1254 +               return status;
1255 +       }
1256 +
1257 +       /*
1258 +        * Wait for device to stabilize.
1259 +        */
1260 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1261 +               rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1262 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1263 +                       break;
1264 +               msleep(1);
1265 +       }
1266 +
1267 +       if (i == REGISTER_BUSY_COUNT) {
1268 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1269 +               return -EBUSY;
1270 +       }
1271 +
1272 +       /*
1273 +        * Initialize firmware.
1274 +        */
1275 +       rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1276 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1277 +       msleep(1);
1278 +
1279 +       return 0;
1280 +}
1281 +
1282 +/*
1283 + * Initialization functions.
1284 + */
1285 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1286 +{
1287 +       u32 reg;
1288 +       unsigned int i;
1289 +
1290 +       /*
1291 +        * Wait untill BBP and RF are ready.
1292 +        */
1293 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1294 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1295 +               if (reg && reg != ~0)
1296 +                       break;
1297 +               msleep(1);
1298 +       }
1299 +
1300 +       if (i == REGISTER_BUSY_COUNT) {
1301 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1302 +               return -EBUSY;
1303 +       }
1304 +
1305 +       rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1306 +       rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1307 +
1308 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1309 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1310 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1311 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1312 +
1313 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1314 +
1315 +       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1316 +                                   USB_MODE_RESET, REGISTER_TIMEOUT);
1317 +
1318 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1319 +
1320 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1321 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1322 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1323 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1324 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1325 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1326 +
1327 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1328 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1329 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1330 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1331 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1332 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1333 +
1334 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1335 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1336 +
1337 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1338 +
1339 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1340 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1341 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1342 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1343 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1344 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1345 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1346 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1347 +
1348 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1349 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1350 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1351 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1352 +       } else {
1353 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1354 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1355 +       }
1356 +
1357 +       rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1358 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1359 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1360 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1361 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1362 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1363 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1364 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1365 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1366 +       rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1367 +
1368 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1369 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1370 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1371 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1372 +
1373 +       rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1374 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1375 +       if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1376 +           rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1377 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1378 +       else
1379 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1380 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1381 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1382 +       rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1383 +
1384 +       rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1385 +
1386 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1387 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1388 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1389 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1390 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1391 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1392 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1393 +
1394 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1395 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1396 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1397 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1398 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1399 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1400 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1401 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1402 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1403 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1404 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1405 +
1406 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1407 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1408 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1409 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1410 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1411 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1412 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1413 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1414 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1415 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1416 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1417 +
1418 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1419 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1420 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1421 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1422 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1423 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1424 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1425 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1426 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1427 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1428 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1429 +
1430 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1431 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1432 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1433 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1434 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1435 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1436 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1437 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1438 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1439 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1440 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1441 +
1442 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1443 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1444 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1445 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1446 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1447 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1448 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1449 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1450 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1451 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1452 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1453 +
1454 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1455 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1456 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1457 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1458 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1459 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1460 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1461 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1462 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1463 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1464 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1465 +
1466 +       rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1467 +
1468 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1469 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1470 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1471 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1472 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1473 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1474 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1475 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1476 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1477 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1478 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1479 +
1480 +       rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1481 +       rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1482 +
1483 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1484 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1485 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1486 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1487 +
1488 +       rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1489 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1490 +
1491 +       /*
1492 +        * ASIC will keep garbage value after boot, clear encryption keys.
1493 +        */
1494 +       for (i = 0; i < 254; i++) {
1495 +               u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1496 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1497 +                                             wcid, sizeof(wcid));
1498 +       }
1499 +
1500 +       for (i = 0; i < 4; i++)
1501 +               rt2x00usb_register_write(rt2x00dev,
1502 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1503 +
1504 +       for (i = 0; i < 256; i++)
1505 +               rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1506 +
1507 +       /*
1508 +        * Clear all beacons
1509 +        * For the Beacon base registers we only need to clear
1510 +        * the first byte since that byte contains the VALID and OWNER
1511 +        * bits which (when set to 0) will invalidate the entire beacon.
1512 +        */
1513 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1514 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1515 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1516 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1517 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1518 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1519 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1520 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1521 +
1522 +       rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1523 +       rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1524 +       rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1525 +
1526 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1527 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1528 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1529 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1530 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1531 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1532 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1533 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1534 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1535 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1536 +
1537 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1538 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1539 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1540 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1541 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1542 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1543 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1544 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1545 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1546 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1547 +
1548 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1549 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1550 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1551 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1552 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1553 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1554 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1555 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1556 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1557 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1558 +
1559 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1560 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1561 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1562 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1563 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1564 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1565 +
1566 +       /*
1567 +        * We must clear the error counters.
1568 +        * These registers are cleared on read,
1569 +        * so we may pass a useless variable to store the value.
1570 +        */
1571 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1572 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1573 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1574 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1575 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1576 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1577 +
1578 +       return 0;
1579 +}
1580 +
1581 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1582 +{
1583 +       unsigned int i;
1584 +       u32 reg;
1585 +
1586 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1587 +               rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1588 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1589 +                       return 0;
1590 +
1591 +               udelay(REGISTER_BUSY_DELAY);
1592 +       }
1593 +
1594 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1595 +       return -EACCES;
1596 +}
1597 +
1598 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1599 +{
1600 +       unsigned int i;
1601 +       u8 value;
1602 +
1603 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1604 +               rt2800usb_bbp_read(rt2x00dev, 0, &value);
1605 +               if ((value != 0xff) && (value != 0x00))
1606 +                       return 0;
1607 +               udelay(REGISTER_BUSY_DELAY);
1608 +       }
1609 +
1610 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1611 +       return -EACCES;
1612 +}
1613 +
1614 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1615 +{
1616 +       unsigned int i;
1617 +       u16 eeprom;
1618 +       u8 reg_id;
1619 +       u8 value;
1620 +
1621 +       if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1622 +                    rt2800usb_wait_bbp_ready(rt2x00dev)))
1623 +               return -EACCES;
1624 +
1625 +       rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1626 +       rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1627 +       rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1628 +       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1629 +       rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1630 +       rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1631 +       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1632 +       rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1633 +       rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1634 +       rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1635 +       rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1636 +       rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1637 +       rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1638 +       rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1639 +
1640 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1641 +               rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1642 +               rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1643 +       }
1644 +
1645 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1646 +               rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1647 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1648 +               rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1649 +       }
1650 +
1651 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1652 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1653 +
1654 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1655 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1656 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1657 +                       rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1658 +               }
1659 +       }
1660 +
1661 +       return 0;
1662 +}
1663 +
1664 +static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1665 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
1666 +{
1667 +       unsigned int i;
1668 +       u8 bbp;
1669 +       u8 rfcsr;
1670 +       u8 passband;
1671 +       u8 stopband;
1672 +       u8 overtuned = 0;
1673 +
1674 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1675 +
1676 +       if (bw40) {
1677 +               rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1678 +               rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0x10);
1679 +               rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1680 +       }
1681 +
1682 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1683 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1684 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1685 +
1686 +       /*
1687 +        * Set power & frequency of passband test tone
1688 +        */
1689 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1690 +
1691 +       for (i = 0; i < 100; i++) {
1692 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1693 +               msleep(1);
1694 +
1695 +               rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1696 +               if (passband)
1697 +                       break;
1698 +       }
1699 +
1700 +       /*
1701 +        * Set power & frequency of stopband test tone
1702 +        */
1703 +       rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1704 +
1705 +       for (i = 0; i < 100; i++) {
1706 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1707 +               msleep(1);
1708 +
1709 +               rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1710 +
1711 +               if ((passband - stopband) <= filter_target) {
1712 +                       rfcsr24++;
1713 +                       overtuned += ((passband - stopband) == filter_target);
1714 +               } else
1715 +                       break;
1716 +
1717 +               rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1718 +       }
1719 +
1720 +       rfcsr24 -= !!overtuned;
1721 +
1722 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1723 +       return rfcsr24;
1724 +}
1725 +
1726 +static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1727 +{
1728 +       u8 rfcsr;
1729 +       u8 bbp;
1730 +
1731 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1732 +               return 0;
1733 +
1734 +       /*
1735 +        * Init RF calibration.
1736 +        */
1737 +       rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1738 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1739 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1740 +       msleep(1);
1741 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1742 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1743 +
1744 +       rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1745 +       rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1746 +       rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1747 +       rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1748 +       rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1749 +       rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1750 +       rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1751 +       rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1752 +       rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1753 +       rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1754 +       rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1755 +       rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1756 +       rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1757 +       rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1758 +       rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1759 +       rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1760 +       rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1761 +       rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1762 +       rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1763 +       rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1764 +
1765 +       /*
1766 +        * Set RX Filter calibration for 20MHz and 40MHz
1767 +        */
1768 +       rt2x00dev->calibration_bw20 =
1769 +           rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1770 +       rt2x00dev->calibration_bw40 =
1771 +           rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1772 +
1773 +       /*
1774 +        * Set back to initial state
1775 +        */
1776 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1777 +
1778 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1779 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1780 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1781 +
1782 +       /*
1783 +        * set BBP back to BW20
1784 +        */
1785 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1786 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1787 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1788 +
1789 +       return 0;
1790 +}
1791 +
1792 +/*
1793 + * Device state switch handlers.
1794 + */
1795 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1796 +                               enum dev_state state)
1797 +{
1798 +       u32 reg;
1799 +
1800 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1801 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1802 +                          (state == STATE_RADIO_RX_ON) ||
1803 +                          (state == STATE_RADIO_RX_ON_LINK));
1804 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1805 +}
1806 +
1807 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1808 +{
1809 +       unsigned int i;
1810 +       u32 reg;
1811 +
1812 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1813 +               rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1814 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1815 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1816 +                       return 0;
1817 +
1818 +               msleep(1);
1819 +       }
1820 +
1821 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1822 +       return -EACCES;
1823 +}
1824 +
1825 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1826 +{
1827 +       u32 reg;
1828 +       u16 word;
1829 +
1830 +       /*
1831 +        * Initialize all registers.
1832 +        */
1833 +       if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1834 +                    rt2800usb_init_registers(rt2x00dev) ||
1835 +                    rt2800usb_init_bbp(rt2x00dev) ||
1836 +                    rt2800usb_init_rfcsr(rt2x00dev)))
1837 +               return -EIO;
1838 +
1839 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1840 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1841 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1842 +
1843 +       udelay(50);
1844 +
1845 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1846 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1847 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1848 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1849 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1850 +
1851 +
1852 +       rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1853 +       rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1854 +       /* Don't use bulk in aggregation when working with USB 1.1 */
1855 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1856 +                          (rt2x00dev->rx->usb_maxpacket == 512));
1857 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1858 +       /* FIXME: Calculate this value based on Aggregation defines */
1859 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1860 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1861 +       rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1862 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1863 +
1864 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1865 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1866 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1867 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1868 +
1869 +       /*
1870 +        * Send signal to firmware during boot time.
1871 +        */
1872 +       rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1873 +
1874 +       /*
1875 +        * Initialize LED control
1876 +        */
1877 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1878 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1879 +                             word & 0xff, (word >> 8) & 0xff);
1880 +
1881 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1882 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1883 +                             word & 0xff, (word >> 8) & 0xff);
1884 +
1885 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1886 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1887 +                             word & 0xff, (word >> 8) & 0xff);
1888 +
1889 +       return 0;
1890 +}
1891 +
1892 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1893 +{
1894 +       u32 reg;
1895 +
1896 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1897 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1898 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1899 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1900 +
1901 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1902 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1903 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1904 +
1905 +       /* Wait for DMA, ignore error */
1906 +       rt2800usb_wait_wpdma_ready(rt2x00dev);
1907 +
1908 +       rt2x00usb_disable_radio(rt2x00dev);
1909 +}
1910 +
1911 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1912 +                              enum dev_state state)
1913 +{
1914 +       rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1915 +
1916 +       if (state == STATE_AWAKE)
1917 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1918 +       else
1919 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1920 +
1921 +       return 0;
1922 +}
1923 +
1924 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1925 +                                     enum dev_state state)
1926 +{
1927 +       int retval = 0;
1928 +
1929 +       switch (state) {
1930 +       case STATE_RADIO_ON:
1931 +               /*
1932 +                * Before the radio can be enabled, the device first has
1933 +                * to be woken up. After that it needs a bit of time
1934 +                * to be fully awake and the radio can be enabled.
1935 +                */
1936 +               rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1937 +               msleep(1);
1938 +               retval = rt2800usb_enable_radio(rt2x00dev);
1939 +               break;
1940 +       case STATE_RADIO_OFF:
1941 +               /*
1942 +                * After the radio has been disablee, the device should
1943 +                * be put to sleep for powersaving.
1944 +                */
1945 +               rt2800usb_disable_radio(rt2x00dev);
1946 +               rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1947 +               break;
1948 +       case STATE_RADIO_RX_ON:
1949 +       case STATE_RADIO_RX_ON_LINK:
1950 +       case STATE_RADIO_RX_OFF:
1951 +       case STATE_RADIO_RX_OFF_LINK:
1952 +               rt2800usb_toggle_rx(rt2x00dev, state);
1953 +               break;
1954 +       case STATE_RADIO_IRQ_ON:
1955 +       case STATE_RADIO_IRQ_OFF:
1956 +               /* No support, but no error either */
1957 +               break;
1958 +       case STATE_DEEP_SLEEP:
1959 +       case STATE_SLEEP:
1960 +       case STATE_STANDBY:
1961 +       case STATE_AWAKE:
1962 +               retval = rt2800usb_set_state(rt2x00dev, state);
1963 +               break;
1964 +       default:
1965 +               retval = -ENOTSUPP;
1966 +               break;
1967 +       }
1968 +
1969 +       if (unlikely(retval))
1970 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1971 +                     state, retval);
1972 +
1973 +       return retval;
1974 +}
1975 +
1976 +/*
1977 + * TX descriptor initialization
1978 + */
1979 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1980 +                                   struct sk_buff *skb,
1981 +                                   struct txentry_desc *txdesc)
1982 +{
1983 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1984 +       __le32 *txi = skbdesc->desc;
1985 +       __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1986 +       u32 word;
1987 +
1988 +       /*
1989 +        * Initialize TX Info descriptor
1990 +        */
1991 +       rt2x00_desc_read(txwi, 0, &word);
1992 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
1993 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1994 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1995 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1996 +       rt2x00_set_field32(&word, TXWI_W0_TS,
1997 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1998 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1999 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2000 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2001 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2002 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2003 +       rt2x00_set_field32(&word, TXWI_W0_BW,
2004 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2005 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2006 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2007 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2008 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2009 +       rt2x00_desc_write(txwi, 0, word);
2010 +
2011 +       rt2x00_desc_read(txwi, 1, &word);
2012 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2013 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2014 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2015 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2016 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2017 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
2018 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2019 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2020 +                          skbdesc->entry->entry_idx);
2021 +       rt2x00_desc_write(txwi, 1, word);
2022 +
2023 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
2024 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
2025 +               _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
2026 +       }
2027 +
2028 +       /*
2029 +        * Initialize TX descriptor
2030 +        */
2031 +       rt2x00_desc_read(txi, 0, &word);
2032 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2033 +                          skb->len + TXWI_DESC_SIZE);
2034 +       rt2x00_set_field32(&word, TXINFO_W0_WIV, 1);
2035 +       rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2036 +       rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2037 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2038 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2039 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2040 +       rt2x00_desc_write(txi, 0, word);
2041 +}
2042 +
2043 +/*
2044 + * TX data initialization
2045 + */
2046 +static void rt2800usb_write_beacon(struct queue_entry *entry)
2047 +{
2048 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2049 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2050 +       unsigned int beacon_base;
2051 +       u32 reg;
2052 +
2053 +       /*
2054 +        * Add the descriptor in front of the skb.
2055 +        */
2056 +       skb_push(entry->skb, entry->queue->desc_size);
2057 +       memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2058 +       skbdesc->desc = entry->skb->data;
2059 +
2060 +       /*
2061 +        * Disable beaconing while we are reloading the beacon data,
2062 +        * otherwise we might be sending out invalid data.
2063 +        */
2064 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2065 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2066 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2067 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2068 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2069 +
2070 +       /*
2071 +        * Write entire beacon with descriptor to register.
2072 +        */
2073 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2074 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2075 +                                           USB_VENDOR_REQUEST_OUT, beacon_base,
2076 +                                           entry->skb->data, entry->skb->len,
2077 +                                           REGISTER_TIMEOUT32(entry->skb->len));
2078 +
2079 +       /*
2080 +        * Clean up the beacon skb.
2081 +        */
2082 +       dev_kfree_skb(entry->skb);
2083 +       entry->skb = NULL;
2084 +}
2085 +
2086 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2087 +{
2088 +       int length;
2089 +
2090 +       /*
2091 +        * The length _must_ include 4 bytes padding,
2092 +        * it should always be multiple of 4,
2093 +        * but it must _not_ be a multiple of the USB packet size.
2094 +        */
2095 +       length = roundup(entry->skb->len + 4, 4);
2096 +       length += (4 * !(length % entry->queue->usb_maxpacket));
2097 +
2098 +       return length;
2099 +}
2100 +
2101 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2102 +                                   const enum data_queue_qid queue)
2103 +{
2104 +       u32 reg;
2105 +
2106 +       if (queue != QID_BEACON) {
2107 +               rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2108 +               return;
2109 +       }
2110 +
2111 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2112 +       if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2113 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2114 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2115 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2116 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2117 +       }
2118 +}
2119 +
2120 +/*
2121 + * RX control handlers
2122 + */
2123 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2124 +                                 struct rxdone_entry_desc *rxdesc)
2125 +{
2126 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2127 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2128 +       __le32 *rxd = (__le32 *)entry->skb->data;
2129 +       __le32 *rxwi;
2130 +       u32 rxd0;
2131 +       u32 rxwi0;
2132 +       u32 rxwi1;
2133 +       u32 rxwi2;
2134 +       u32 rxwi3;
2135 +
2136 +       /*
2137 +        * Copy descriptor to the skbdesc->desc buffer, making it safe from
2138 +        * moving of frame data in rt2x00usb.
2139 +        */
2140 +       memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2141 +       rxd = (__le32 *)skbdesc->desc;
2142 +       rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2143 +
2144 +       /*
2145 +        * It is now safe to read the descriptor on all architectures.
2146 +        */
2147 +       rt2x00_desc_read(rxd, 0, &rxd0);
2148 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2149 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2150 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2151 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2152 +
2153 +       if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2154 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2155 +
2156 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2157 +               /*
2158 +                * Unfortunately we don't know the cipher type used during
2159 +                * decryption. This prevents us from correct providing
2160 +                * correct statistics through debugfs.
2161 +                */
2162 +               rxdesc->cipher = CIPHER_NONE;
2163 +               rxdesc->cipher_status =
2164 +                   rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2165 +       }
2166 +
2167 +       if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2168 +               /*
2169 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2170 +                * decryption. Unfortunately the descriptor doesn't contain
2171 +                * any fields with the EIV/IV data either, so they can't
2172 +                * be restored by rt2x00lib.
2173 +                */
2174 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2175 +
2176 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2177 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2178 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2179 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2180 +       }
2181 +
2182 +       if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2183 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2184 +
2185 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2186 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
2187 +
2188 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2189 +               rxdesc->flags |= RX_FLAG_40MHZ;
2190 +
2191 +       /*
2192 +        * Detect RX rate, always use MCS as signal type.
2193 +        */
2194 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2195 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2196 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2197 +
2198 +       /*
2199 +        * Mask of 0x8 bit to remove the short preamble flag.
2200 +        */
2201 +       if (rxdesc->dev_flags == RATE_MODE_CCK)
2202 +               rxdesc->signal &= ~0x8;
2203 +
2204 +       rxdesc->rssi =
2205 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2206 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2207 +
2208 +       rxdesc->noise =
2209 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2210 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2211 +
2212 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2213 +
2214 +       /*
2215 +        * Remove RXWI descriptor from start of buffer.
2216 +        */
2217 +       skb_pull(entry->skb, skbdesc->desc_len);
2218 +       skb_trim(entry->skb, rxdesc->size);
2219 +}
2220 +
2221 +/*
2222 + * Device probe functions.
2223 + */
2224 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2225 +{
2226 +       u16 word;
2227 +       u8 *mac;
2228 +       u8 default_lna_gain;
2229 +
2230 +       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2231 +
2232 +       /*
2233 +        * Start validation of the data that has been read.
2234 +        */
2235 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2236 +       if (!is_valid_ether_addr(mac)) {
2237 +               DECLARE_MAC_BUF(macbuf);
2238 +
2239 +               random_ether_addr(mac);
2240 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2241 +       }
2242 +
2243 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2244 +       if (word == 0xffff) {
2245 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2246 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2247 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2248 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2249 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2250 +       }
2251 +
2252 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2253 +       if (word == 0xffff) {
2254 +               rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2255 +               rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2256 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2257 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2258 +               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2259 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2260 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2261 +               rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2262 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2263 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2264 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2265 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2266 +       }
2267 +
2268 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2269 +       if ((word & 0x00ff) == 0x00ff) {
2270 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2271 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2272 +                                  LED_MODE_TXRX_ACTIVITY);
2273 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2274 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2275 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2276 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2277 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2278 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2279 +       }
2280 +
2281 +       /*
2282 +        * During the LNA validation we are going to use
2283 +        * lna0 as correct value. Note that EEPROM_LNA
2284 +        * is never validated.
2285 +        */
2286 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2287 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2288 +
2289 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2290 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2291 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2292 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2293 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2294 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2295 +
2296 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2297 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2298 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2299 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2300 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2301 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2302 +                                  default_lna_gain);
2303 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2304 +
2305 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2306 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2307 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2308 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2309 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2310 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2311 +
2312 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2313 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2314 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2315 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2316 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2317 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2318 +                                  default_lna_gain);
2319 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2320 +
2321 +       return 0;
2322 +}
2323 +
2324 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2325 +{
2326 +       u32 reg;
2327 +       u16 value;
2328 +       u16 eeprom;
2329 +
2330 +       /*
2331 +        * Read EEPROM word for configuration.
2332 +        */
2333 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2334 +
2335 +       /*
2336 +        * Identify RF chipset.
2337 +        */
2338 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2339 +       rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2340 +       rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2341 +
2342 +       /*
2343 +        * The check for rt2860 is not a typo, some rt2870 hardware
2344 +        * identifies itself as rt2860 in the CSR register.
2345 +        */
2346 +       if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2347 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
2348 +               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2349 +               return -ENODEV;
2350 +       }
2351 +
2352 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2353 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2354 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2355 +           !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2356 +           !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2357 +           !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2358 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2359 +               return -ENODEV;
2360 +       }
2361 +
2362 +       /*
2363 +        * Read frequency offset and RF programming sequence.
2364 +        */
2365 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2366 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2367 +
2368 +       /*
2369 +        * Read external LNA informations.
2370 +        */
2371 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2372 +
2373 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2374 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2375 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2376 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2377 +
2378 +       /*
2379 +        * Detect if this device has an hardware controlled radio.
2380 +        */
2381 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2382 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2383 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2384 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2385 +
2386 +       /*
2387 +        * Store led settings, for correct led behaviour.
2388 +        */
2389 +#ifdef CONFIG_RT2X00_LIB_LEDS
2390 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2391 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2392 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2393 +
2394 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2395 +                          &rt2x00dev->led_mcu_reg);
2396 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2397 +
2398 +       return 0;
2399 +}
2400 +
2401 +/*
2402 + * RF value list for rt2870
2403 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2404 + */
2405 +static const struct rf_channel rf_vals[] = {
2406 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2407 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2408 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2409 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2410 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2411 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2412 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2413 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2414 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2415 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2416 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2417 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2418 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2419 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2420 +
2421 +       /* 802.11 UNI / HyperLan 2 */
2422 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2423 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2424 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2425 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2426 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2427 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2428 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2429 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2430 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2431 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2432 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2433 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2434 +
2435 +       /* 802.11 HyperLan 2 */
2436 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2437 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2438 +       { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2439 +       { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2440 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2441 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2442 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2443 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2444 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2445 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2446 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2447 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2448 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2449 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2450 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2451 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2452 +
2453 +       /* 802.11 UNII */
2454 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2455 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2456 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2457 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2458 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2459 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2460 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2461 +
2462 +       /* 802.11 Japan */
2463 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2464 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2465 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2466 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2467 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2468 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2469 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2470 +};
2471 +
2472 +/*
2473 + * RF value list for rt3070
2474 + * Supports: 2.4 GHz
2475 + */
2476 +static const struct rf_channel rf_vals_3070[] = {
2477 +       {1,  241, 2, 2 },
2478 +       {2,  241, 2, 7 },
2479 +       {3,  242, 2, 2 },
2480 +       {4,  242, 2, 7 },
2481 +       {5,  243, 2, 2 },
2482 +       {6,  243, 2, 7 },
2483 +       {7,  244, 2, 2 },
2484 +       {8,  244, 2, 7 },
2485 +       {9,  245, 2, 2 },
2486 +       {10, 245, 2, 7 },
2487 +       {11, 246, 2, 2 },
2488 +       {12, 246, 2, 7 },
2489 +       {13, 247, 2, 2 },
2490 +       {14, 248, 2, 4 },
2491 +};
2492 +
2493 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2494 +{
2495 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2496 +       struct channel_info *info;
2497 +       char *tx_power1;
2498 +       char *tx_power2;
2499 +       unsigned int i;
2500 +
2501 +       /*
2502 +        * Initialize all hw fields.
2503 +        */
2504 +       rt2x00dev->hw->flags =
2505 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2506 +           IEEE80211_HW_SIGNAL_DBM |
2507 +           IEEE80211_HW_SUPPORTS_PS |
2508 +           IEEE80211_HW_PS_NULLFUNC_STACK;
2509 +       rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2510 +
2511 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2512 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2513 +                               rt2x00_eeprom_addr(rt2x00dev,
2514 +                                                  EEPROM_MAC_ADDR_0));
2515 +
2516 +       /*
2517 +        * Initialize HT information.
2518 +        */
2519 +       spec->ht.ht_supported = true;
2520 +       spec->ht.cap =
2521 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2522 +           IEEE80211_HT_CAP_GRN_FLD |
2523 +           IEEE80211_HT_CAP_SGI_20 |
2524 +           IEEE80211_HT_CAP_SGI_40 |
2525 +           IEEE80211_HT_CAP_TX_STBC |
2526 +           IEEE80211_HT_CAP_RX_STBC |
2527 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2528 +       spec->ht.ampdu_factor = 3;
2529 +       spec->ht.ampdu_density = 4;
2530 +       spec->ht.mcs.rx_mask[0] = 0xff;
2531 +       spec->ht.mcs.rx_mask[1] = 0xff;
2532 +       spec->ht.mcs.tx_params =
2533 +           IEEE80211_HT_MCS_TX_DEFINED;
2534 +
2535 +       /*
2536 +        * Initialize hw_mode information.
2537 +        */
2538 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2539 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2540 +
2541 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2542 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2543 +               spec->num_channels = 14;
2544 +               spec->channels = rf_vals;
2545 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2546 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2547 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2548 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2549 +               spec->channels = rf_vals;
2550 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2551 +                  rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2552 +               spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2553 +               spec->channels = rf_vals_3070;
2554 +       }
2555 +
2556 +       /*
2557 +        * Create channel information array
2558 +        */
2559 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2560 +       if (!info)
2561 +               return -ENOMEM;
2562 +
2563 +       spec->channels_info = info;
2564 +
2565 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2566 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2567 +
2568 +       for (i = 0; i < 14; i++) {
2569 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2570 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2571 +       }
2572 +
2573 +       if (spec->num_channels > 14) {
2574 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2575 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2576 +
2577 +               for (i = 14; i < spec->num_channels; i++) {
2578 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2579 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2580 +               }
2581 +       }
2582 +
2583 +       return 0;
2584 +}
2585 +
2586 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2587 +{
2588 +       int retval;
2589 +
2590 +       /*
2591 +        * Allocate eeprom data.
2592 +        */
2593 +       retval = rt2800usb_validate_eeprom(rt2x00dev);
2594 +       if (retval)
2595 +               return retval;
2596 +
2597 +       retval = rt2800usb_init_eeprom(rt2x00dev);
2598 +       if (retval)
2599 +               return retval;
2600 +
2601 +       /*
2602 +        * Initialize hw specifications.
2603 +        */
2604 +       retval = rt2800usb_probe_hw_mode(rt2x00dev);
2605 +       if (retval)
2606 +               return retval;
2607 +
2608 +       /*
2609 +        * This device requires firmware.
2610 +        */
2611 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2612 +       __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2613 +       if (!modparam_nohwcrypt)
2614 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2615 +
2616 +       /*
2617 +        * Set the rssi offset.
2618 +        */
2619 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2620 +
2621 +       return 0;
2622 +}
2623 +
2624 +/*
2625 + * IEEE80211 stack callback functions.
2626 + */
2627 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2628 +{
2629 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2630 +       u32 reg;
2631 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2632 +
2633 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2634 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2635 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2636 +
2637 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2638 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2639 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2640 +
2641 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2642 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2643 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2644 +
2645 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2646 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2647 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2648 +
2649 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2650 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2651 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2652 +
2653 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2654 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2655 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2656 +
2657 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2658 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2659 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2660 +
2661 +       return 0;
2662 +}
2663 +
2664 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2665 +                            const struct ieee80211_tx_queue_params *params)
2666 +{
2667 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2668 +       struct data_queue *queue;
2669 +       struct rt2x00_field32 field;
2670 +       int retval;
2671 +       u32 reg;
2672 +       u32 offset;
2673 +
2674 +       /*
2675 +        * First pass the configuration through rt2x00lib, that will
2676 +        * update the queue settings and validate the input. After that
2677 +        * we are free to update the registers based on the value
2678 +        * in the queue parameter.
2679 +        */
2680 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2681 +       if (retval)
2682 +               return retval;
2683 +
2684 +       /*
2685 +        * We only need to perform additional register initialization
2686 +        * for WMM queues/
2687 +        */
2688 +       if (queue_idx >= 4)
2689 +               return 0;
2690 +
2691 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2692 +
2693 +       /* Update WMM TXOP register */
2694 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2695 +       field.bit_offset = (queue_idx & 1) * 16;
2696 +       field.bit_mask = 0xffff << field.bit_offset;
2697 +
2698 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2699 +       rt2x00_set_field32(&reg, field, queue->txop);
2700 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2701 +
2702 +       /* Update WMM registers */
2703 +       field.bit_offset = queue_idx * 4;
2704 +       field.bit_mask = 0xf << field.bit_offset;
2705 +
2706 +       rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2707 +       rt2x00_set_field32(&reg, field, queue->aifs);
2708 +       rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2709 +
2710 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2711 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2712 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2713 +
2714 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2715 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2716 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2717 +
2718 +       /* Update EDCA registers */
2719 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2720 +
2721 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2722 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2723 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2724 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2725 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2726 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2727 +
2728 +       return 0;
2729 +}
2730 +
2731 +#if 0
2732 +/*
2733 + * Mac80211 demands get_tsf must be atomic.
2734 + * This is not possible for rt2800usb since all register access
2735 + * functions require sleeping. Untill mac80211 no longer needs
2736 + * get_tsf to be atomic, this function should be disabled.
2737 + */
2738 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2739 +{
2740 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2741 +       u64 tsf;
2742 +       u32 reg;
2743 +
2744 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2745 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2746 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2747 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2748 +
2749 +       return tsf;
2750 +}
2751 +#else
2752 +#define rt2800usb_get_tsf      NULL
2753 +#endif
2754 +
2755 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2756 +       .tx                     = rt2x00mac_tx,
2757 +       .start                  = rt2x00mac_start,
2758 +       .stop                   = rt2x00mac_stop,
2759 +       .add_interface          = rt2x00mac_add_interface,
2760 +       .remove_interface       = rt2x00mac_remove_interface,
2761 +       .config                 = rt2x00mac_config,
2762 +       .config_interface       = rt2x00mac_config_interface,
2763 +       .configure_filter       = rt2x00mac_configure_filter,
2764 +       .set_key                = rt2x00mac_set_key,
2765 +       .get_stats              = rt2x00mac_get_stats,
2766 +       .set_rts_threshold      = rt2800usb_set_rts_threshold,
2767 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2768 +       .conf_tx                = rt2800usb_conf_tx,
2769 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2770 +       .get_tsf                = rt2800usb_get_tsf,
2771 +};
2772 +
2773 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2774 +       .probe_hw               = rt2800usb_probe_hw,
2775 +       .get_firmware_name      = rt2800usb_get_firmware_name,
2776 +       .check_firmware         = rt2800usb_check_firmware,
2777 +       .load_firmware          = rt2800usb_load_firmware,
2778 +       .initialize             = rt2x00usb_initialize,
2779 +       .uninitialize           = rt2x00usb_uninitialize,
2780 +       .clear_entry            = rt2x00usb_clear_entry,
2781 +       .set_device_state       = rt2800usb_set_device_state,
2782 +       .rfkill_poll            = rt2800usb_rfkill_poll,
2783 +       .link_stats             = rt2800usb_link_stats,
2784 +       .reset_tuner            = rt2800usb_reset_tuner,
2785 +       .link_tuner             = rt2800usb_link_tuner,
2786 +       .write_tx_desc          = rt2800usb_write_tx_desc,
2787 +       .write_tx_data          = rt2x00usb_write_tx_data,
2788 +       .write_beacon           = rt2800usb_write_beacon,
2789 +       .get_tx_data_len        = rt2800usb_get_tx_data_len,
2790 +       .kick_tx_queue          = rt2800usb_kick_tx_queue,
2791 +       .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2792 +       .fill_rxdone            = rt2800usb_fill_rxdone,
2793 +       .config_shared_key      = rt2800usb_config_shared_key,
2794 +       .config_pairwise_key    = rt2800usb_config_pairwise_key,
2795 +       .config_filter          = rt2800usb_config_filter,
2796 +       .config_intf            = rt2800usb_config_intf,
2797 +       .config_erp             = rt2800usb_config_erp,
2798 +       .config_ant             = rt2800usb_config_ant,
2799 +       .config                 = rt2800usb_config,
2800 +};
2801 +
2802 +static const struct data_queue_desc rt2800usb_queue_rx = {
2803 +       .entry_num              = RX_ENTRIES,
2804 +       .data_size              = DATA_FRAME_SIZE,
2805 +       .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2806 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2807 +};
2808 +
2809 +static const struct data_queue_desc rt2800usb_queue_tx = {
2810 +       .entry_num              = TX_ENTRIES,
2811 +       .data_size              = DATA_FRAME_SIZE,
2812 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2813 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2814 +};
2815 +
2816 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2817 +       .entry_num              = 8 * BEACON_ENTRIES,
2818 +       .data_size              = MGMT_FRAME_SIZE,
2819 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2820 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2821 +};
2822 +
2823 +static const struct rt2x00_ops rt2800usb_ops = {
2824 +       .name           = KBUILD_MODNAME,
2825 +       .max_sta_intf   = 1,
2826 +       .max_ap_intf    = 8,
2827 +       .eeprom_size    = EEPROM_SIZE,
2828 +       .rf_size        = RF_SIZE,
2829 +       .tx_queues      = NUM_TX_QUEUES,
2830 +       .rx             = &rt2800usb_queue_rx,
2831 +       .tx             = &rt2800usb_queue_tx,
2832 +       .bcn            = &rt2800usb_queue_bcn,
2833 +       .lib            = &rt2800usb_rt2x00_ops,
2834 +       .hw             = &rt2800usb_mac80211_ops,
2835 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2836 +       .debugfs        = &rt2800usb_rt2x00debug,
2837 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2838 +};
2839 +
2840 +/*
2841 + * rt2800usb module information.
2842 + */
2843 +static struct usb_device_id rt2800usb_device_table[] = {
2844 +       /* Abocom */
2845 +       { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2846 +       { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2847 +       { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2848 +       { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2849 +       { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2850 +       /* Amit */
2851 +       { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2852 +       /* ASUS */
2853 +       { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2854 +       { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2855 +       { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2856 +       /* AzureWave */
2857 +       { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2858 +       /* Belkin */
2859 +       { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2860 +       { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2861 +       /* Conceptronic */
2862 +       { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2863 +       { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2864 +       { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2865 +       { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2866 +       { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2867 +       { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2868 +       { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2869 +       { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2870 +       /* Corega */
2871 +       { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2872 +       { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2873 +       { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2874 +       { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2875 +       /* D-Link */
2876 +       { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2877 +       { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2878 +       /* Edimax */
2879 +       { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2880 +       /* EnGenius */
2881 +       { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2882 +       { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2883 +       /* Gigabyte */
2884 +       { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2885 +       /* Hawking */
2886 +       { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2887 +       { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2888 +       /* Linksys */
2889 +       { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2890 +       /* Logitec */
2891 +       { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2892 +       { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 +       { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2894 +       /* Philips */
2895 +       { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2896 +       /* Planex */
2897 +       { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 +       { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2899 +       /* Ralink */
2900 +       { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2901 +       { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2902 +       { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 +       /* Samsung */
2904 +       { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 +       /* Siemens */
2906 +       { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 +       /* Sitecom */
2908 +       { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 +       { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2910 +       { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 +       { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2912 +       /* SMC */
2913 +       { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 +       { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2915 +       { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 +       { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 +       /* Sparklan */
2918 +       { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 +       /* U-Media*/
2920 +       { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 +       /* ZCOM */
2922 +       { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 +       { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 +       /* Zinwell */
2925 +       { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 +       { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
2927 +       /* Zyxel */
2928 +       { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 +       { 0, }
2930 +};
2931 +
2932 +MODULE_AUTHOR(DRV_PROJECT);
2933 +MODULE_VERSION(DRV_VERSION);
2934 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
2935 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
2936 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
2937 +MODULE_FIRMWARE(FIRMWARE_RT2870);
2938 +MODULE_LICENSE("GPL");
2939 +
2940 +static struct usb_driver rt2800usb_driver = {
2941 +       .name           = KBUILD_MODNAME,
2942 +       .id_table       = rt2800usb_device_table,
2943 +       .probe          = rt2x00usb_probe,
2944 +       .disconnect     = rt2x00usb_disconnect,
2945 +       .suspend        = rt2x00usb_suspend,
2946 +       .resume         = rt2x00usb_resume,
2947 +};
2948 +
2949 +static int __init rt2800usb_init(void)
2950 +{
2951 +       return usb_register(&rt2800usb_driver);
2952 +}
2953 +
2954 +static void __exit rt2800usb_exit(void)
2955 +{
2956 +       usb_deregister(&rt2800usb_driver);
2957 +}
2958 +
2959 +module_init(rt2800usb_init);
2960 +module_exit(rt2800usb_exit);
2961 --- /dev/null
2962 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
2963 @@ -0,0 +1,1940 @@
2964 +/*
2965 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
2966 +       <http://rt2x00.serialmonkey.com>
2967 +
2968 +       This program is free software; you can redistribute it and/or modify
2969 +       it under the terms of the GNU General Public License as published by
2970 +       the Free Software Foundation; either version 2 of the License, or
2971 +       (at your option) any later version.
2972 +
2973 +       This program is distributed in the hope that it will be useful,
2974 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
2975 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2976 +       GNU General Public License for more details.
2977 +
2978 +       You should have received a copy of the GNU General Public License
2979 +       along with this program; if not, write to the
2980 +       Free Software Foundation, Inc.,
2981 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2982 + */
2983 +
2984 +/*
2985 +       Module: rt2800usb
2986 +       Abstract: Data structures and registers for the rt2800usb module.
2987 +       Supported chipsets: RT2800U.
2988 + */
2989 +
2990 +#ifndef RT2800USB_H
2991 +#define RT2800USB_H
2992 +
2993 +/*
2994 + * RF chip defines.
2995 + *
2996 + * RF2820 2.4G 2T3R
2997 + * RF2850 2.4G/5G 2T3R
2998 + * RF2720 2.4G 1T2R
2999 + * RF2750 2.4G/5G 1T2R
3000 + * RF3020 2.4G 1T1R
3001 + * RF2020 2.4G B/G
3002 + */
3003 +#define RF2820                         0x0001
3004 +#define RF2850                         0x0002
3005 +#define RF2720                         0x0003
3006 +#define RF2750                         0x0004
3007 +#define RF3020                         0x0005
3008 +#define RF2020                         0x0006
3009 +
3010 +/*
3011 + * RT2870 version
3012 + */
3013 +#define RT2860C_VERSION                        0x28600100
3014 +#define RT2860D_VERSION                        0x28600101
3015 +#define RT2880E_VERSION                        0x28720200
3016 +#define RT2883_VERSION                 0x28830300
3017 +#define RT3070_VERSION                 0x30700200
3018 +
3019 +/*
3020 + * Signal information.
3021 + * Defaul offset is required for RSSI <-> dBm conversion.
3022 + */
3023 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
3024 +
3025 +/*
3026 + * Register layout information.
3027 + */
3028 +#define CSR_REG_BASE                   0x1000
3029 +#define CSR_REG_SIZE                   0x0800
3030 +#define EEPROM_BASE                    0x0000
3031 +#define EEPROM_SIZE                    0x0110
3032 +#define BBP_BASE                       0x0000
3033 +#define BBP_SIZE                       0x0080
3034 +#define RF_BASE                                0x0000
3035 +#define RF_SIZE                                0x0014
3036 +
3037 +/*
3038 + * Number of TX queues.
3039 + */
3040 +#define NUM_TX_QUEUES                  4
3041 +
3042 +/*
3043 + * USB registers.
3044 + */
3045 +
3046 +/*
3047 + * HOST-MCU shared memory
3048 + */
3049 +#define HOST_CMD_CSR                   0x0404
3050 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
3051 +
3052 +/*
3053 + * INT_SOURCE_CSR: Interrupt source register.
3054 + * Write one to clear corresponding bit.
3055 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3056 + */
3057 +#define INT_SOURCE_CSR                 0x0200
3058 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
3059 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
3060 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
3061 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
3062 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
3063 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
3064 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
3065 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
3066 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
3067 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
3068 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
3069 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
3070 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
3071 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
3072 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
3073 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
3074 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
3075 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
3076 +
3077 +/*
3078 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3079 + */
3080 +#define INT_MASK_CSR                   0x0204
3081 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
3082 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
3083 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
3084 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
3085 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
3086 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
3087 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
3088 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
3089 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
3090 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
3091 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
3092 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
3093 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
3094 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
3095 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
3096 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
3097 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
3098 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
3099 +
3100 +/*
3101 + * WPDMA_GLO_CFG
3102 + */
3103 +#define WPDMA_GLO_CFG                  0x0208
3104 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
3105 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
3106 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
3107 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
3108 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
3109 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
3110 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
3111 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
3112 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
3113 +
3114 +/*
3115 + * WPDMA_RST_IDX
3116 + */
3117 +#define WPDMA_RST_IDX                  0x020c
3118 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
3119 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
3120 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
3121 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
3122 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
3123 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
3124 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
3125 +
3126 +/*
3127 + * DELAY_INT_CFG
3128 + */
3129 +#define DELAY_INT_CFG                  0x0210
3130 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
3131 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
3132 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
3133 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
3134 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
3135 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
3136 +
3137 +/*
3138 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3139 + * AIFSN0: AC_BE
3140 + * AIFSN1: AC_BK
3141 + * AIFSN1: AC_VI
3142 + * AIFSN1: AC_VO
3143 + */
3144 +#define WMM_AIFSN_CFG                  0x0214
3145 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3146 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3147 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3148 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3149 +
3150 +/*
3151 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3152 + * CWMIN0: AC_BE
3153 + * CWMIN1: AC_BK
3154 + * CWMIN1: AC_VI
3155 + * CWMIN1: AC_VO
3156 + */
3157 +#define WMM_CWMIN_CFG                  0x0218
3158 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3159 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3160 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3161 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3162 +
3163 +/*
3164 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3165 + * CWMAX0: AC_BE
3166 + * CWMAX1: AC_BK
3167 + * CWMAX1: AC_VI
3168 + * CWMAX1: AC_VO
3169 + */
3170 +#define WMM_CWMAX_CFG                  0x021c
3171 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3172 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3173 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3174 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3175 +
3176 +/*
3177 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3178 + * AC0TXOP: AC_BK in unit of 32us
3179 + * AC1TXOP: AC_BE in unit of 32us
3180 + */
3181 +#define WMM_TXOP0_CFG                  0x0220
3182 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3183 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3184 +
3185 +/*
3186 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3187 + * AC2TXOP: AC_VI in unit of 32us
3188 + * AC3TXOP: AC_VO in unit of 32us
3189 + */
3190 +#define WMM_TXOP1_CFG                  0x0224
3191 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3192 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3193 +
3194 +/*
3195 + * RINGREG_DIFF
3196 + */
3197 +#define RINGREG_DIFF                   0x0010
3198 +
3199 +/*
3200 + * GPIO_CTRL_CFG:
3201 + */
3202 +#define GPIO_CTRL_CFG                  0x0228
3203 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3204 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3205 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3206 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3207 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3208 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3209 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3210 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3211 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3212 +
3213 +/*
3214 + * MCU_CMD_CFG
3215 + */
3216 +#define MCU_CMD_CFG                    0x022c
3217 +
3218 +/*
3219 + * AC_BK register offsets
3220 + */
3221 +#define TX_BASE_PTR0                   0x0230
3222 +#define TX_MAX_CNT0                    0x0234
3223 +#define TX_CTX_IDX0                    0x0238
3224 +#define TX_DTX_IDX0                    0x023c
3225 +
3226 +/*
3227 + * AC_BE register offsets
3228 + */
3229 +#define TX_BASE_PTR1                   0x0240
3230 +#define TX_MAX_CNT1                    0x0244
3231 +#define TX_CTX_IDX1                    0x0248
3232 +#define TX_DTX_IDX1                    0x024c
3233 +
3234 +/*
3235 + * AC_VI register offsets
3236 + */
3237 +#define TX_BASE_PTR2                   0x0250
3238 +#define TX_MAX_CNT2                    0x0254
3239 +#define TX_CTX_IDX2                    0x0258
3240 +#define TX_DTX_IDX2                    0x025c
3241 +
3242 +/*
3243 + * AC_VO register offsets
3244 + */
3245 +#define TX_BASE_PTR3                   0x0260
3246 +#define TX_MAX_CNT3                    0x0264
3247 +#define TX_CTX_IDX3                    0x0268
3248 +#define TX_DTX_IDX3                    0x026c
3249 +
3250 +/*
3251 + * HCCA register offsets
3252 + */
3253 +#define TX_BASE_PTR4                   0x0270
3254 +#define TX_MAX_CNT4                    0x0274
3255 +#define TX_CTX_IDX4                    0x0278
3256 +#define TX_DTX_IDX4                    0x027c
3257 +
3258 +/*
3259 + * MGMT register offsets
3260 + */
3261 +#define TX_BASE_PTR5                   0x0280
3262 +#define TX_MAX_CNT5                    0x0284
3263 +#define TX_CTX_IDX5                    0x0288
3264 +#define TX_DTX_IDX5                    0x028c
3265 +
3266 +/*
3267 + * RX register offsets
3268 + */
3269 +#define RX_BASE_PTR                    0x0290
3270 +#define RX_MAX_CNT                     0x0294
3271 +#define RX_CRX_IDX                     0x0298
3272 +#define RX_DRX_IDX                     0x029c
3273 +
3274 +/*
3275 + * USB_DMA_CFG
3276 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
3277 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
3278 + * PHY_CLEAR: phy watch dog enable.
3279 + * TX_CLEAR: Clear USB DMA TX path.
3280 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
3281 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
3282 + * RX_BULK_EN: Enable USB DMA Rx.
3283 + * TX_BULK_EN: Enable USB DMA Tx.
3284 + * EP_OUT_VALID: OUT endpoint data valid.
3285 + * RX_BUSY: USB DMA RX FSM busy.
3286 + * TX_BUSY: USB DMA TX FSM busy.
3287 + */
3288 +#define USB_DMA_CFG                    0x02a0
3289 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT        FIELD32(0x000000ff)
3290 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT  FIELD32(0x0000ff00)
3291 +#define USB_DMA_CFG_PHY_CLEAR          FIELD32(0x00010000)
3292 +#define USB_DMA_CFG_TX_CLEAR           FIELD32(0x00080000)
3293 +#define USB_DMA_CFG_TXOP_HALT          FIELD32(0x00100000)
3294 +#define USB_DMA_CFG_RX_BULK_AGG_EN     FIELD32(0x00200000)
3295 +#define USB_DMA_CFG_RX_BULK_EN         FIELD32(0x00400000)
3296 +#define USB_DMA_CFG_TX_BULK_EN         FIELD32(0x00800000)
3297 +#define USB_DMA_CFG_EP_OUT_VALID       FIELD32(0x3f000000)
3298 +#define USB_DMA_CFG_RX_BUSY            FIELD32(0x40000000)
3299 +#define USB_DMA_CFG_TX_BUSY            FIELD32(0x80000000)
3300 +
3301 +/*
3302 + * USB_CYC_CFG
3303 + */
3304 +#define USB_CYC_CFG                    0x02a4
3305 +#define USB_CYC_CFG_CLOCK_CYCLE                FIELD32(0x000000ff)
3306 +
3307 +/*
3308 + * PBF_SYS_CTRL
3309 + * HOST_RAM_WRITE: enable Host program ram write selection
3310 + */
3311 +#define PBF_SYS_CTRL                   0x0400
3312 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3313 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3314 +
3315 +/*
3316 + * PBF registers
3317 + * Most are for debug. Driver doesn't touch PBF register.
3318 + */
3319 +#define PBF_CFG                                0x0408
3320 +#define PBF_MAX_PCNT                   0x040c
3321 +#define PBF_CTRL                       0x0410
3322 +#define PBF_INT_STA                    0x0414
3323 +#define PBF_INT_ENA                    0x0418
3324 +
3325 +/*
3326 + * BCN_OFFSET0:
3327 + */
3328 +#define BCN_OFFSET0                    0x042c
3329 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3330 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3331 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3332 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3333 +
3334 +/*
3335 + * BCN_OFFSET1:
3336 + */
3337 +#define BCN_OFFSET1                    0x0430
3338 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3339 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3340 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3341 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3342 +
3343 +/*
3344 + * PBF registers
3345 + * Most are for debug. Driver doesn't touch PBF register.
3346 + */
3347 +#define TXRXQ_PCNT                     0x0438
3348 +#define PBF_DBG                                0x043c
3349 +
3350 +/*
3351 + * RF registers
3352 + */
3353 +#define        RF_CSR_CFG                      0x0500
3354 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
3355 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
3356 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
3357 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
3358 +
3359 +/*
3360 + * MAC Control/Status Registers(CSR).
3361 + * Some values are set in TU, whereas 1 TU == 1024 us.
3362 + */
3363 +
3364 +/*
3365 + * MAC_CSR0: ASIC revision number.
3366 + * ASIC_REV: 0
3367 + * ASIC_VER: 2870
3368 + */
3369 +#define MAC_CSR0                       0x1000
3370 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3371 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3372 +
3373 +/*
3374 + * MAC_SYS_CTRL:
3375 + */
3376 +#define MAC_SYS_CTRL                   0x1004
3377 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3378 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3379 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3380 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3381 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3382 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3383 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3384 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3385 +
3386 +/*
3387 + * MAC_ADDR_DW0: STA MAC register 0
3388 + */
3389 +#define MAC_ADDR_DW0                   0x1008
3390 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3391 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3392 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3393 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3394 +
3395 +/*
3396 + * MAC_ADDR_DW1: STA MAC register 1
3397 + * UNICAST_TO_ME_MASK:
3398 + * Used to mask off bits from byte 5 of the MAC address
3399 + * to determine the UNICAST_TO_ME bit for RX frames.
3400 + * The full mask is complemented by BSS_ID_MASK:
3401 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3402 + */
3403 +#define MAC_ADDR_DW1                   0x100c
3404 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3405 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3406 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3407 +
3408 +/*
3409 + * MAC_BSSID_DW0: BSSID register 0
3410 + */
3411 +#define MAC_BSSID_DW0                  0x1010
3412 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3413 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3414 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3415 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3416 +
3417 +/*
3418 + * MAC_BSSID_DW1: BSSID register 1
3419 + * BSS_ID_MASK:
3420 + *     0: 1-BSSID mode (BSS index = 0)
3421 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3422 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3423 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3424 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3425 + * BSSID. This will make sure that those bits will be ignored
3426 + * when determining the MY_BSS of RX frames.
3427 + */
3428 +#define MAC_BSSID_DW1                  0x1014
3429 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3430 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3431 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3432 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3433 +
3434 +/*
3435 + * MAX_LEN_CFG: Maximum frame length register.
3436 + * MAX_MPDU: rt2860b max 16k bytes
3437 + * MAX_PSDU: Maximum PSDU length
3438 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3439 + */
3440 +#define MAX_LEN_CFG                    0x1018
3441 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3442 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3443 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3444 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3445 +
3446 +/*
3447 + * BBP_CSR_CFG: BBP serial control register
3448 + * VALUE: Register value to program into BBP
3449 + * REG_NUM: Selected BBP register
3450 + * READ_CONTROL: 0 write BBP, 1 read BBP
3451 + * BUSY: ASIC is busy executing BBP commands
3452 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3453 + * BBP_RW_MODE: 0 serial, 1 paralell
3454 + */
3455 +#define BBP_CSR_CFG                    0x101c
3456 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3457 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3458 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3459 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3460 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3461 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3462 +
3463 +/*
3464 + * RF_CSR_CFG0: RF control register
3465 + * REGID_AND_VALUE: Register value to program into RF
3466 + * BITWIDTH: Selected RF register
3467 + * STANDBYMODE: 0 high when standby, 1 low when standby
3468 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3469 + * BUSY: ASIC is busy executing RF commands
3470 + */
3471 +#define RF_CSR_CFG0                    0x1020
3472 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3473 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3474 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3475 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3476 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3477 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3478 +
3479 +/*
3480 + * RF_CSR_CFG1: RF control register
3481 + * REGID_AND_VALUE: Register value to program into RF
3482 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3483 + *        0: 3 system clock cycle (37.5usec)
3484 + *        1: 5 system clock cycle (62.5usec)
3485 + */
3486 +#define RF_CSR_CFG1                    0x1024
3487 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3488 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3489 +
3490 +/*
3491 + * RF_CSR_CFG2: RF control register
3492 + * VALUE: Register value to program into RF
3493 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3494 + *        0: 3 system clock cycle (37.5usec)
3495 + *        1: 5 system clock cycle (62.5usec)
3496 + */
3497 +#define RF_CSR_CFG2                    0x1028
3498 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3499 +
3500 +/*
3501 + * LED_CFG: LED control
3502 + * color LED's:
3503 + *   0: off
3504 + *   1: blinking upon TX2
3505 + *   2: periodic slow blinking
3506 + *   3: always on
3507 + * LED polarity:
3508 + *   0: active low
3509 + *   1: active high
3510 + */
3511 +#define LED_CFG                                0x102c
3512 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3513 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3514 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3515 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3516 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3517 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3518 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3519 +
3520 +/*
3521 + * XIFS_TIME_CFG: MAC timing
3522 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3523 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3524 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3525 + *     when MAC doesn't reference BBP signal BBRXEND
3526 + * EIFS: unit 1us
3527 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3528 + *
3529 + */
3530 +#define XIFS_TIME_CFG                  0x1100
3531 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3532 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3533 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3534 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3535 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3536 +
3537 +/*
3538 + * BKOFF_SLOT_CFG:
3539 + */
3540 +#define BKOFF_SLOT_CFG                 0x1104
3541 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3542 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3543 +
3544 +/*
3545 + * NAV_TIME_CFG:
3546 + */
3547 +#define NAV_TIME_CFG                   0x1108
3548 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3549 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3550 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3551 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3552 +
3553 +/*
3554 + * CH_TIME_CFG: count as channel busy
3555 + */
3556 +#define CH_TIME_CFG                    0x110c
3557 +
3558 +/*
3559 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3560 + */
3561 +#define PBF_LIFE_TIMER                 0x1110
3562 +
3563 +/*
3564 + * BCN_TIME_CFG:
3565 + * BEACON_INTERVAL: in unit of 1/16 TU
3566 + * TSF_TICKING: Enable TSF auto counting
3567 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3568 + * BEACON_GEN: Enable beacon generator
3569 + */
3570 +#define BCN_TIME_CFG                   0x1114
3571 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3572 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3573 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3574 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3575 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3576 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3577 +
3578 +/*
3579 + * TBTT_SYNC_CFG:
3580 + */
3581 +#define TBTT_SYNC_CFG                  0x1118
3582 +
3583 +/*
3584 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3585 + */
3586 +#define TSF_TIMER_DW0                  0x111c
3587 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3588 +
3589 +/*
3590 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3591 + */
3592 +#define TSF_TIMER_DW1                  0x1120
3593 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3594 +
3595 +/*
3596 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3597 + */
3598 +#define TBTT_TIMER                     0x1124
3599 +
3600 +/*
3601 + * INT_TIMER_CFG:
3602 + */
3603 +#define INT_TIMER_CFG                  0x1128
3604 +
3605 +/*
3606 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3607 + */
3608 +#define INT_TIMER_EN                   0x112c
3609 +
3610 +/*
3611 + * CH_IDLE_STA: channel idle time
3612 + */
3613 +#define CH_IDLE_STA                    0x1130
3614 +
3615 +/*
3616 + * CH_BUSY_STA: channel busy time
3617 + */
3618 +#define CH_BUSY_STA                    0x1134
3619 +
3620 +/*
3621 + * MAC_STATUS_CFG:
3622 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3623 + *     if 1 or higher one of the 2 registers is busy.
3624 + */
3625 +#define MAC_STATUS_CFG                 0x1200
3626 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3627 +
3628 +/*
3629 + * PWR_PIN_CFG:
3630 + */
3631 +#define PWR_PIN_CFG                    0x1204
3632 +
3633 +/*
3634 + * AUTOWAKEUP_CFG: Manual power control / status register
3635 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3636 + * AUTOWAKE: 0:sleep, 1:awake
3637 + */
3638 +#define AUTOWAKEUP_CFG                 0x1208
3639 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3640 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3641 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3642 +
3643 +/*
3644 + * EDCA_AC0_CFG:
3645 + */
3646 +#define EDCA_AC0_CFG                   0x1300
3647 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
3648 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3649 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3650 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3651 +
3652 +/*
3653 + * EDCA_AC1_CFG:
3654 + */
3655 +#define EDCA_AC1_CFG                   0x1304
3656 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
3657 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3658 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3659 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3660 +
3661 +/*
3662 + * EDCA_AC2_CFG:
3663 + */
3664 +#define EDCA_AC2_CFG                   0x1308
3665 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
3666 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3667 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3668 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3669 +
3670 +/*
3671 + * EDCA_AC3_CFG:
3672 + */
3673 +#define EDCA_AC3_CFG                   0x130c
3674 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
3675 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3676 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3677 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3678 +
3679 +/*
3680 + * EDCA_TID_AC_MAP:
3681 + */
3682 +#define EDCA_TID_AC_MAP                        0x1310
3683 +
3684 +/*
3685 + * TX_PWR_CFG_0:
3686 + */
3687 +#define TX_PWR_CFG_0                   0x1314
3688 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3689 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3690 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3691 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3692 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3693 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3694 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3695 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3696 +
3697 +/*
3698 + * TX_PWR_CFG_1:
3699 + */
3700 +#define TX_PWR_CFG_1                   0x1318
3701 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3702 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3703 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3704 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3705 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3706 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3707 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3708 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3709 +
3710 +/*
3711 + * TX_PWR_CFG_2:
3712 + */
3713 +#define TX_PWR_CFG_2                   0x131c
3714 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3715 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3716 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3717 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3718 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3719 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3720 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3721 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3722 +
3723 +/*
3724 + * TX_PWR_CFG_3:
3725 + */
3726 +#define TX_PWR_CFG_3                   0x1320
3727 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3728 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3729 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3730 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3731 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3732 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3733 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3734 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3735 +
3736 +/*
3737 + * TX_PWR_CFG_4:
3738 + */
3739 +#define TX_PWR_CFG_4                   0x1324
3740 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3741 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3742 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3743 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3744 +
3745 +/*
3746 + * TX_PIN_CFG:
3747 + */
3748 +#define TX_PIN_CFG                     0x1328
3749 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3750 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3751 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3752 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3753 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3754 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3755 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3756 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3757 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3758 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3759 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3760 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3761 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3762 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3763 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3764 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3765 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3766 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3767 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3768 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3769 +
3770 +/*
3771 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3772 + */
3773 +#define TX_BAND_CFG                    0x132c
3774 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3775 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3776 +
3777 +/*
3778 + * TX_SW_CFG0:
3779 + */
3780 +#define TX_SW_CFG0                     0x1330
3781 +
3782 +/*
3783 + * TX_SW_CFG1:
3784 + */
3785 +#define TX_SW_CFG1                     0x1334
3786 +
3787 +/*
3788 + * TX_SW_CFG2:
3789 + */
3790 +#define TX_SW_CFG2                     0x1338
3791 +
3792 +/*
3793 + * TXOP_THRES_CFG:
3794 + */
3795 +#define TXOP_THRES_CFG                 0x133c
3796 +
3797 +/*
3798 + * TXOP_CTRL_CFG:
3799 + */
3800 +#define TXOP_CTRL_CFG                  0x1340
3801 +
3802 +/*
3803 + * TX_RTS_CFG:
3804 + * RTS_THRES: unit:byte
3805 + * RTS_FBK_EN: enable rts rate fallback
3806 + */
3807 +#define TX_RTS_CFG                     0x1344
3808 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3809 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3810 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3811 +
3812 +/*
3813 + * TX_TIMEOUT_CFG:
3814 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3815 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3816 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3817 + *                it is recommended that:
3818 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3819 + */
3820 +#define TX_TIMEOUT_CFG                 0x1348
3821 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3822 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3823 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3824 +
3825 +/*
3826 + * TX_RTY_CFG:
3827 + * SHORT_RTY_LIMIT: short retry limit
3828 + * LONG_RTY_LIMIT: long retry limit
3829 + * LONG_RTY_THRE: Long retry threshoold
3830 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3831 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3832 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3833 + *               0:expired by retry limit, 1: expired by mpdu life timer
3834 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3835 + */
3836 +#define TX_RTY_CFG                     0x134c
3837 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3838 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3839 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3840 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3841 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3842 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3843 +
3844 +/*
3845 + * TX_LINK_CFG:
3846 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3847 + * MFB_ENABLE: TX apply remote MFB 1:enable
3848 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3849 + *                     0: not apply remote remote unsolicit (MFS=7)
3850 + * TX_MRQ_EN: MCS request TX enable
3851 + * TX_RDG_EN: RDG TX enable
3852 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3853 + * REMOTE_MFB: remote MCS feedback
3854 + * REMOTE_MFS: remote MCS feedback sequence number
3855 + */
3856 +#define TX_LINK_CFG                    0x1350
3857 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3858 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3859 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3860 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3861 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3862 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3863 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3864 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3865 +
3866 +/*
3867 + * HT_FBK_CFG0:
3868 + */
3869 +#define HT_FBK_CFG0                    0x1354
3870 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3871 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3872 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3873 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3874 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3875 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3876 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3877 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3878 +
3879 +/*
3880 + * HT_FBK_CFG1:
3881 + */
3882 +#define HT_FBK_CFG1                    0x1358
3883 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3884 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3885 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3886 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3887 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3888 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3889 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3890 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3891 +
3892 +/*
3893 + * LG_FBK_CFG0:
3894 + */
3895 +#define LG_FBK_CFG0                    0x135c
3896 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
3897 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
3898 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
3899 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
3900 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
3901 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
3902 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
3903 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
3904 +
3905 +/*
3906 + * LG_FBK_CFG1:
3907 + */
3908 +#define LG_FBK_CFG1                    0x1360
3909 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
3910 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
3911 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
3912 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
3913 +
3914 +/*
3915 + * CCK_PROT_CFG: CCK Protection
3916 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3917 + * PROTECT_CTRL: Protection control frame type for CCK TX
3918 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
3919 + * PROTECT_NAV: TXOP protection type for CCK TX
3920 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3921 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3922 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3923 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3924 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3925 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3926 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3927 + * RTS_TH_EN: RTS threshold enable on CCK TX
3928 + */
3929 +#define CCK_PROT_CFG                   0x1364
3930 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
3931 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
3932 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
3933 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
3934 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
3935 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
3936 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
3937 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
3938 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
3939 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
3940 +
3941 +/*
3942 + * OFDM_PROT_CFG: OFDM Protection
3943 + */
3944 +#define OFDM_PROT_CFG                  0x1368
3945 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3946 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3947 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3948 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3949 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3950 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3951 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3952 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3953 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3954 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3955 +
3956 +/*
3957 + * MM20_PROT_CFG: MM20 Protection
3958 + */
3959 +#define MM20_PROT_CFG                  0x136c
3960 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3961 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3962 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3963 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3964 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3965 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3966 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3967 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3968 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3969 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3970 +
3971 +/*
3972 + * MM40_PROT_CFG: MM40 Protection
3973 + */
3974 +#define MM40_PROT_CFG                  0x1370
3975 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3976 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3977 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3978 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3979 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3980 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3981 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3982 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3983 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3984 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3985 +
3986 +/*
3987 + * GF20_PROT_CFG: GF20 Protection
3988 + */
3989 +#define GF20_PROT_CFG                  0x1374
3990 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3991 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3992 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3993 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3994 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3995 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3996 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3997 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3998 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3999 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4000 +
4001 +/*
4002 + * GF40_PROT_CFG: GF40 Protection
4003 + */
4004 +#define GF40_PROT_CFG                  0x1378
4005 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4006 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4007 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4008 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4009 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4010 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4011 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4012 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4013 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4014 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4015 +
4016 +/*
4017 + * EXP_CTS_TIME:
4018 + */
4019 +#define EXP_CTS_TIME                   0x137c
4020 +
4021 +/*
4022 + * EXP_ACK_TIME:
4023 + */
4024 +#define EXP_ACK_TIME                   0x1380
4025 +
4026 +/*
4027 + * RX_FILTER_CFG: RX configuration register.
4028 + */
4029 +#define RX_FILTER_CFG                  0x1400
4030 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
4031 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
4032 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
4033 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4034 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
4035 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
4036 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
4037 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
4038 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
4039 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
4040 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
4041 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
4042 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
4043 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
4044 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
4045 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
4046 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
4047 +
4048 +/*
4049 + * AUTO_RSP_CFG:
4050 + * AUTORESPONDER: 0: disable, 1: enable
4051 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4052 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4053 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4054 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4055 + * DUAL_CTS_EN: Power bit value in control frame
4056 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4057 + */
4058 +#define AUTO_RSP_CFG                   0x1404
4059 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
4060 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
4061 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
4062 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
4063 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
4064 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
4065 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
4066 +
4067 +/*
4068 + * LEGACY_BASIC_RATE:
4069 + */
4070 +#define LEGACY_BASIC_RATE              0x1408
4071 +
4072 +/*
4073 + * HT_BASIC_RATE:
4074 + */
4075 +#define HT_BASIC_RATE                  0x140c
4076 +
4077 +/*
4078 + * HT_CTRL_CFG:
4079 + */
4080 +#define HT_CTRL_CFG                    0x1410
4081 +
4082 +/*
4083 + * SIFS_COST_CFG:
4084 + */
4085 +#define SIFS_COST_CFG                  0x1414
4086 +
4087 +/*
4088 + * RX_PARSER_CFG:
4089 + * Set NAV for all received frames
4090 + */
4091 +#define RX_PARSER_CFG                  0x1418
4092 +
4093 +/*
4094 + * TX_SEC_CNT0:
4095 + */
4096 +#define TX_SEC_CNT0                    0x1500
4097 +
4098 +/*
4099 + * RX_SEC_CNT0:
4100 + */
4101 +#define RX_SEC_CNT0                    0x1504
4102 +
4103 +/*
4104 + * CCMP_FC_MUTE:
4105 + */
4106 +#define CCMP_FC_MUTE                   0x1508
4107 +
4108 +/*
4109 + * TXOP_HLDR_ADDR0:
4110 + */
4111 +#define TXOP_HLDR_ADDR0                        0x1600
4112 +
4113 +/*
4114 + * TXOP_HLDR_ADDR1:
4115 + */
4116 +#define TXOP_HLDR_ADDR1                        0x1604
4117 +
4118 +/*
4119 + * TXOP_HLDR_ET:
4120 + */
4121 +#define TXOP_HLDR_ET                   0x1608
4122 +
4123 +/*
4124 + * QOS_CFPOLL_RA_DW0:
4125 + */
4126 +#define QOS_CFPOLL_RA_DW0              0x160c
4127 +
4128 +/*
4129 + * QOS_CFPOLL_RA_DW1:
4130 + */
4131 +#define QOS_CFPOLL_RA_DW1              0x1610
4132 +
4133 +/*
4134 + * QOS_CFPOLL_QC:
4135 + */
4136 +#define QOS_CFPOLL_QC                  0x1614
4137 +
4138 +/*
4139 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4140 + */
4141 +#define RX_STA_CNT0                    0x1700
4142 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
4143 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
4144 +
4145 +/*
4146 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4147 + */
4148 +#define RX_STA_CNT1                    0x1704
4149 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
4150 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
4151 +
4152 +/*
4153 + * RX_STA_CNT2:
4154 + */
4155 +#define RX_STA_CNT2                    0x1708
4156 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
4157 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
4158 +
4159 +/*
4160 + * TX_STA_CNT0: TX Beacon count
4161 + */
4162 +#define TX_STA_CNT0                    0x170c
4163 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
4164 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
4165 +
4166 +/*
4167 + * TX_STA_CNT1: TX tx count
4168 + */
4169 +#define TX_STA_CNT1                    0x1710
4170 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
4171 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
4172 +
4173 +/*
4174 + * TX_STA_CNT2: TX tx count
4175 + */
4176 +#define TX_STA_CNT2                    0x1714
4177 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
4178 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
4179 +
4180 +/*
4181 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4182 + */
4183 +#define TX_STA_FIFO                    0x1718
4184 +#define TX_STA_FIFO_B_VALID            FIELD32(0x00000001)
4185 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
4186 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
4187 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4188 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4189 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4190 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4191 +
4192 +/*
4193 + * TX_AGG_CNT: Debug counter
4194 + */
4195 +#define TX_AGG_CNT                     0x171c
4196 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4197 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4198 +
4199 +/*
4200 + * TX_AGG_CNT0:
4201 + */
4202 +#define TX_AGG_CNT0                    0x1720
4203 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4204 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4205 +
4206 +/*
4207 + * TX_AGG_CNT1:
4208 + */
4209 +#define TX_AGG_CNT1                    0x1724
4210 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4211 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4212 +
4213 +/*
4214 + * TX_AGG_CNT2:
4215 + */
4216 +#define TX_AGG_CNT2                    0x1728
4217 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4218 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4219 +
4220 +/*
4221 + * TX_AGG_CNT3:
4222 + */
4223 +#define TX_AGG_CNT3                    0x172c
4224 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4225 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4226 +
4227 +/*
4228 + * TX_AGG_CNT4:
4229 + */
4230 +#define TX_AGG_CNT4                    0x1730
4231 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4232 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4233 +
4234 +/*
4235 + * TX_AGG_CNT5:
4236 + */
4237 +#define TX_AGG_CNT5                    0x1734
4238 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4239 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4240 +
4241 +/*
4242 + * TX_AGG_CNT6:
4243 + */
4244 +#define TX_AGG_CNT6                    0x1738
4245 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4246 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4247 +
4248 +/*
4249 + * TX_AGG_CNT7:
4250 + */
4251 +#define TX_AGG_CNT7                    0x173c
4252 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4253 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4254 +
4255 +/*
4256 + * MPDU_DENSITY_CNT:
4257 + * TX_ZERO_DEL: TX zero length delimiter count
4258 + * RX_ZERO_DEL: RX zero length delimiter count
4259 + */
4260 +#define MPDU_DENSITY_CNT               0x1740
4261 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4262 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4263 +
4264 +/*
4265 + * Security key table memory.
4266 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4267 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4268 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4269 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4270 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4271 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4272 + */
4273 +#define MAC_WCID_BASE                  0x1800
4274 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4275 +#define MAC_IVEIV_TABLE_BASE           0x6000
4276 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4277 +#define SHARED_KEY_TABLE_BASE          0x6c00
4278 +#define SHARED_KEY_MODE_BASE           0x7000
4279 +
4280 +#define MAC_WCID_ENTRY(__idx) \
4281 +       ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4282 +#define PAIRWISE_KEY_ENTRY(__idx) \
4283 +       ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4284 +#define MAC_IVEIV_ENTRY(__idx) \
4285 +       ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4286 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4287 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4288 +#define SHARED_KEY_ENTRY(__idx) \
4289 +       ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4290 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4291 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4292 +
4293 +struct mac_wcid_entry {
4294 +       u8 mac[6];
4295 +       u8 reserved[2];
4296 +} __attribute__ ((packed));
4297 +
4298 +struct hw_key_entry {
4299 +       u8 key[16];
4300 +       u8 tx_mic[8];
4301 +       u8 rx_mic[8];
4302 +} __attribute__ ((packed));
4303 +
4304 +struct mac_iveiv_entry {
4305 +       u8 iv[8];
4306 +} __attribute__ ((packed));
4307 +
4308 +/*
4309 + * MAC_IVEIV:
4310 + */
4311 +#define MAC_IVEIV_EIV                  FIELD32(0x20000000)
4312 +#define MAC_IVEIV_KEYIDX               FIELD32(0xc0000000)
4313 +
4314 +/*
4315 + * MAC_WCID_ATTRIBUTE:
4316 + */
4317 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4318 +#define MAC_WCID_ATTRIBUTE_CIPHER      FIELD32(0x0000000e)
4319 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4320 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4321 +
4322 +/*
4323 + * SHARED_KEY_MODE:
4324 + */
4325 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4326 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4327 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4328 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4329 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4330 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4331 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4332 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4333 +
4334 +/*
4335 + * HOST-MCU communication
4336 + */
4337 +
4338 +/*
4339 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4340 + */
4341 +#define H2M_MAILBOX_CSR                        0x7010
4342 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4343 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4344 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4345 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4346 +
4347 +/*
4348 + * H2M_MAILBOX_CID:
4349 + */
4350 +#define H2M_MAILBOX_CID                        0x7014
4351 +
4352 +/*
4353 + * H2M_MAILBOX_STATUS:
4354 + */
4355 +#define H2M_MAILBOX_STATUS             0x701c
4356 +
4357 +/*
4358 + * H2M_INT_SRC:
4359 + */
4360 +#define H2M_INT_SRC                    0x7024
4361 +
4362 +/*
4363 + * H2M_BBP_AGENT:
4364 + */
4365 +#define H2M_BBP_AGENT                  0x7028
4366 +
4367 +/*
4368 + * MCU_LEDCS: LED control for MCU Mailbox.
4369 + */
4370 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4371 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4372 +
4373 +/*
4374 + * HW_CS_CTS_BASE:
4375 + * Carrier-sense CTS frame base address.
4376 + * It's where mac stores carrier-sense frame for carrier-sense function.
4377 + */
4378 +#define HW_CS_CTS_BASE                 0x7700
4379 +
4380 +/*
4381 + * HW_DFS_CTS_BASE:
4382 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4383 + */
4384 +#define HW_DFS_CTS_BASE                        0x7780
4385 +
4386 +/*
4387 + * TXRX control registers - base address 0x3000
4388 + */
4389 +
4390 +/*
4391 + * TXRX_CSR1:
4392 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4393 + */
4394 +#define TXRX_CSR1                      0x77d0
4395 +
4396 +/*
4397 + * HW_DEBUG_SETTING_BASE:
4398 + * since NULL frame won't be that long (256 byte)
4399 + * We steal 16 tail bytes to save debugging settings
4400 + */
4401 +#define HW_DEBUG_SETTING_BASE          0x77f0
4402 +#define HW_DEBUG_SETTING_BASE2         0x7770
4403 +
4404 +/*
4405 + * HW_BEACON_BASE
4406 + * In order to support maximum 8 MBSS and its maximum length
4407 + *     is 512 bytes for each beacon
4408 + * Three section discontinue memory segments will be used.
4409 + * 1. The original region for BCN 0~3
4410 + * 2. Extract memory from FCE table for BCN 4~5
4411 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4412 + *    It occupied those memory of wcid 238~253 for BCN 6
4413 + *    and wcid 222~237 for BCN 7
4414 + *
4415 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4416 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4417 + */
4418 +#define HW_BEACON_BASE0                        0x7800
4419 +#define HW_BEACON_BASE1                        0x7a00
4420 +#define HW_BEACON_BASE2                        0x7c00
4421 +#define HW_BEACON_BASE3                        0x7e00
4422 +#define HW_BEACON_BASE4                        0x7200
4423 +#define HW_BEACON_BASE5                        0x7400
4424 +#define HW_BEACON_BASE6                        0x5dc0
4425 +#define HW_BEACON_BASE7                        0x5bc0
4426 +
4427 +#define HW_BEACON_OFFSET(__index) \
4428 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4429 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4430 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4431 +
4432 +/*
4433 + * 8051 firmware image.
4434 + */
4435 +#define FIRMWARE_RT2870                        "rt2870.bin"
4436 +#define FIRMWARE_IMAGE_BASE            0x3000
4437 +
4438 +/*
4439 + * BBP registers.
4440 + * The wordsize of the BBP is 8 bits.
4441 + */
4442 +
4443 +/*
4444 + * BBP 1: TX Antenna
4445 + */
4446 +#define BBP1_TX_POWER                  FIELD8(0x07)
4447 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4448 +
4449 +/*
4450 + * BBP 3: RX Antenna
4451 + */
4452 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4453 +
4454 +/*
4455 + * BBP 4: Bandwidth
4456 + */
4457 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
4458 +
4459 +/*
4460 + * RFCSR registers
4461 + * The wordsize of the RFCSR is 8 bits.
4462 + */
4463 +
4464 +/*
4465 + * RFCSR 6:
4466 + */
4467 +#define RFCSR6_R                       FIELD8(0x03)
4468 +
4469 +/*
4470 + * RFCSR 7:
4471 + */
4472 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
4473 +
4474 +/*
4475 + * RFCSR 12:
4476 + */
4477 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
4478 +
4479 +/*
4480 + * RFCSR 22:
4481 + */
4482 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
4483 +
4484 +/*
4485 + * RFCSR 23:
4486 + */
4487 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
4488 +
4489 +/*
4490 + * RFCSR 30:
4491 + */
4492 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
4493 +
4494 +/*
4495 + * RF registers
4496 + */
4497 +
4498 +/*
4499 + * RF 2
4500 + */
4501 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4502 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4503 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4504 +
4505 +/*
4506 + * RF 3
4507 + */
4508 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4509 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4510 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4511 +
4512 +/*
4513 + * RF 4
4514 + */
4515 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4516 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4517 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4518 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4519 +#define RF4_BW40                       FIELD32(0x00200000)
4520 +
4521 +/*
4522 + * EEPROM content.
4523 + * The wordsize of the EEPROM is 16 bits.
4524 + */
4525 +
4526 +/*
4527 + * EEPROM Version
4528 + */
4529 +#define EEPROM_VERSION                 0x0001
4530 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4531 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4532 +
4533 +/*
4534 + * HW MAC address.
4535 + */
4536 +#define EEPROM_MAC_ADDR_0              0x0002
4537 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4538 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4539 +#define EEPROM_MAC_ADDR_1              0x0003
4540 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4541 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4542 +#define EEPROM_MAC_ADDR_2              0x0004
4543 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4544 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4545 +
4546 +/*
4547 + * EEPROM ANTENNA config
4548 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4549 + * TXPATH: 1: 1T, 2: 2T
4550 + */
4551 +#define        EEPROM_ANTENNA                  0x001a
4552 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4553 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4554 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4555 +
4556 +/*
4557 + * EEPROM NIC config
4558 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4559 + */
4560 +#define        EEPROM_NIC                      0x001b
4561 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4562 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4563 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4564 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4565 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4566 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4567 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4568 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4569 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4570 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4571 +
4572 +/*
4573 + * EEPROM frequency
4574 + */
4575 +#define        EEPROM_FREQ                     0x001d
4576 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4577 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4578 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4579 +
4580 +/*
4581 + * EEPROM LED
4582 + * POLARITY_RDY_G: Polarity RDY_G setting.
4583 + * POLARITY_RDY_A: Polarity RDY_A setting.
4584 + * POLARITY_ACT: Polarity ACT setting.
4585 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4586 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4587 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4588 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4589 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4590 + * LED_MODE: Led mode.
4591 + */
4592 +#define EEPROM_LED1                    0x001e
4593 +#define EEPROM_LED2                    0x001f
4594 +#define EEPROM_LED3                    0x0020
4595 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4596 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4597 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4598 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4599 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4600 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4601 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4602 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4603 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4604 +
4605 +/*
4606 + * EEPROM LNA
4607 + */
4608 +#define EEPROM_LNA                     0x0022
4609 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4610 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4611 +
4612 +/*
4613 + * EEPROM RSSI BG offset
4614 + */
4615 +#define EEPROM_RSSI_BG                 0x0023
4616 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4617 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4618 +
4619 +/*
4620 + * EEPROM RSSI BG2 offset
4621 + */
4622 +#define EEPROM_RSSI_BG2                        0x0024
4623 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4624 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4625 +
4626 +/*
4627 + * EEPROM RSSI A offset
4628 + */
4629 +#define EEPROM_RSSI_A                  0x0025
4630 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4631 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4632 +
4633 +/*
4634 + * EEPROM RSSI A2 offset
4635 + */
4636 +#define EEPROM_RSSI_A2                 0x0026
4637 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4638 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4639 +
4640 +/*
4641 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4642 + *     This is delta in 40MHZ.
4643 + * VALUE: Tx Power dalta value (MAX=4)
4644 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4645 + * TXPOWER: Enable:
4646 + */
4647 +#define EEPROM_TXPOWER_DELTA           0x0028
4648 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4649 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4650 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4651 +
4652 +/*
4653 + * EEPROM TXPOWER 802.11BG
4654 + */
4655 +#define        EEPROM_TXPOWER_BG1              0x0029
4656 +#define        EEPROM_TXPOWER_BG2              0x0030
4657 +#define EEPROM_TXPOWER_BG_SIZE         7
4658 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4659 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4660 +
4661 +/*
4662 + * EEPROM TXPOWER 802.11A
4663 + */
4664 +#define EEPROM_TXPOWER_A1              0x003c
4665 +#define EEPROM_TXPOWER_A2              0x0053
4666 +#define EEPROM_TXPOWER_A_SIZE          6
4667 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4668 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4669 +
4670 +/*
4671 + * EEPROM TXpower byrate: 20MHZ power
4672 + */
4673 +#define EEPROM_TXPOWER_BYRATE          0x006f
4674 +
4675 +/*
4676 + * EEPROM BBP.
4677 + */
4678 +#define        EEPROM_BBP_START                0x0078
4679 +#define EEPROM_BBP_SIZE                        16
4680 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4681 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4682 +
4683 +/*
4684 + * MCU mailbox commands.
4685 + */
4686 +#define MCU_SLEEP                      0x30
4687 +#define MCU_WAKEUP                     0x31
4688 +#define MCU_LED                                0x50
4689 +#define MCU_LED_STRENGTH               0x51
4690 +#define MCU_LED_1                      0x52
4691 +#define MCU_LED_2                      0x53
4692 +#define MCU_LED_3                      0x54
4693 +#define MCU_RADAR                      0x60
4694 +#define MCU_BOOT_SIGNAL                        0x72
4695 +
4696 +/*
4697 + * DMA descriptor defines.
4698 + */
4699 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4700 +#define TXINFO_DESC_SIZE               ( 1 * sizeof(__le32) )
4701 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4702 +#define RXD_DESC_SIZE                  ( 1 * sizeof(__le32) )
4703 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4704 +
4705 +/*
4706 + * TX descriptor format for TX, PRIO and Beacon Ring.
4707 + */
4708 +
4709 +/*
4710 + * Word0
4711 + */
4712 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4713 +
4714 +/*
4715 + * Word1
4716 + */
4717 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4718 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4719 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4720 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4721 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4722 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4723 +
4724 +/*
4725 + * Word2
4726 + */
4727 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4728 +
4729 +/*
4730 + * Word3
4731 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4732 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4733 + *       0:MGMT, 1:HCCA 2:EDCA
4734 + */
4735 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4736 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4737 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4738 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4739 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4740 +
4741 +/*
4742 + * TX Info structure
4743 + */
4744 +
4745 +/*
4746 + * Word0
4747 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4748 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4749 + *       0:MGMT, 1:HCCA 2:EDCA
4750 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4751 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4752 + *               Force USB DMA transmit frame from current selected endpoint
4753 + */
4754 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN   FIELD32(0x0000ffff)
4755 +#define TXINFO_W0_WIV                  FIELD32(0x01000000)
4756 +#define TXINFO_W0_QSEL                 FIELD32(0x06000000)
4757 +#define TXINFO_W0_SW_USE_LAST_ROUND    FIELD32(0x08000000)
4758 +#define TXINFO_W0_USB_DMA_NEXT_VALID   FIELD32(0x40000000)
4759 +#define TXINFO_W0_USB_DMA_TX_BURST     FIELD32(0x80000000)
4760 +
4761 +/*
4762 + * TX WI structure
4763 + */
4764 +
4765 +/*
4766 + * Word0
4767 + * FRAG: 1 To inform TKIP engine this is a fragment.
4768 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4769 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4770 + * BW: Channel bandwidth 20MHz or 40 MHz
4771 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4772 + */
4773 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4774 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4775 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4776 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4777 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4778 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4779 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4780 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4781 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4782 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4783 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4784 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4785 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4786 +
4787 +/*
4788 + * Word1
4789 + */
4790 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4791 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4792 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4793 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4794 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4795 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4796 +
4797 +/*
4798 + * Word2
4799 + */
4800 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4801 +
4802 +/*
4803 + * Word3
4804 + */
4805 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4806 +
4807 +/*
4808 + * RX descriptor format for RX Ring.
4809 + */
4810 +
4811 +/*
4812 + * Word0
4813 + * UNICAST_TO_ME: This RX frame is unicast to me.
4814 + * MULTICAST: This is a multicast frame.
4815 + * BROADCAST: This is a broadcast frame.
4816 + * MY_BSS: this frame belongs to the same BSSID.
4817 + * CRC_ERROR: CRC error.
4818 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4819 + * AMSDU: rx with 802.3 header, not 802.11 header.
4820 + */
4821 +
4822 +#define RXD_W0_BA                      FIELD32(0x00000001)
4823 +#define RXD_W0_DATA                    FIELD32(0x00000002)
4824 +#define RXD_W0_NULLDATA                        FIELD32(0x00000004)
4825 +#define RXD_W0_FRAG                    FIELD32(0x00000008)
4826 +#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000010)
4827 +#define RXD_W0_MULTICAST               FIELD32(0x00000020)
4828 +#define RXD_W0_BROADCAST               FIELD32(0x00000040)
4829 +#define RXD_W0_MY_BSS                  FIELD32(0x00000080)
4830 +#define RXD_W0_CRC_ERROR               FIELD32(0x00000100)
4831 +#define RXD_W0_CIPHER_ERROR            FIELD32(0x00000600)
4832 +#define RXD_W0_AMSDU                   FIELD32(0x00000800)
4833 +#define RXD_W0_HTC                     FIELD32(0x00001000)
4834 +#define RXD_W0_RSSI                    FIELD32(0x00002000)
4835 +#define RXD_W0_L2PAD                   FIELD32(0x00004000)
4836 +#define RXD_W0_AMPDU                   FIELD32(0x00008000)
4837 +#define RXD_W0_DECRYPTED               FIELD32(0x00010000)
4838 +#define RXD_W0_PLCP_RSSI               FIELD32(0x00020000)
4839 +#define RXD_W0_CIPHER_ALG              FIELD32(0x00040000)
4840 +#define RXD_W0_LAST_AMSDU              FIELD32(0x00080000)
4841 +#define RXD_W0_PLCP_SIGNAL             FIELD32(0xfff00000)
4842 +
4843 +/*
4844 + * RX WI structure
4845 + */
4846 +
4847 +/*
4848 + * Word0
4849 + */
4850 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4851 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4852 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4853 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4854 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4855 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4856 +
4857 +/*
4858 + * Word1
4859 + */
4860 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4861 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4862 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4863 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4864 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4865 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4866 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4867 +
4868 +/*
4869 + * Word2
4870 + */
4871 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4872 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4873 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4874 +
4875 +/*
4876 + * Word3
4877 + */
4878 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4879 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4880 +
4881 +/*
4882 + * Macro's for converting txpower from EEPROM to mac80211 value
4883 + * and from mac80211 value to register value.
4884 + */
4885 +#define MIN_G_TXPOWER  0
4886 +#define MIN_A_TXPOWER  -7
4887 +#define MAX_G_TXPOWER  31
4888 +#define MAX_A_TXPOWER  15
4889 +#define DEFAULT_TXPOWER        5
4890 +
4891 +#define TXPOWER_G_FROM_DEV(__txpower) \
4892 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4893 +
4894 +#define TXPOWER_G_TO_DEV(__txpower) \
4895 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4896 +
4897 +#define TXPOWER_A_FROM_DEV(__txpower) \
4898 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4899 +
4900 +#define TXPOWER_A_TO_DEV(__txpower) \
4901 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4902 +
4903 +#endif /* RT2800USB_H */
4904 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4905 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4906 @@ -142,6 +142,7 @@ struct rt2x00_chip {
4907  #define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
4908  #define RT2890         0x0701  /* 2.4GHz PCIe */
4909  #define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
4910 +#define RT2870         0x1600
4911
4912         u16 rf;
4913         u32 rev;
4914 @@ -780,6 +781,12 @@ struct rt2x00_dev {
4915         u8 freq_offset;
4916
4917         /*
4918 +        * Calibration information (for rt2800usb).
4919 +        */
4920 +       u8 calibration_bw20;
4921 +       u8 calibration_bw40;
4922 +
4923 +       /*
4924          * Low level statistics which will have
4925          * to be kept up to date while device is running.
4926          */