1 /******************************************************************************
4 Infineon Technologies AG
5 Am Campeon 1-12; 81726 Munich, Germany
7 For licensing information, see the file 'LICENSE' in the root folder of
10 ******************************************************************************/
13 \defgroup AMAZON_S_MEI Amazon-S MEI Driver Module
14 \brief Amazon-S MEI driver module
18 \defgroup Internal Compile Parametere
20 \brief exported functions for other driver use
24 \file amazon_s_mei_bsp.c
26 \brief Amazon-S MEI driver file
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/version.h>
32 #include <generated/utsrelease.h>
33 #include <linux/types.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioport.h>
43 #include <linux/delay.h>
44 #include <linux/device.h>
45 #include <linux/sched.h>
46 #include <asm/uaccess.h>
47 #include <asm/hardirq.h>
50 #include <lantiq_regs.h>
51 #include "ifxmips_atm.h"
53 #include "ifxmips_mei_interface.h"
55 /*#define LQ_RCU_RST IFX_RCU_RST_REQ
56 #define LQ_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG
57 #define LQ_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE
58 #define LQ_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE
59 #define IFXMIPS_FUSE_BASE_ADDR IFX_FUSE_BASE_ADDR
60 #define IFXMIPS_ICU_IM0_IER IFX_ICU_IM0_IER
61 #define IFXMIPS_ICU_IM2_IER IFX_ICU_IM2_IER
62 #define LQ_MEI_INT IFX_MEI_INT
63 #define LQ_MEI_DYING_GASP_INT IFX_MEI_DYING_GASP_INT
64 #define LQ_MEI_BASE_ADDR IFX_MEI_SPACE_ACCESS
65 #define IFXMIPS_PMU_PWDCR IFX_PMU_PWDCR
66 #define IFXMIPS_MPS_CHIPID IFX_MPS_CHIPID
68 #define ifxmips_port_reserve_pin ifx_gpio_pin_reserve
69 #define ifxmips_port_set_dir_in ifx_gpio_dir_in_set
70 #define ifxmips_port_clear_altsel0 ifx_gpio_altsel0_set
71 #define ifxmips_port_clear_altsel1 ifx_gpio_altsel1_clear
72 #define ifxmips_port_set_open_drain ifx_gpio_open_drain_clear
73 #define ifxmips_port_free_pin ifx_gpio_pin_free
74 #define ifxmips_mask_and_ack_irq bsp_mask_and_ack_irq
75 #define IFXMIPS_MPS_CHIPID_VERSION_GET IFX_MCD_CHIPID_VERSION_GET
76 #define lq_r32(reg) __raw_readl(reg)
77 #define lq_w32(val, reg) __raw_writel(val, reg)
78 #define lq_w32_mask(clear, set, reg) lq_w32((lq_r32(reg) & ~clear) | set, reg)
81 #define LQ_RCU_RST_REQ_DFE (1 << 7)
82 #define LQ_RCU_RST_REQ_AFE (1 << 11)
83 #define LQ_PMU_PWDCR ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
84 #define LQ_PMU_PWDSR ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
85 #define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
86 #define LQ_RCU_RST_ALL 0x40000000
87 #define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
89 #define LQ_ICU_IM0_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
90 #define LQ_ICU_IM0_IER ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
91 #define LQ_ICU_IM0_IOSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
92 #define LQ_ICU_IM0_IRSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
93 #define LQ_ICU_IM0_IMR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
96 #define LQ_ICU_IM1_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
97 #define LQ_ICU_IM2_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
98 #define LQ_ICU_IM3_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
99 #define LQ_ICU_IM4_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
101 #define LQ_ICU_OFFSET (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
102 #define LQ_ICU_IM2_IER (LQ_ICU_IM0_IER + LQ_ICU_OFFSET)
104 #define IFX_MEI_EMSG(fmt, args...) pr_err("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
105 #define IFX_MEI_DMSG(fmt, args...) pr_debug("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
107 #define LQ_FUSE_BASE (KSEG1 + 0x1F107354)
109 #ifdef CONFIG_LQ_MEI_FW_LOOPBACK
110 //#define DFE_MEM_TEST
111 //#define DFE_PING_TEST
112 #define DFE_ATM_LOOPBACK
115 #ifdef DFE_ATM_LOOPBACK
116 #include <asm/ifxmips/ifxmips_mei_fw_loopback.h>
119 void dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev);
121 #endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
123 DSL_DEV_Version_t bsp_mei_version = {
128 DSL_DEV_HwVersion_t bsp_chip_info;
130 #define IFX_MEI_DEVNAME "ifx_mei"
131 #define BSP_MAX_DEVICES 1
133 DSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *);
134 DSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
135 DSL_DEV_MeiError_t DSL_BSP_AdslLedInit (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
136 //DSL_DEV_MeiError_t DSL_BSP_AdslLedSet (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedMode_t);
137 DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t*, DSL_uint32_t);
138 DSL_DEV_MeiError_t DSL_BSP_SendCMV (DSL_DEV_Device_t *, u16 *, int, u16 *);
140 int DSL_BSP_KernelIoctls (DSL_DEV_Device_t *, unsigned int, unsigned long);
142 static DSL_DEV_MeiError_t IFX_MEI_RunAdslModem (DSL_DEV_Device_t *);
143 static DSL_DEV_MeiError_t IFX_MEI_CpuModeSet (DSL_DEV_Device_t *, DSL_DEV_CpuMode_t);
144 static DSL_DEV_MeiError_t IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *);
145 static DSL_DEV_MeiError_t IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *, int);
146 static DSL_DEV_MeiError_t IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *, int);
148 static int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *);
149 static int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int);
151 static ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *);
152 static int IFX_MEI_UserIoctls (DSL_DRV_inode_t *, DSL_DRV_file_t *, unsigned int, unsigned long);
153 static int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *);
154 static int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *);
156 void AMAZON_SE_MEI_ARC_MUX_Test(void);
158 #ifdef CONFIG_PROC_FS
159 static int IFX_MEI_ProcRead (struct file *, char *, size_t, loff_t *);
160 static ssize_t IFX_MEI_ProcWrite (struct file *, const char *, size_t, loff_t *);
162 #define PROC_ITEMS 11
163 #define MEI_DIRNAME "ifxmips_mei"
165 static struct proc_dir_entry *meidir;
166 static struct file_operations IFX_MEI_ProcOperations = {
167 read:IFX_MEI_ProcRead,
168 write:IFX_MEI_ProcWrite,
170 static reg_entry_t regs[BSP_MAX_DEVICES][PROC_ITEMS]; //total items to be monitored by /proc/mei
171 #define NUM_OF_REG_ENTRY (sizeof(regs[0])/sizeof(reg_entry_t))
172 #endif //CONFIG_PROC_FS
174 void IFX_MEI_ARC_MUX_Test(void);
176 static int adsl_dummy_ledcallback(void);
178 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
179 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
181 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
182 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
184 static int (*g_adsl_ledcallback)(void) = adsl_dummy_ledcallback;
186 static unsigned int g_tx_link_rate[2] = {0};
188 static void *g_xdata_addr = NULL;
190 static u32 *mei_arc_swap_buff = NULL; // holding swap pages
192 extern void lq_mask_and_ack_irq(unsigned int irq_nr);
193 #define MEI_MASK_AND_ACK_IRQ lq_mask_and_ack_irq
195 #define MEI_MAJOR 105
196 static int dev_major = MEI_MAJOR;
198 static struct file_operations bsp_mei_operations = {
201 release:IFX_MEI_Release,
203 ioctl:IFX_MEI_UserIoctls,
206 static DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES];
208 static ifx_mei_device_private_t
209 sDanube_Mei_Private[BSP_MAX_DEVICES];
211 static DSL_BSP_EventCallBack_t dsl_bsp_event_callback[DSL_BSP_CB_LAST + 1];
214 * Write a value to register
215 * This function writes a value to danube register
217 * \param ul_address The address to write
218 * \param ul_data The value to write
222 IFX_MEI_LongWordWrite (u32 ul_address, u32 ul_data)
224 IFX_MEI_WRITE_REGISTER_L (ul_data, ul_address);
230 * Write a value to register
231 * This function writes a value to danube register
233 * \param pDev the device pointer
234 * \param ul_address The address to write
235 * \param ul_data The value to write
239 IFX_MEI_LongWordWriteOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
242 IFX_MEI_WRITE_REGISTER_L (ul_data, pDev->base_address + ul_address);
248 * Read the danube register
249 * This function read the value from danube register
251 * \param ul_address The address to write
252 * \param pul_data Pointer to the data
256 IFX_MEI_LongWordRead (u32 ul_address, u32 * pul_data)
258 *pul_data = IFX_MEI_READ_REGISTER_L (ul_address);
264 * Read the danube register
265 * This function read the value from danube register
267 * \param pDev the device pointer
268 * \param ul_address The address to write
269 * \param pul_data Pointer to the data
273 IFX_MEI_LongWordReadOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
276 *pul_data = IFX_MEI_READ_REGISTER_L (pDev->base_address + ul_address);
282 * Write several DWORD datas to ARC memory via ARC DMA interface
283 * This function writes several DWORD datas to ARC memory via DMA interface.
285 * \param pDev the device pointer
286 * \param destaddr The address to write
287 * \param databuff Pointer to the data buffer
288 * \param databuffsize Number of DWORDs to write
289 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
292 static DSL_DEV_MeiError_t
293 IFX_MEI_DMAWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
294 u32 * databuff, u32 databuffsize)
300 return DSL_DEV_MEI_ERR_FAILURE;
302 // Set the write transfer address
303 IFX_MEI_LongWordWriteOffset (pDev, ME_DX_AD, destaddr);
305 // Write the data pushed across DMA
306 while (databuffsize--) {
308 if (destaddr == MEI_TO_ARC_MAILBOX)
309 MEI_HALF_WORD_SWAP (temp);
310 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_DATA, temp);
314 return DSL_DEV_MEI_ERR_SUCCESS;
319 * Read several DWORD datas from ARC memory via ARC DMA interface
320 * This function reads several DWORD datas from ARC memory via DMA interface.
322 * \param pDev the device pointer
323 * \param srcaddr The address to read
324 * \param databuff Pointer to the data buffer
325 * \param databuffsize Number of DWORDs to read
326 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
329 static DSL_DEV_MeiError_t
330 IFX_MEI_DMARead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff,
337 return DSL_DEV_MEI_ERR_FAILURE;
339 // Set the read transfer address
340 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_AD, srcaddr);
342 // Read the data popped across DMA
343 while (databuffsize--) {
344 IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DX_DATA, &temp);
345 if (databuff == (u32 *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg) // swap half word
346 MEI_HALF_WORD_SWAP (temp);
351 return DSL_DEV_MEI_ERR_SUCCESS;
356 * Switch the ARC control mode
357 * This function switchs the ARC control mode to JTAG mode or MEI mode
359 * \param pDev the device pointer
360 * \param mode The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE.
364 IFX_MEI_ControlModeSet (DSL_DEV_Device_t * pDev, int mode)
368 IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_MASTER, &temp);
370 case JTAG_MASTER_MODE:
371 temp &= ~(HOST_MSTR);
373 case MEI_MASTER_MODE:
377 IFX_MEI_EMSG ("IFX_MEI_ControlModeSet: unkonwn mode [%d]\n", mode);
380 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_MASTER, temp);
384 * Disable ARC to MEI interrupt
386 * \param pDev the device pointer
390 IFX_MEI_IRQDisable (DSL_DEV_Device_t * pDev)
392 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, 0x0);
396 * Eable ARC to MEI interrupt
398 * \param pDev the device pointer
402 IFX_MEI_IRQEnable (DSL_DEV_Device_t * pDev)
404 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, MSGAV_EN);
408 * Poll for transaction complete signal
409 * This function polls and waits for transaction complete signal.
411 * \param pDev the device pointer
415 meiPollForDbgDone (DSL_DEV_Device_t * pDev)
420 while (i < WHILE_DELAY) {
421 IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ARC2ME_STAT, &query);
422 query &= (ARC_TO_MEI_DBG_DONE);
426 if (i == WHILE_DELAY) {
427 IFX_MEI_EMSG ("PollforDbg fail!\n");
430 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt
434 * ARC Debug Memory Access for a single DWORD reading.
435 * This function used for direct, address-based access to ARC memory.
437 * \param pDev the device pointer
438 * \param DEC_mode ARC memory space to used
439 * \param address Address to read
440 * \param data Pointer to data
441 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
444 static DSL_DEV_MeiError_t
445 _IFX_MEI_DBGLongWordRead (DSL_DEV_Device_t * pDev, u32 DEC_mode,
446 u32 address, u32 * data)
448 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
449 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_RD_AD, address);
450 meiPollForDbgDone (pDev);
451 IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_DATA, data);
452 return DSL_DEV_MEI_ERR_SUCCESS;
456 * ARC Debug Memory Access for a single DWORD writing.
457 * This function used for direct, address-based access to ARC memory.
459 * \param pDev the device pointer
460 * \param DEC_mode ARC memory space to used
461 * \param address The address to write
462 * \param data The data to write
463 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
466 static DSL_DEV_MeiError_t
467 _IFX_MEI_DBGLongWordWrite (DSL_DEV_Device_t * pDev, u32 DEC_mode,
468 u32 address, u32 data)
470 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
471 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_WR_AD, address);
472 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DATA, data);
473 meiPollForDbgDone (pDev);
474 return DSL_DEV_MEI_ERR_SUCCESS;
478 * ARC Debug Memory Access for writing.
479 * This function used for direct, address-based access to ARC memory.
481 * \param pDev the device pointer
482 * \param destaddr The address to read
483 * \param databuffer Pointer to data
484 * \param databuffsize The number of DWORDs to read
485 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
489 static DSL_DEV_MeiError_t
490 IFX_MEI_DebugWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
491 u32 * databuff, u32 databuffsize)
498 // Open the debug port before DMP memory write
499 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
501 // For the requested length, write the address and write the data
504 for (i = 0; i < databuffsize; i++) {
506 _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, address, temp);
511 // Close the debug port after DMP memory write
512 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
514 return DSL_DEV_MEI_ERR_SUCCESS;
518 * ARC Debug Memory Access for reading.
519 * This function used for direct, address-based access to ARC memory.
521 * \param pDev the device pointer
522 * \param srcaddr The address to read
523 * \param databuffer Pointer to data
524 * \param databuffsize The number of DWORDs to read
525 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
528 static DSL_DEV_MeiError_t
529 IFX_MEI_DebugRead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, u32 databuffsize)
536 // Open the debug port before DMP memory read
537 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
539 // For the requested length, write the address and read the data
542 for (i = 0; i < databuffsize; i++) {
543 _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, address, &temp);
549 // Close the debug port after DMP memory read
550 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
552 return DSL_DEV_MEI_ERR_SUCCESS;
556 * Send a message to ARC MailBox.
557 * This function sends a message to ARC Mailbox via ARC DMA interface.
559 * \param pDev the device pointer
560 * \param msgsrcbuffer Pointer to message.
561 * \param msgsize The number of words to write.
562 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
565 static DSL_DEV_MeiError_t
566 IFX_MEI_MailboxWrite (DSL_DEV_Device_t * pDev, u16 * msgsrcbuffer,
570 u32 arc_mailbox_status = 0x0;
572 DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;
576 IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, msgsize / 2);
578 IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1);
580 // Notify arc that mailbox write completed
581 DSL_DEV_PRIVATE(pDev)->cmv_waiting = 1;
582 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
585 while (i < WHILE_DELAY) { // wait for ARC to clear the bit
586 IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ME2ARC_INT, &arc_mailbox_status);
587 if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV)
590 if (i == WHILE_DELAY) {
591 IFX_MEI_EMSG (">>> Timeout waiting for ARC to clear MEI_TO_ARC_MSGAV!!!"
592 " MEI_TO_ARC message size = %d DWORDs <<<\n", msgsize/2);
593 meiMailboxError = DSL_DEV_MEI_ERR_FAILURE;
597 return meiMailboxError;
601 * Read a message from ARC MailBox.
602 * This function reads a message from ARC Mailbox via ARC DMA interface.
604 * \param pDev the device pointer
605 * \param msgsrcbuffer Pointer to message.
606 * \param msgsize The number of words to read
607 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
610 static DSL_DEV_MeiError_t
611 IFX_MEI_MailboxRead (DSL_DEV_Device_t * pDev, u16 * msgdestbuffer,
614 DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;
617 IFX_MEI_DMARead (pDev, ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, msgsize / 2);
619 // Notify arc that mailbox read completed
620 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
622 return meiMailboxError;
626 * Download boot pages to ARC.
627 * This function downloads boot pages to ARC.
629 * \param pDev the device pointer
630 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
633 static DSL_DEV_MeiError_t
634 IFX_MEI_DownloadBootPages (DSL_DEV_Device_t * pDev)
641 ** DMA the boot code page(s)
646 (DSL_DEV_PRIVATE(pDev)->img_hdr-> count); boot_loop++) {
647 if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].p_size) & BOOT_FLAG) {
648 page_size = IFX_MEI_GetPage (pDev, boot_loop,
649 GET_PROG, MAXSWAPSIZE,
653 IFX_MEI_DMAWrite (pDev, dest_addr,
658 if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].d_size) & BOOT_FLAG) {
659 page_size = IFX_MEI_GetPage (pDev, boot_loop,
660 GET_DATA, MAXSWAPSIZE,
664 IFX_MEI_DMAWrite (pDev, dest_addr,
670 return DSL_DEV_MEI_ERR_SUCCESS;
677 IFX_MEI_FuseInit (DSL_DEV_Device_t * pDev)
680 IFX_MEI_DMAWrite (pDev, IRAM0_BASE, &data, 1);
681 IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &data, 1);
682 IFX_MEI_DMAWrite (pDev, IRAM1_BASE, &data, 1);
683 IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &data, 1);
684 IFX_MEI_DMAWrite (pDev, BRAM_BASE, &data, 1);
685 IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &data, 1);
686 IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &data, 1);
687 IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &data, 1);
694 IFX_MEI_FuseProg (DSL_DEV_Device_t * pDev)
696 u32 reg_data, fuse_value;
699 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
700 while ((reg_data & 0x10000000) == 0) {
701 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
703 /* 0x4000 translate to about 16 ms@111M, so should be enough */
707 // STEP a: Prepare memory for external accesses
708 // Write fuse_en bit24
709 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
710 IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data | (1 << 24));
712 IFX_MEI_FuseInit (pDev);
713 for (i = 0; i < 4; i++) {
714 IFX_MEI_LongWordRead ((u32) (LQ_FUSE_BASE) + i * 4, &fuse_value);
715 switch (fuse_value & 0xF0000) {
717 reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
718 (RX_DILV_ADDR_BIT_MASK + 0x1));
719 IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, ®_data, 1);
722 reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
723 (RX_DILV_ADDR_BIT_MASK + 0x1));
724 IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, ®_data, 1);
727 reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
728 (IRAM0_ADDR_BIT_MASK + 0x1));
729 IFX_MEI_DMAWrite (pDev, IRAM0_BASE, ®_data, 1);
732 reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
733 (IRAM0_ADDR_BIT_MASK + 0x1));
734 IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, ®_data, 1);
737 reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
738 (IRAM1_ADDR_BIT_MASK + 0x1));
739 IFX_MEI_DMAWrite (pDev, IRAM1_BASE, ®_data, 1);
742 reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
743 (IRAM1_ADDR_BIT_MASK + 0x1));
744 IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, ®_data, 1);
747 reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
748 (BRAM_ADDR_BIT_MASK + 0x1));
749 IFX_MEI_DMAWrite (pDev, BRAM_BASE, ®_data, 1);
752 reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
753 (BRAM_ADDR_BIT_MASK + 0x1));
754 IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, ®_data, 1);
756 default: // PPE efuse
760 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
761 IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data & ~(1 << 24));
762 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
767 * This function enables DFE Clock
769 * \param pDev the device pointer
770 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
773 static DSL_DEV_MeiError_t
774 IFX_MEI_EnableCLK (DSL_DEV_Device_t * pDev)
776 u32 arc_debug_data = 0;
777 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
778 //enable ac_clk signal
779 _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK,
780 CRI_CCR0, &arc_debug_data);
781 arc_debug_data |= ACL_CLK_MODE_ENABLE;
782 _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK,
783 CRI_CCR0, arc_debug_data);
784 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
785 return DSL_DEV_MEI_ERR_SUCCESS;
790 * This function halts the ARC.
792 * \param pDev the device pointer
793 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
796 static DSL_DEV_MeiError_t
797 IFX_MEI_HaltArc (DSL_DEV_Device_t * pDev)
799 u32 arc_debug_data = 0x0;
801 // Switch arc control from JTAG mode to MEI mode
802 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
803 _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
804 ARC_DEBUG, &arc_debug_data);
805 arc_debug_data |= ARC_DEBUG_HALT;
806 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
807 ARC_DEBUG, arc_debug_data);
808 // Switch arc control from MEI mode to JTAG mode
809 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
813 return DSL_DEV_MEI_ERR_SUCCESS;
818 * This function runs the ARC.
820 * \param pDev the device pointer
821 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
824 static DSL_DEV_MeiError_t
825 IFX_MEI_RunArc (DSL_DEV_Device_t * pDev)
827 u32 arc_debug_data = 0x0;
829 // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
830 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
831 _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
832 AUX_STATUS, &arc_debug_data);
834 // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)
835 arc_debug_data &= ~ARC_AUX_HALT;
836 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
837 AUX_STATUS, arc_debug_data);
839 // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
840 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
841 // Enable mask for arc codeswap interrupts
842 IFX_MEI_IRQEnable (pDev);
844 return DSL_DEV_MEI_ERR_SUCCESS;
850 * This function resets the ARC.
852 * \param pDev the device pointer
853 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
856 static DSL_DEV_MeiError_t
857 IFX_MEI_ResetARC (DSL_DEV_Device_t * pDev)
859 u32 arc_debug_data = 0;
861 IFX_MEI_HaltArc (pDev);
863 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &arc_debug_data);
864 IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST,
865 arc_debug_data | LQ_RCU_RST_REQ_DFE | LQ_RCU_RST_REQ_AFE);
868 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, MEI_SOFT_RESET);
869 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, 0);
871 IFX_MEI_IRQDisable (pDev);
873 IFX_MEI_EnableCLK (pDev);
877 *(unsigned long *) (BSP_PPE32_SRST) = 0xC30;
878 *(unsigned long *) (BSP_PPE32_SRST) = 0xFFF;
881 DSL_DEV_PRIVATE(pDev)->modem_ready = 0;
883 return DSL_DEV_MEI_ERR_SUCCESS;
887 DSL_BSP_Showtime (DSL_DEV_Device_t * dev, DSL_uint32_t rate_fast, DSL_uint32_t rate_intl)
889 struct port_cell_info port_cell = {0};
891 IFX_MEI_EMSG ("Datarate US intl = %d, fast = %d\n", (int)rate_intl,
895 g_tx_link_rate[0] = rate_fast / (53 * 8);
897 g_tx_link_rate[1] = rate_intl / (53 * 8);
899 if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) {
900 IFX_MEI_EMSG ("Got rate fail.\n");
903 if ( ifx_mei_atm_showtime_enter )
905 port_cell.port_num = 2;
906 port_cell.tx_link_rate[0] = g_tx_link_rate[0];
907 port_cell.tx_link_rate[1] = g_tx_link_rate[1];
908 ifx_mei_atm_showtime_enter(&port_cell, g_xdata_addr);
912 IFX_MEI_EMSG("no hookup from ATM driver to set cell rate\n");
915 return DSL_DEV_MEI_ERR_SUCCESS;
919 * Reset/halt/run the DFE.
920 * This function provide operations to reset/halt/run the DFE.
922 * \param pDev the device pointer
923 * \param mode which operation want to do
924 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
927 static DSL_DEV_MeiError_t
928 IFX_MEI_CpuModeSet (DSL_DEV_Device_t *pDev,
929 DSL_DEV_CpuMode_t mode)
931 DSL_DEV_MeiError_t err_ret = DSL_DEV_MEI_ERR_FAILURE;
934 err_ret = IFX_MEI_HaltArc (pDev);
937 err_ret = IFX_MEI_RunArc (pDev);
940 err_ret = IFX_MEI_ResetARC (pDev);
949 * Accress DFE memory.
950 * This function provide a way to access DFE memory;
952 * \param pDev the device pointer
953 * \param type read or write
954 * \param destaddr destination address
955 * \param databuff pointer to hold data
956 * \param databuffsize size want to read/write
957 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
961 DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t * pDev,
962 DSL_BSP_MemoryAccessType_t type,
963 DSL_uint32_t destaddr, DSL_uint32_t *databuff,
964 DSL_uint32_t databuffsize)
966 DSL_DEV_MeiError_t meierr = DSL_DEV_MEI_ERR_SUCCESS;
968 case DSL_BSP_MEMORY_READ:
969 meierr = IFX_MEI_DebugRead (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
971 case DSL_BSP_MEMORY_WRITE:
972 meierr = IFX_MEI_DebugWrite (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
975 return DSL_DEV_MEI_ERR_SUCCESS;
979 * Download boot code to ARC.
980 * This function downloads boot code to ARC.
982 * \param pDev the device pointer
983 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
986 static DSL_DEV_MeiError_t
987 IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *pDev)
989 IFX_MEI_IRQDisable (pDev);
991 IFX_MEI_EnableCLK (pDev);
993 IFX_MEI_FuseProg (pDev); //program fuse rar
995 IFX_MEI_DownloadBootPages (pDev);
997 return DSL_DEV_MEI_ERR_SUCCESS;
1001 * Enable Jtag debugger interface
1002 * This function setups mips gpio to enable jtag debugger
1004 * \param pDev the device pointer
1005 * \param enable enable or disable
1006 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
1009 static DSL_DEV_MeiError_t
1010 IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *dev, int enable)
1017 //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG
1018 ifxmips_port_reserve_pin (0, 9);
1019 ifxmips_port_reserve_pin (0, 10);
1020 ifxmips_port_reserve_pin (0, 11);
1021 ifxmips_port_reserve_pin (0, 14);
1022 ifxmips_port_reserve_pin (1, 3);
1024 ifxmips_port_set_dir_in(0, 11);
1025 ifxmips_port_clear_altsel0(0, 11);
1026 ifxmips_port_clear_altsel1(0, 11);
1027 ifxmips_port_set_open_drain(0, 11);
1029 IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, ®_data);
1030 IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data | LQ_RCU_RST_REQ_ARC_JTAG);
1038 return DSL_DEV_MEI_ERR_FAILURE;
1040 printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1041 printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1043 return DSL_DEV_MEI_ERR_SUCCESS;
1047 * Enable DFE to MIPS interrupt
1048 * This function enable DFE to MIPS interrupt
1050 * \param pDev the device pointer
1051 * \param enable enable or disable
1052 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
1055 static DSL_DEV_MeiError_t
1056 IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *pDev, int enable)
1058 DSL_DEV_MeiError_t meierr;
1061 meierr = DSL_DEV_MEI_ERR_SUCCESS;
1062 IFX_MEI_IRQDisable (pDev);
1065 IFX_MEI_IRQEnable (pDev);
1066 meierr = DSL_DEV_MEI_ERR_SUCCESS;
1069 meierr = DSL_DEV_MEI_ERR_FAILURE;
1077 * Get the modem status
1078 * This function return the modem status
1080 * \param pDev the device pointer
1081 * \return 1: modem ready 0: not ready
1085 IFX_MEI_IsModemReady (DSL_DEV_Device_t * pDev)
1087 return DSL_DEV_PRIVATE(pDev)->modem_ready;
1091 DSL_BSP_AdslLedInit (DSL_DEV_Device_t * dev,
1092 DSL_DEV_LedId_t led_number,
1093 DSL_DEV_LedType_t type,
1094 DSL_DEV_LedHandler_t handler)
1097 struct led_config_param param;
1098 if (led_number == DSL_LED_LINK_ID && type == DSL_LED_LINK_TYPE && handler == /*DSL_LED_HD_CPU*/DSL_LED_HD_FW) {
1099 param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
1101 param.source = 0x01;
1102 // bsp_led_config (¶m);
1104 } else if (led_number == DSL_LED_DATA_ID && type == DSL_LED_DATA_TYPE && (handler == DSL_LED_HD_FW)) {
1105 param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
1107 param.source = 0x02;
1108 // bsp_led_config (¶m);
1111 return DSL_DEV_MEI_ERR_SUCCESS;
1115 DSL_BSP_AdslLedSet (DSL_DEV_Device_t * dev, DSL_DEV_LedId_t led_number, DSL_DEV_LedMode_t mode)
1117 printk(KERN_INFO "[%s %d]: mode = %#x, led_number = %d\n", __func__, __LINE__, mode, led_number);
1120 switch (led_number) {
1121 case DSL_LED_LINK_ID:
1122 #ifdef CONFIG_BSP_LED
1123 bsp_led_set_blink (1, 0);
1124 bsp_led_set_data (1, 0);
1127 case DSL_LED_DATA_ID:
1128 #ifdef CONFIG_BSP_LED
1129 bsp_led_set_blink (0, 0);
1130 bsp_led_set_data (0, 0);
1136 switch (led_number) {
1137 case DSL_LED_LINK_ID:
1138 #ifdef CONFIG_BSP_LED
1139 bsp_led_set_blink (1, 1); // data
1142 case DSL_LED_DATA_ID:
1143 #ifdef CONFIG_BSP_LED
1144 bsp_led_set_blink (0, 1); // data
1150 switch (led_number) {
1151 case DSL_LED_LINK_ID:
1152 #ifdef CONFIG_BSP_LED
1153 bsp_led_set_blink (1, 0);
1154 bsp_led_set_data (1, 1);
1157 case DSL_LED_DATA_ID:
1158 #ifdef CONFIG_BSP_LED
1159 bsp_led_set_blink (0, 0);
1160 bsp_led_set_data (0, 1);
1166 return DSL_DEV_MEI_ERR_SUCCESS;
1172 * Compose a message.
1173 * This function compose a message from opcode, group, address, index, size, and data
1175 * \param opcode The message opcode
1176 * \param group The message group number
1177 * \param address The message address.
1178 * \param index The message index.
1179 * \param size The number of words to read/write.
1180 * \param data The pointer to data.
1181 * \param CMVMSG The pointer to message buffer.
1185 makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 *CMVMSG)
1187 memset (CMVMSG, 0, MSG_LENGTH * 2);
1188 CMVMSG[0] = (opcode << 4) + (size & 0xf);
1189 CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f);
1190 CMVMSG[2] = address;
1192 if (opcode == H2D_CMV_WRITE)
1193 memcpy (CMVMSG + 4, data, size * 2);
1198 * Send a message to ARC and read the response
1199 * This function sends a message to arc, waits the response, and reads the responses.
1201 * \param pDev the device pointer
1202 * \param request Pointer to the request
1203 * \param reply Wait reply or not.
1204 * \param response Pointer to the response
1205 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
1209 DSL_BSP_SendCMV (DSL_DEV_Device_t * pDev, u16 * request, int reply, u16 * response) // write cmv to arc, if reply needed, wait for reply
1211 DSL_DEV_MeiError_t meierror;
1212 #if defined(BSP_PORT_RTEMS)
1213 int delay_counter = 0;
1216 if (MEI_MUTEX_LOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema))
1217 return -ERESTARTSYS;
1219 DSL_DEV_PRIVATE(pDev)->cmv_reply = reply;
1220 memset (DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, 0,
1221 sizeof (DSL_DEV_PRIVATE(pDev)->
1223 DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
1225 meierror = IFX_MEI_MailboxWrite (pDev, request, MSG_LENGTH);
1227 if (meierror != DSL_DEV_MEI_ERR_SUCCESS) {
1228 DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
1229 DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
1230 IFX_MEI_EMSG ("MailboxWrite Fail!\n");
1231 IFX_MEI_EMSG ("Resetting ARC...\n");
1232 IFX_MEI_ResetARC(pDev);
1233 MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
1237 DSL_DEV_PRIVATE(pDev)->cmv_count++;
1240 if (DSL_DEV_PRIVATE(pDev)->cmv_reply ==
1242 MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
1243 return DSL_DEV_MEI_ERR_SUCCESS;
1246 #if !defined(BSP_PORT_RTEMS)
1247 if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0)
1248 MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav, CMV_TIMEOUT);
1250 while (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) {
1256 DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
1257 if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) { //CMV_timeout
1258 DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
1259 IFX_MEI_EMSG ("\%s: DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT\n",
1261 MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
1262 return DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT;
1265 DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
1266 DSL_DEV_PRIVATE(pDev)->
1268 memcpy (response, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
1269 MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
1270 return DSL_DEV_MEI_ERR_SUCCESS;
1272 MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
1273 return DSL_DEV_MEI_ERR_SUCCESS;
1277 * Reset the ARC, download boot codes, and run the ARC.
1278 * This function resets the ARC, downloads boot codes to ARC, and runs the ARC.
1280 * \param pDev the device pointer
1281 * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
1284 static DSL_DEV_MeiError_t
1285 IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev)
1287 int nSize = 0, idx = 0;
1288 uint32_t im0_register, im2_register;
1289 // DSL_DEV_WinHost_Message_t m;
1291 if (mei_arc_swap_buff == NULL) {
1293 (u32 *) kmalloc (MAXSWAPSIZE * 4, GFP_KERNEL);
1294 if (mei_arc_swap_buff == NULL) {
1295 IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n");
1296 return DSL_DEV_MEI_ERR_FAILURE;
1298 IFX_MEI_DMSG("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
1301 DSL_DEV_PRIVATE(pDev)->img_hdr =
1302 (ARC_IMG_HDR *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[0].address;
1303 if ((DSL_DEV_PRIVATE(pDev)->img_hdr->
1304 count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) {
1305 IFX_MEI_EMSG ("firmware header size is bigger than 64K segment size\n");
1306 return DSL_DEV_MEI_ERR_FAILURE;
1309 for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
1310 nSize += DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].nCopy;
1313 DSL_DEV_PRIVATE(pDev)->image_size) {
1314 IFX_MEI_EMSG ("Firmware download is not completed. Please download firmware again!\n");
1315 return DSL_DEV_MEI_ERR_FAILURE;
1320 IFX_MEI_ResetARC (pDev);
1321 IFX_MEI_HaltArc (pDev);
1322 IFX_MEI_BarUpdate (pDev, DSL_DEV_PRIVATE(pDev)->nBar);
1324 //IFX_MEI_DMSG("Starting to meiDownloadBootCode\n");
1326 IFX_MEI_DownloadBootCode (pDev);
1328 im0_register = (*LQ_ICU_IM0_IER) & (1 << 20);
1329 im2_register = (*LQ_ICU_IM2_IER) & (1 << 20);
1331 #ifdef CONFIG_LANTIQ_AMAZON_SE
1332 disable_irq (IFXMIPS_USB_OC_INT0);
1333 disable_irq (IFXMIPS_USB_OC_INT2);
1334 #elif defined(CONFIG_LANTIQ_AR9)
1335 disable_irq (IFXMIPS_USB_OC_INT0);
1336 disable_irq (IFXMIPS_USB_OC_INT2);
1337 #elif defined(CONFIG_SOC_LANTIQ_XWAY)
1338 disable_irq (LQ_USB_OC_INT);
1342 disable_irq (pDev->nIrq[IFX_DYING_GASP]);
1344 IFX_MEI_RunArc (pDev);
1346 MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000);
1348 #ifdef CONFIG_LANTIQ_AMAZON_SE
1349 MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
1350 MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
1351 #elif defined(CONFIG_LANTIQ_AMAZON_S)
1352 MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
1353 MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
1354 #elif defined(CONFIG_SOC_LANTIQ_XWAY)
1355 MEI_MASK_AND_ACK_IRQ (LQ_USB_OC_INT);
1359 MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
1362 enable_irq(pDev->nIrq[IFX_DYING_GASP]);
1363 *LQ_ICU_IM0_IER |= im0_register;
1364 *LQ_ICU_IM2_IER |= im2_register;
1366 if (DSL_DEV_PRIVATE(pDev)->modem_ready != 1) {
1367 IFX_MEI_EMSG ("Modem failed to be ready!\n");
1368 return DSL_DEV_MEI_ERR_FAILURE;
1370 IFX_MEI_DMSG("Modem is ready.\n");
1371 return DSL_DEV_MEI_ERR_SUCCESS;
1376 * Get the page's data pointer
1377 * This function caculats the data address from the firmware header.
1379 * \param pDev the device pointer
1380 * \param Page The page number.
1381 * \param data Data page or program page.
1382 * \param MaxSize The maximum size to read.
1383 * \param Buffer Pointer to data.
1384 * \param Dest Pointer to the destination address.
1385 * \return The number of bytes to read.
1389 IFX_MEI_GetPage (DSL_DEV_Device_t * pDev, u32 Page, u32 data,
1390 u32 MaxSize, u32 * Buffer, u32 * Dest)
1395 u32 idx, offset, nBar = 0;
1397 if (Page > DSL_DEV_PRIVATE(pDev)->img_hdr->count)
1400 ** Get program or data size, depending on "data" flag
1402 size = (data == GET_DATA) ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_size) :
1403 (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_size);
1404 size &= BOOT_FLAG_MASK; // Clear boot bit!
1411 ** Get program or data offset, depending on "data" flag
1413 i = data ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_offset) :
1414 (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_offset);
1417 ** Copy data/program to buffer
1420 idx = i / SDRAM_SEGMENT_SIZE;
1421 offset = i % SDRAM_SEGMENT_SIZE;
1422 p = (u32 *) ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address + offset);
1424 for (i = 0; i < size; i++) {
1425 if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= SDRAM_SEGMENT_SIZE) {
1428 p = (u32 *) ((u8 *) KSEG1ADDR ((u32)DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address));
1434 ** Pass back data/program destination address
1436 *Dest = data ? (DSL_DEV_PRIVATE(pDev)-> img_hdr->page[Page].d_dest) :
1437 (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_dest);
1443 * Free the memory for ARC firmware
1445 * \param pDev the device pointer
1446 * \param type Free all memory or free the unused memory after showtime
1449 const char *free_str[4] = {"Invalid", "Free_Reload", "Free_Showtime", "Free_All"};
1451 IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t * pDev, int type)
1454 smmu_mem_info_t *adsl_mem_info =
1455 DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
1457 for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
1458 if (type == FREE_ALL ||adsl_mem_info[idx].type == type) {
1459 if (adsl_mem_info[idx].size > 0) {
1460 IFX_MEI_DMSG ("Freeing memory %p (%s)\n", adsl_mem_info[idx].org_address, free_str[adsl_mem_info[idx].type]);
1461 if ( idx == XDATA_REGISTER ) {
1462 g_xdata_addr = NULL;
1463 if ( ifx_mei_atm_showtime_exit )
1464 ifx_mei_atm_showtime_exit();
1466 kfree (adsl_mem_info[idx].org_address);
1467 adsl_mem_info[idx].org_address = 0;
1468 adsl_mem_info[idx].address = 0;
1469 adsl_mem_info[idx].size = 0;
1470 adsl_mem_info[idx].type = 0;
1471 adsl_mem_info[idx].nCopy = 0;
1476 if(mei_arc_swap_buff != NULL){
1477 IFX_MEI_DMSG("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
1478 kfree(mei_arc_swap_buff);
1479 mei_arc_swap_buff=NULL;
1485 IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size)
1487 unsigned long mem_ptr;
1488 char *org_mem_ptr = NULL;
1490 long total_size = 0;
1492 smmu_mem_info_t *adsl_mem_info =
1493 ((ifx_mei_device_private_t *) pDev->pPriv)->adsl_mem_info;
1494 // DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
1495 int allocate_size = SDRAM_SEGMENT_SIZE;
1497 IFX_MEI_DMSG("image_size = %ld\n", size);
1499 for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) {
1500 // skip bar15 for XDATA usage.
1501 if (idx == XDATA_REGISTER)
1504 if (size < SDRAM_SEGMENT_SIZE) {
1505 allocate_size = size;
1506 if (allocate_size < 1024)
1507 allocate_size = 1024;
1510 if (idx == (MAX_BAR_REGISTERS - 1))
1511 allocate_size = size;
1513 allocate_size = SDRAM_SEGMENT_SIZE;
1514 org_mem_ptr = kmalloc (allocate_size + 1024, GFP_KERNEL);
1515 if (org_mem_ptr == NULL) {
1516 IFX_MEI_EMSG ("%d: kmalloc %d bytes memory fail!\n", idx, allocate_size);
1518 goto allocate_error;
1520 mem_ptr = (unsigned long) (org_mem_ptr + 1023) & ~(1024 -1);
1521 adsl_mem_info[idx].address = (char *) mem_ptr;
1522 adsl_mem_info[idx].org_address = org_mem_ptr;
1523 adsl_mem_info[idx].size = allocate_size;
1524 size -= allocate_size;
1525 total_size += allocate_size;
1528 IFX_MEI_EMSG ("Image size is too large!\n");
1530 goto allocate_error;
1536 IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
1541 * Program the BAR registers
1543 * \param pDev the device pointer
1544 * \param nTotalBar The number of bar to program.
1548 IFX_MEI_BarUpdate (DSL_DEV_Device_t * pDev, int nTotalBar)
1551 smmu_mem_info_t *adsl_mem_info =
1552 DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
1554 for (idx = 0; idx < nTotalBar; idx++) {
1555 //skip XDATA register
1556 if (idx == XDATA_REGISTER)
1558 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,
1559 (((uint32_t) adsl_mem_info[idx].address) & 0x0FFFFFFF));
1561 for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) {
1562 if (idx == XDATA_REGISTER)
1564 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,
1565 (((uint32_t)adsl_mem_info[nTotalBar - 1].address) & 0x0FFFFFFF));
1566 /* These are for /proc/danube_mei/meminfo purpose */
1567 adsl_mem_info[idx].address = adsl_mem_info[nTotalBar - 1].address;
1568 adsl_mem_info[idx].org_address = adsl_mem_info[nTotalBar - 1].org_address;
1569 adsl_mem_info[idx].size = 0; /* Prevent it from being freed */
1572 g_xdata_addr = adsl_mem_info[XDATA_REGISTER].address;
1573 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + XDATA_REGISTER * 4,
1574 (((uint32_t) adsl_mem_info [XDATA_REGISTER].address) & 0x0FFFFFFF));
1575 // update MEI_XDATA_BASE_SH
1576 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
1577 ((unsigned long)adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);
1579 return DSL_DEV_MEI_ERR_SUCCESS;
1582 /* This copies the firmware from secondary storage to 64k memory segment in SDRAM */
1584 DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf,
1585 unsigned long size, long *loff, long *current_offset)
1587 ARC_IMG_HDR img_hdr_tmp;
1588 smmu_mem_info_t *adsl_mem_info = DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
1590 size_t nRead = 0, nCopy = 0;
1592 ssize_t retval = -ENOMEM;
1598 if (size < sizeof (img_hdr_tmp)) {
1599 IFX_MEI_EMSG ("Firmware size is too small!\n");
1602 copy_from_user ((char *) &img_hdr_tmp, buf, sizeof (img_hdr_tmp));
1603 // header of image_size and crc are not included.
1604 DSL_DEV_PRIVATE(pDev)->image_size = le32_to_cpu (img_hdr_tmp.size) + 8;
1606 if (DSL_DEV_PRIVATE(pDev)->image_size > 1024 * 1024) {
1607 IFX_MEI_EMSG ("Firmware size is too large!\n");
1610 // check if arc is halt
1611 IFX_MEI_ResetARC (pDev);
1612 IFX_MEI_HaltArc (pDev);
1614 IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); //free all
1616 retval = IFX_MEI_DFEMemoryAlloc (pDev, DSL_DEV_PRIVATE(pDev)->image_size);
1618 IFX_MEI_EMSG ("Error: No memory space left.\n");
1621 for (idx = 0; idx < retval; idx++) {
1622 //skip XDATA register
1623 if (idx == XDATA_REGISTER)
1625 if (idx * SDRAM_SEGMENT_SIZE < le32_to_cpu (img_hdr_tmp.page[0].p_offset))
1626 adsl_mem_info[idx].type = FREE_RELOAD;
1628 adsl_mem_info[idx].type = FREE_SHOWTIME;
1630 DSL_DEV_PRIVATE(pDev)->nBar = retval;
1632 DSL_DEV_PRIVATE(pDev)->img_hdr =
1633 (ARC_IMG_HDR *) adsl_mem_info[0].address;
1635 adsl_mem_info[XDATA_REGISTER].org_address = kmalloc (SDRAM_SEGMENT_SIZE + 1024, GFP_KERNEL);
1636 adsl_mem_info[XDATA_REGISTER].address =
1637 (char *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER].org_address + 1023) & 0xFFFFFC00);
1639 adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE;
1641 if (adsl_mem_info[XDATA_REGISTER].address == NULL) {
1642 IFX_MEI_EMSG ("kmalloc memory fail!\n");
1646 adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;
1647 IFX_MEI_DMSG("-> IFX_MEI_BarUpdate()\n");
1648 IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar));
1650 else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) {
1651 IFX_MEI_EMSG ("Error: Firmware size=0! \n");
1656 while (nRead < size) {
1657 long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE;
1658 idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE;
1659 mem_ptr = (char *) KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].address) + offset);
1660 if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE)
1661 nCopy = SDRAM_SEGMENT_SIZE - offset;
1663 nCopy = size - nRead;
1664 copy_from_user (mem_ptr, buf + nRead, nCopy);
1665 for (offset = 0; offset < (nCopy / 4); offset++) {
1666 ((unsigned long *) mem_ptr)[offset] = le32_to_cpu (((unsigned long *) mem_ptr)[offset]);
1669 adsl_mem_info[idx].nCopy += nCopy;
1673 *current_offset = size;
1674 return DSL_DEV_MEI_ERR_SUCCESS;
1676 IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
1677 return DSL_DEV_MEI_ERR_FAILURE;
1680 * Register a callback event.
1682 * -1 if the event already has a callback function registered.
1685 int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *p)
1688 IFX_MEI_EMSG("Invalid parameter!\n");
1691 if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
1692 IFX_MEI_EMSG("Invalid Event %d\n", p->event);
1695 if (dsl_bsp_event_callback[p->event].function) {
1696 IFX_MEI_EMSG("Event %d already has a callback function registered!\n", p->event);
1699 dsl_bsp_event_callback[p->event].function = p->function;
1700 dsl_bsp_event_callback[p->event].event = p->event;
1701 dsl_bsp_event_callback[p->event].pData = p->pData;
1705 int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p)
1708 IFX_MEI_EMSG("Invalid parameter!\n");
1711 if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
1712 IFX_MEI_EMSG("Invalid Event %d\n", p->event);
1715 if (dsl_bsp_event_callback[p->event].function) {
1716 IFX_MEI_EMSG("Unregistering Event %d...\n", p->event);
1717 dsl_bsp_event_callback[p->event].function = NULL;
1718 dsl_bsp_event_callback[p->event].pData = NULL;
1720 IFX_MEI_EMSG("Event %d is not registered!\n", p->event);
1727 * MEI Dying Gasp interrupt handler
1731 * \param regs Pointer to the structure of danube mips registers
1734 static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
1736 DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
1737 DSL_BSP_CB_Type_t event;
1740 IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");
1743 disable_irq (pDev->nIrq[IFX_DYING_GASP]);
1745 disable_irq_nosync(pDev->nIrq[IFX_DYING_GASP]);
1747 event = DSL_BSP_CB_DYING_GASP;
1749 if (dsl_bsp_event_callback[event].function)
1750 (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
1752 #ifdef CONFIG_USE_EMULATOR
1753 IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n");
1755 IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n");
1756 // kill_proc (1, SIGINT, 1); /* Ask init to reboot us */
1761 extern void ifx_usb_enable_afe_oc(void);
1764 * MEI interrupt handler
1768 * \param regs Pointer to the structure of danube mips registers
1771 static irqreturn_t IFX_MEI_IrqHandle (int int1, void *void0)
1774 DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
1775 #if defined(CONFIG_LQ_MEI_FW_LOOPBACK) && defined(DFE_PING_TEST)
1776 dfe_loopback_irq_handler (pDev);
1778 #endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
1779 DSL_BSP_CB_Type_t event;
1782 IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");
1784 IFX_MEI_DebugRead (pDev, ARC_MEI_MAILBOXR, &scratch, 1);
1785 if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) {
1786 IFX_MEI_EMSG("Receive Code Swap Request interrupt!!!\n");
1789 else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE) {
1790 // clear eoc message interrupt
1791 IFX_MEI_DMSG("OMB_CLEAREOC_INTERRUPT_CODE\n");
1792 event = DSL_BSP_CB_CEOC_IRQ;
1793 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
1794 if (dsl_bsp_event_callback[event].function)
1795 (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
1796 } else if (scratch & OMB_REBOOT_INTERRUPT_CODE) {
1798 IFX_MEI_DMSG("OMB_REBOOT_INTERRUPT_CODE\n");
1799 event = DSL_BSP_CB_FIRMWARE_REBOOT;
1801 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
1803 if (dsl_bsp_event_callback[event].function)
1804 (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
1805 } else { // normal message
1806 IFX_MEI_MailboxRead (pDev, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH);
1807 if (DSL_DEV_PRIVATE(pDev)-> cmv_waiting == 1) {
1808 DSL_DEV_PRIVATE(pDev)-> arcmsgav = 1;
1809 DSL_DEV_PRIVATE(pDev)-> cmv_waiting = 0;
1810 #if !defined(BSP_PORT_RTEMS)
1811 MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);
1815 DSL_DEV_PRIVATE(pDev)-> modem_ready_cnt++;
1816 memcpy ((char *) DSL_DEV_PRIVATE(pDev)->Recent_indicator,
1817 (char *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
1818 if (((DSL_DEV_PRIVATE(pDev)->CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) {
1819 //check ARC ready message
1820 IFX_MEI_DMSG ("Got MODEM_READY_MSG\n");
1821 DSL_DEV_PRIVATE(pDev)->modem_ready = 1;
1822 MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);
1831 DSL_BSP_ATMLedCBRegister (int (*ifx_adsl_ledcallback) (void))
1833 g_adsl_ledcallback = ifx_adsl_ledcallback;
1838 DSL_BSP_ATMLedCBUnregister (int (*ifx_adsl_ledcallback) (void))
1840 g_adsl_ledcallback = adsl_dummy_ledcallback;
1846 DSL_BSP_EventCBRegister (int (*ifx_adsl_callback)
1847 (DSL_BSP_CB_Event_t * param))
1851 if (DSL_EventCB == NULL) {
1852 DSL_EventCB = ifx_adsl_callback;
1861 DSL_BSP_EventCBUnregister (int (*ifx_adsl_callback)
1862 (DSL_BSP_CB_Event_t * param))
1866 if (DSL_EventCB == ifx_adsl_callback) {
1876 DSL_BSP_GetEventCB (int (**ifx_adsl_callback)
1877 (DSL_BSP_CB_Event_t * param))
1879 *ifx_adsl_callback = DSL_EventCB;
1884 #ifdef CONFIG_LQ_MEI_FW_LOOPBACK
1885 #define mte_reg_base (0x4800*4+0x20000)
1887 /* Iridia Registers Address Constants */
1888 #define MTE_Reg(r) (int)(mte_reg_base + (r*4))
1890 #define IT_AMODE MTE_Reg(0x0004)
1892 #define TIMER_DELAY (1024)
1893 #define BC0_BYTES (32)
1894 #define BC1_BYTES (30)
1896 #define TIMEOUT_VALUE 2000
1902 for (i = 0; i < cycle; i++);
1906 WriteRegLong (u32 addr, u32 data)
1908 //*((volatile u32 *)(addr)) = data;
1909 IFX_MEI_WRITE_REGISTER_L (data, addr);
1913 ReadRegLong (u32 addr)
1916 //rd_val = *((volatile u32 *)(addr));
1918 return IFX_MEI_READ_REGISTER_L (addr);
1921 /* This routine writes the mailbox with the data in an input array */
1923 WriteMbox (u32 * mboxarray, u32 size)
1925 IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size);
1926 IFX_MEI_DMSG("write to %X\n", IMBOX_BASE);
1927 IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
1930 /* This routine reads the output mailbox and places the results into an array */
1932 ReadMbox (u32 * mboxarray, u32 size)
1934 IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size);
1935 IFX_MEI_DMSG("read from %X\n", OMBOX_BASE);
1939 MEIWriteARCValue (u32 address, u32 value)
1943 /* Write address register */
1944 IFX_MEI_WRITE_REGISTER_L (address, ME_DBG_WR_AD + LQ_MEI_BASE_ADDR);
1946 /* Write data register */
1947 IFX_MEI_WRITE_REGISTER_L (value, ME_DBG_DATA + LQ_MEI_BASE_ADDR);
1949 /* wait until complete - timeout at 40 */
1950 for (i = 0; i < 40; i++) {
1951 check = IFX_MEI_READ_REGISTER_L (ME_ARC2ME_STAT + LQ_MEI_BASE_ADDR);
1953 if ((check & ARC_TO_MEI_DBG_DONE))
1956 /* clear the flag */
1957 IFX_MEI_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ME_ARC2ME_STAT + LQ_MEI_BASE_ADDR);
1961 arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address)
1965 IFX_MEI_DMSG("try to download pages,size=%d\n", arc_code_length);
1966 IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE);
1967 IFX_MEI_HaltArc (&dsl_devices[0]);
1968 IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0);
1969 for (count = 0; count < arc_code_length; count++) {
1970 IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_DATA,
1971 *(start_address + count));
1973 IFX_MEI_ControlModeSet (&dsl_devices[0], JTAG_MASTER_MODE);
1976 load_jump_table (unsigned long addr)
1979 uint32_t addr_le, addr_be;
1980 uint32_t jump_table[32];
1982 for (i = 0; i < 16; i++) {
1983 addr_le = i * 8 + addr;
1984 addr_be = ((addr_le >> 16) & 0xffff);
1985 addr_be |= ((addr_le & 0xffff) << 16);
1986 jump_table[i * 2 + 0] = 0x0f802020;
1987 jump_table[i * 2 + 1] = addr_be;
1988 //printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]);
1990 arc_code_page_download (32, &jump_table[0]);
1997 dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev)
1999 uint32_t rd_mbox[10];
2001 memset (&rd_mbox[0], 0, 10 * 4);
2002 ReadMbox (&rd_mbox[0], 6);
2003 if (rd_mbox[0] == 0x0) {
2004 FX_MEI_DMSG("Get ARC_ACK\n");
2007 else if (rd_mbox[0] == 0x5) {
2008 IFX_MEI_DMSG("Get ARC_BUSY\n");
2011 else if (rd_mbox[0] == 0x3) {
2012 IFX_MEI_DMSG("Get ARC_EDONE\n");
2013 if (rd_mbox[1] == 0x0) {
2015 IFX_MEI_DMSG("Get E_MEMTEST\n");
2016 if (rd_mbox[2] != 0x1) {
2018 IFX_MEI_DMSG("Get Result %X\n", rd_mbox[2]);
2022 IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_STAT,
2023 ARC_TO_MEI_DBG_DONE);
2024 MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
2025 disable_irq (pDev->nIrq[IFX_DFEIR]);
2031 wait_mem_test_result (void)
2036 IFX_MEI_DMSG("Waiting Starting\n");
2037 while (mbox[0] == 0) {
2038 ReadMbox (&mbox[0], 5);
2040 IFX_MEI_DMSG("Try to get mem test result.\n");
2041 ReadMbox (&mbox[0], 5);
2042 if (mbox[0] == 0xA) {
2043 IFX_MEI_DMSG("Success.\n");
2045 else if (mbox[0] == 0xA) {
2046 IFX_MEI_EMSG("Fail,address %X,except data %X,receive data %X\n",
2047 mbox[1], mbox[2], mbox[3]);
2050 IFX_MEI_EMSG("Fail\n");
2055 arc_ping_testing (DSL_DEV_Device_t *pDev)
2057 #define MEI_PING 0x00000001
2058 uint32_t wr_mbox[10], rd_mbox[10];
2061 for (i = 0; i < 10; i++) {
2066 FX_MEI_DMSG("send ping msg\n");
2067 wr_mbox[0] = MEI_PING;
2068 WriteMbox (&wr_mbox[0], 10);
2070 while (got_int == 0) {
2074 IFX_MEI_DMSG("send start event\n");
2080 wr_mbox[3] = (uint32_t) 0xf5acc307e;
2083 wr_mbox[6] = 0x1c000;
2087 WriteMbox (&wr_mbox[0], 10);
2088 DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
2089 //printk("IFX_MEI_MailboxWrite ret=%d\n",i);
2090 IFX_MEI_LongWordWriteOffset (&dsl_devices[0],
2091 (u32) ME_ME2ARC_INT,
2093 IFX_MEI_DMSG("sleeping\n");
2098 IFX_MEI_DMSG("got_int >>>> 3\n");
2100 IFX_MEI_DMSG("got int = %d\n", got_int);
2103 DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
2105 //mbox_read(&rd_mbox[0],6);
2111 static DSL_DEV_MeiError_t
2112 DFE_Loopback_Test (void)
2115 u32 arc_debug_data = 0, temp;
2116 DSL_DEV_Device_t *pDev = &dsl_devices[0];
2117 uint32_t wr_mbox[10];
2119 IFX_MEI_ResetARC (pDev);
2121 arc_debug_data = ACL_CLK_MODE_ENABLE;
2122 IFX_MEI_DebugWrite (pDev, CRI_CCR0, &arc_debug_data, 1);
2124 #if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
2125 // WriteARCreg(AUX_XMEM_LTEST,0);
2126 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
2127 #define AUX_XMEM_LTEST 0x128
2128 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XMEM_LTEST, 0);
2129 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
2131 // WriteARCreg(AUX_XDMA_GAP,0);
2132 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
2133 #define AUX_XDMA_GAP 0x114
2134 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0);
2135 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
2137 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
2139 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
2140 (u32) ME_XDATA_BASE_SH + LQ_MEI_BASE_ADDR, temp);
2141 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
2143 i = IFX_MEI_DFEMemoryAlloc (pDev, SDRAM_SEGMENT_SIZE * 16);
2147 for (idx = 0; idx < i; idx++) {
2148 DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD;
2149 IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff),
2150 LQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + idx * 4);
2151 IFX_MEI_DMSG("bar%d(%X)=%X\n", idx,
2152 LQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE +
2153 idx * 4, (((uint32_t)
2154 ((ifx_mei_device_private_t *)
2155 pDev->pPriv)->adsl_mem_info[idx].
2156 address) & 0x0fffffff));
2157 memset ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address, 0, SDRAM_SEGMENT_SIZE);
2160 IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
2161 ((unsigned long) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);
2164 IFX_MEI_EMSG ("cannot load image: no memory\n");
2165 return DSL_DEV_MEI_ERR_FAILURE;
2167 //WriteARCreg(AUX_IC_CTRL,2);
2168 IFX_MEI_DMSG("Setting MEI_MASTER_MODE..\n");
2169 IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
2170 #define AUX_IC_CTRL 0x11
2171 _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
2173 IFX_MEI_DMSG("Setting JTAG_MASTER_MODE..\n");
2174 IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
2176 IFX_MEI_DMSG("Halting ARC...\n");
2177 IFX_MEI_HaltArc (&dsl_devices[0]);
2179 #ifdef DFE_PING_TEST
2181 IFX_MEI_DMSG("ping test image size=%d\n", sizeof (arc_ahb_access_code));
2182 memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)->
2183 adsl_mem_info[0].address + 0x1004),
2184 &arc_ahb_access_code[0], sizeof (arc_ahb_access_code));
2185 load_jump_table (0x80000 + 0x1004);
2187 #endif //DFE_PING_TEST
2189 IFX_MEI_DMSG("ARC ping test code download complete\n");
2190 #endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
2192 IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN);
2194 arc_code_page_download (1537, &code_array[0]);
2195 IFX_MEI_DMSG("ARC mem test code download complete\n");
2196 #endif //DFE_MEM_TEST
2197 #ifdef DFE_ATM_LOOPBACK
2198 arc_debug_data = 0xf;
2199 arc_code_page_download (sizeof(code_array) / sizeof(*code_array), &code_array[0]);
2200 wr_mbox[0] = 0; //TIMER_DELAY - org: 1024
2201 wr_mbox[1] = 0; //TXFB_START0
2202 wr_mbox[2] = 0x7f; //TXFB_END0 - org: 49
2203 wr_mbox[3] = 0x80; //TXFB_START1 - org: 80
2204 wr_mbox[4] = 0xff; //TXFB_END1 - org: 109
2205 wr_mbox[5] = 0x100; //RXFB_START0 - org: 0
2206 wr_mbox[6] = 0x17f; //RXFB_END0 - org: 49
2207 wr_mbox[7] = 0x180; //RXFB_START1 - org: 256
2208 wr_mbox[8] = 0x1ff; //RXFB_END1 - org: 315
2209 WriteMbox (&wr_mbox[0], 9);
2210 // Start Iridia IT_AMODE (in dmp access) why is it required?
2211 IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1);
2212 #endif //DFE_ATM_LOOPBACK
2213 IFX_MEI_IRQEnable (pDev);
2214 IFX_MEI_DMSG("run ARC...\n");
2215 IFX_MEI_RunArc (&dsl_devices[0]);
2217 #ifdef DFE_PING_TEST
2218 arc_ping_testing (pDev);
2219 #endif //DFE_PING_TEST
2221 wait_mem_test_result ();
2222 #endif //DFE_MEM_TEST
2224 IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
2225 return DSL_DEV_MEI_ERR_SUCCESS;
2228 #endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
2231 IFX_MEI_InitDevNode (int num)
2234 if ((dev_major = register_chrdev (dev_major, IFX_MEI_DEVNAME, &bsp_mei_operations)) < 0) {
2235 IFX_MEI_EMSG ("register_chrdev(%d %s) failed!\n", dev_major, IFX_MEI_DEVNAME);
2243 IFX_MEI_CleanUpDevNode (int num)
2246 unregister_chrdev (dev_major, MEI_DIRNAME);
2251 IFX_MEI_InitDevice (int num)
2253 DSL_DEV_Device_t *pDev;
2255 pDev = &dsl_devices[num];
2258 pDev->pPriv = &sDanube_Mei_Private[num];
2259 memset (pDev->pPriv, 0, sizeof (ifx_mei_device_private_t));
2261 memset (&DSL_DEV_PRIVATE(pDev)->
2262 adsl_mem_info[0], 0,
2263 sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);
2266 pDev->nIrq[IFX_DFEIR] = LQ_MEI_INT;
2267 pDev->nIrq[IFX_DYING_GASP] = LQ_MEI_DYING_GASP_INT;
2268 pDev->base_address = LQ_MEI_BASE_ADDR;
2271 #ifdef CONFIG_LANTIQ_AMAZON_SE
2272 *LQ_PMU_PWDCR &= ~(1 << 9); // enable dsl
2273 *LQ_PMU_PWDCR &= ~(1 << 15); // enable AHB base
2275 temp = lq_r32(LQ_PMU_PWDCR);
2277 lq_w32(temp, LQ_PMU_PWDCR);
2281 DSL_DEV_PRIVATE(pDev)->modem_ready = 0;
2282 DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
2284 MEI_INIT_WAKELIST ("arcq", DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav); // for ARCMSGAV
2285 MEI_INIT_WAKELIST ("arcr", DSL_DEV_PRIVATE(pDev)->wait_queue_modemready); // for arc modem ready
2287 MEI_MUTEX_INIT (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema, 1); // semaphore initialization, mutex
2289 MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
2290 MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
2292 if (request_irq (pDev->nIrq[IFX_DFEIR], IFX_MEI_IrqHandle, 0, "DFEIR", pDev) != 0) {
2293 IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
2296 /*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
2297 IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
2300 // IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
2305 IFX_MEI_ExitDevice (int num)
2307 DSL_DEV_Device_t *pDev;
2308 pDev = &dsl_devices[num];
2313 disable_irq (pDev->nIrq[IFX_DFEIR]);
2314 disable_irq (pDev->nIrq[IFX_DYING_GASP]);
2316 free_irq(pDev->nIrq[IFX_DFEIR], pDev);
2317 free_irq(pDev->nIrq[IFX_DYING_GASP], pDev);
2322 static DSL_DEV_Device_t *
2323 IFX_BSP_HandleGet (int maj, int num)
2325 if (num > BSP_MAX_DEVICES)
2327 return &dsl_devices[num];
2331 DSL_BSP_DriverHandleGet (int maj, int num)
2333 DSL_DEV_Device_t *pDev;
2335 if (num > BSP_MAX_DEVICES)
2338 pDev = &dsl_devices[num];
2339 if (!try_module_get(pDev->owner))
2347 DSL_BSP_DriverHandleDelete (DSL_DEV_Device_t * nHandle)
2349 DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) nHandle;
2352 module_put(pDev->owner);
2357 IFX_MEI_Open (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
2359 int maj = MAJOR (ino->i_rdev);
2360 int num = MINOR (ino->i_rdev);
2362 DSL_DEV_Device_t *pDev = NULL;
2363 if ((pDev = DSL_BSP_DriverHandleGet (maj, num)) == NULL) {
2364 IFX_MEI_EMSG("open(%d:%d) fail!\n", maj, num);
2367 fil->private_data = pDev;
2372 IFX_MEI_Release (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
2374 //int maj = MAJOR(ino->i_rdev);
2375 int num = MINOR (ino->i_rdev);
2376 DSL_DEV_Device_t *pDev;
2378 pDev = &dsl_devices[num];
2381 DSL_BSP_DriverHandleDelete (pDev);
2386 * Callback function for linux userspace program writing
2389 IFX_MEI_Write (DSL_DRV_file_t * filp, const char *buf, size_t size, loff_t * loff)
2391 DSL_DEV_MeiError_t mei_error = DSL_DEV_MEI_ERR_FAILURE;
2393 DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) filp->private_data;
2399 DSL_BSP_FWDownload (pDev, buf, size, (long *) loff, &offset);
2401 if (mei_error == DSL_DEV_MEI_ERR_FAILURE)
2403 return (ssize_t) offset;
2407 * Callback function for linux userspace program ioctling
2410 IFX_MEI_IoctlCopyFrom (int from_kernel, char *dest, char *from, int size)
2415 ret = copy_from_user ((char *) dest, (char *) from, size);
2417 ret = (int)memcpy ((char *) dest, (char *) from, size);
2422 IFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size)
2427 ret = copy_to_user ((char *) dest, (char *) from, size);
2429 ret = (int)memcpy ((char *) dest, (char *) from, size);
2434 IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon)
2437 int meierr = DSL_DEV_MEI_ERR_SUCCESS;
2438 u32 base_address = LQ_MEI_BASE_ADDR;
2439 DSL_DEV_WinHost_Message_t winhost_msg, m;
2440 DSL_DEV_MeiDebug_t debugrdwr;
2441 DSL_DEV_MeiReg_t regrdwr;
2445 case DSL_FIO_BSP_CMV_WINHOST:
2446 IFX_MEI_IoctlCopyFrom (from_kernel, (char *) winhost_msg.msg.TxMessage,
2447 (char *) lon, MSG_LENGTH * 2);
2449 if ((meierr = DSL_BSP_SendCMV (pDev, winhost_msg.msg.TxMessage, YES_REPLY,
2450 winhost_msg.msg.RxMessage)) != DSL_DEV_MEI_ERR_SUCCESS) {
2451 IFX_MEI_EMSG ("WINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n",
2452 winhost_msg.msg.TxMessage[0], winhost_msg.msg.TxMessage[1], winhost_msg.msg.TxMessage[2], winhost_msg.msg.TxMessage[3],
2453 winhost_msg.msg.RxMessage[0], winhost_msg.msg.RxMessage[1], winhost_msg.msg.RxMessage[2], winhost_msg.msg.RxMessage[3],
2454 winhost_msg.msg.RxMessage[4]);
2455 meierr = DSL_DEV_MEI_ERR_FAILURE;
2458 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
2459 (char *) winhost_msg.msg.RxMessage,
2464 case DSL_FIO_BSP_CMV_READ:
2465 IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr),
2466 (char *) lon, sizeof (DSL_DEV_MeiReg_t));
2468 IFX_MEI_LongWordRead ((u32) regrdwr.iAddress,
2469 (u32 *) & (regrdwr.iData));
2471 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
2472 (char *) (®rdwr),
2473 sizeof (DSL_DEV_MeiReg_t));
2477 case DSL_FIO_BSP_CMV_WRITE:
2478 IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr),
2479 (char *) lon, sizeof (DSL_DEV_MeiReg_t));
2481 IFX_MEI_LongWordWrite ((u32) regrdwr.iAddress,
2485 case DSL_FIO_BSP_GET_BASE_ADDRESS:
2486 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
2487 (char *) (&base_address),
2488 sizeof (base_address));
2491 case DSL_FIO_BSP_IS_MODEM_READY:
2492 i = IFX_MEI_IsModemReady (pDev);
2493 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
2494 (char *) (&i), sizeof (int));
2495 meierr = DSL_DEV_MEI_ERR_SUCCESS;
2497 case DSL_FIO_BSP_RESET:
2498 case DSL_FIO_BSP_REBOOT:
2499 meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RESET);
2500 meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
2503 case DSL_FIO_BSP_HALT:
2504 meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
2507 case DSL_FIO_BSP_RUN:
2508 meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RUN);
2510 case DSL_FIO_BSP_BOOTDOWNLOAD:
2511 meierr = IFX_MEI_DownloadBootCode (pDev);
2513 case DSL_FIO_BSP_JTAG_ENABLE:
2514 meierr = IFX_MEI_ArcJtagEnable (pDev, 1);
2517 case DSL_FIO_BSP_REMOTE:
2518 IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&i),
2519 (char *) lon, sizeof (int));
2521 meierr = IFX_MEI_AdslMailboxIRQEnable (pDev, i);
2524 case DSL_FIO_BSP_DSL_START:
2525 IFX_MEI_DMSG("DSL_FIO_BSP_DSL_START\n");
2526 if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) {
2527 IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error...");
2528 meierr = DSL_DEV_MEI_ERR_FAILURE;
2532 case DSL_FIO_BSP_DEBUG_READ:
2533 case DSL_FIO_BSP_DEBUG_WRITE:
2534 IFX_MEI_IoctlCopyFrom (from_kernel,
2535 (char *) (&debugrdwr),
2537 sizeof (debugrdwr));
2539 if (command == DSL_FIO_BSP_DEBUG_READ)
2540 meierr = DSL_BSP_MemoryDebugAccess (pDev,
2541 DSL_BSP_MEMORY_READ,
2549 meierr = DSL_BSP_MemoryDebugAccess (pDev,
2550 DSL_BSP_MEMORY_WRITE,
2558 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr));
2560 case DSL_FIO_BSP_GET_VERSION:
2561 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t));
2564 #define LQ_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
2565 case DSL_FIO_BSP_GET_CHIP_INFO:
2566 bsp_chip_info.major = 1;
2567 bsp_chip_info.minor = LQ_MPS_CHIPID_VERSION_GET(*LQ_MPS_CHIPID);
2568 IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_chip_info), sizeof (DSL_DEV_HwVersion_t));
2569 meierr = DSL_DEV_MEI_ERR_SUCCESS;
2572 case DSL_FIO_BSP_FREE_RESOURCE:
2573 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_STAT, 4, 0, 1, NULL, m.msg.TxMessage);
2574 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) {
2575 meierr = DSL_DEV_MEI_ERR_FAILURE;
2578 IFX_MEI_DMSG("RxMessage[4] = %#x\n", m.msg.RxMessage[4]);
2579 if (!(m.msg.RxMessage[4] & DSL_DEV_STAT_CODESWAP_COMPLETE)) {
2580 meierr = DSL_DEV_MEI_ERR_FAILURE;
2583 IFX_MEI_DMSG("Freeing all memories marked FREE_SHOWTIME\n");
2584 IFX_MEI_DFEMemoryFree (pDev, FREE_SHOWTIME);
2585 meierr = DSL_DEV_MEI_ERR_SUCCESS;
2587 #ifdef CONFIG_IFXMIPS_AMAZON_SE
2588 case DSL_FIO_ARC_MUX_TEST:
2589 AMAZON_SE_MEI_ARC_MUX_Test();
2593 // IFX_MEI_EMSG("Invalid IOCTL command: %d\n");
2599 #ifdef CONFIG_IFXMIPS_AMAZON_SE
2600 void AMAZON_SE_MEI_ARC_MUX_Test(void)
2603 *LQ_RCU_RST |= LQ_RCU_RST_REQ_MUX_ARC;
2605 p = (u32*)(DFE_LDST_BASE_ADDR + IRAM0_BASE);
2606 IFX_MEI_EMSG("Writing to IRAM0(%p)...\n", p);
2607 for (i = 0; i < IRAM0_SIZE/sizeof(u32); i++, p++) {
2609 if (*p != 0xdeadbeef)
2610 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2613 p = (u32*)(DFE_LDST_BASE_ADDR + IRAM1_BASE);
2614 IFX_MEI_EMSG("Writing to IRAM1(%p)...\n", p);
2615 for (i = 0; i < IRAM1_SIZE/sizeof(u32); i++, p++) {
2617 if (*p != 0xdeadbeef)
2618 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2621 p = (u32*)(DFE_LDST_BASE_ADDR + BRAM_BASE);
2622 IFX_MEI_EMSG("Writing to BRAM(%p)...\n", p);
2623 for (i = 0; i < BRAM_SIZE/sizeof(u32); i++, p++) {
2625 if (*p != 0xdeadbeef)
2626 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2629 p = (u32*)(DFE_LDST_BASE_ADDR + XRAM_BASE);
2630 IFX_MEI_EMSG("Writing to XRAM(%p)...\n", p);
2631 for (i = 0; i < XRAM_SIZE/sizeof(u32); i++, p++) {
2633 if (*p != 0xdeadbeef)
2634 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2637 p = (u32*)(DFE_LDST_BASE_ADDR + YRAM_BASE);
2638 IFX_MEI_EMSG("Writing to YRAM(%p)...\n", p);
2639 for (i = 0; i < YRAM_SIZE/sizeof(u32); i++, p++) {
2641 if (*p != 0xdeadbeef)
2642 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2645 p = (u32*)(DFE_LDST_BASE_ADDR + EXT_MEM_BASE);
2646 IFX_MEI_EMSG("Writing to EXT_MEM(%p)...\n", p);
2647 for (i = 0; i < EXT_MEM_SIZE/sizeof(u32); i++, p++) {
2649 if (*p != 0xdeadbeef)
2650 IFX_MEI_EMSG("%p: %#x\n", p, *p);
2652 *LQ_RCU_RST &= ~LQ_RCU_RST_REQ_MUX_ARC;
2656 DSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command,
2661 error = IFX_MEI_Ioctls (pDev, 1, command, lon);
2666 IFX_MEI_UserIoctls (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil,
2667 unsigned int command, unsigned long lon)
2670 int maj = MAJOR (ino->i_rdev);
2671 int num = MINOR (ino->i_rdev);
2672 DSL_DEV_Device_t *pDev;
2674 pDev = IFX_BSP_HandleGet (maj, num);
2678 error = IFX_MEI_Ioctls (pDev, 0, command, lon);
2682 #ifdef CONFIG_PROC_FS
2684 * Register a callback function for linux proc filesystem
2687 IFX_MEI_InitProcFS (int num)
2689 struct proc_dir_entry *entry;
2691 DSL_DEV_Device_t *pDev;
2692 reg_entry_t regs_temp[PROC_ITEMS] = {
2693 /* flag, name, description } */
2694 {NULL, "arcmsgav", "arc to mei message ", 0},
2695 {NULL, "cmv_reply", "cmv needs reply", 0},
2696 {NULL, "cmv_waiting", "waiting for cmv reply from arc", 0},
2697 {NULL, "modem_ready_cnt", "ARC to MEI indicator count", 0},
2698 {NULL, "cmv_count", "MEI to ARC CMVs", 0},
2699 {NULL, "reply_count", "ARC to MEI Reply", 0},
2700 {NULL, "Recent_indicator", "most recent indicator", 0},
2701 {NULL, "fw_version", "Firmware Version", 0},
2702 {NULL, "fw_date", "Firmware Date", 0},
2703 {NULL, "meminfo", "Memory Allocation Information", 0},
2704 {NULL, "version", "MEI version information", 0},
2707 pDev = &dsl_devices[num];
2711 regs_temp[0].flag = &(DSL_DEV_PRIVATE(pDev)->arcmsgav);
2712 regs_temp[1].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_reply);
2713 regs_temp[2].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_waiting);
2714 regs_temp[3].flag = &(DSL_DEV_PRIVATE(pDev)->modem_ready_cnt);
2715 regs_temp[4].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_count);
2716 regs_temp[5].flag = &(DSL_DEV_PRIVATE(pDev)->reply_count);
2717 regs_temp[6].flag = (int *) &(DSL_DEV_PRIVATE(pDev)->Recent_indicator);
2719 memcpy ((char *) regs[num], (char *) regs_temp, sizeof (regs_temp));
2721 meidir = proc_mkdir (MEI_DIRNAME, NULL);
2722 if (meidir == NULL) {
2723 IFX_MEI_EMSG ("Failed to create /proc/%s\n", MEI_DIRNAME);
2727 for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
2728 entry = create_proc_entry (regs[num][i].name,
2729 S_IWUSR | S_IRUSR | S_IRGRP |
2732 regs[num][i].low_ino = entry->low_ino;
2733 entry->proc_fops = &IFX_MEI_ProcOperations;
2736 IFX_MEI_EMSG ("Failed to create /proc/%s/%s\n", MEI_DIRNAME, regs[num][i].name);
2744 * Reading function for linux proc filesystem
2747 IFX_MEI_ProcRead (struct file *file, char *buf, size_t nbytes, loff_t * ppos)
2749 int i_ino = (file->f_dentry->d_inode)->i_ino;
2753 reg_entry_t *entry = NULL;
2754 DSL_DEV_Device_t *pDev = NULL;
2755 DSL_DEV_WinHost_Message_t m;
2757 for (num = 0; num < BSP_MAX_DEVICES; num++) {
2758 for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
2759 if (regs[num][i].low_ino == (unsigned short)i_ino) {
2760 entry = ®s[num][i];
2761 pDev = &dsl_devices[num];
2768 else if (strcmp(entry->name, "meminfo") == 0) {
2769 if (*ppos > 0) /* Assume reading completed in previous read */
2771 p += sprintf (p, "No Address Size\n");
2772 for (i = 0; i < MAX_BAR_REGISTERS; i++) {
2773 p += sprintf (p, "BAR[%02d] Addr:0x%08X Size:%lu\n",
2774 i, (u32) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[i].address,
2775 DSL_DEV_PRIVATE(pDev)-> adsl_mem_info[i].size);
2776 //printk( "BAR[%02d] Addr:0x%08X Size:%d\n",i,adsl_mem_info[i].address,adsl_mem_info[i].size);
2779 } else if (strcmp(entry->name, "fw_version") == 0) {
2780 if (*ppos > 0) /* Assume reading completed in previous read */
2782 if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
2786 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 0, 1, NULL, m.msg.TxMessage);
2787 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
2789 p += sprintf(p, "FW Version: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
2790 //sub_version:bits 4-7
2791 //int_version:bits 0-3
2792 //spl_appl:bits 8-13
2793 //rel_state:bits 14-15
2794 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 1, 1, NULL, m.msg.TxMessage);
2795 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
2797 p += sprintf(p, "%d.%d.%d.%d\n",
2798 (m.msg.RxMessage[4] >> 4) & 0xF, m.msg.RxMessage[4] & 0xF,
2799 (m.msg.RxMessage[4] >> 14) & 3, (m.msg.RxMessage[4] >> 8) & 0x3F);
2801 } else if (strcmp(entry->name, "fw_date") == 0) {
2802 if (*ppos > 0) /* Assume reading completed in previous read */
2804 if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
2807 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 0, 1, NULL, m.msg.TxMessage);
2808 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
2811 p += sprintf(p, "FW Date: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
2813 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 2, 1, NULL, m.msg.TxMessage);
2814 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
2817 p += sprintf(p, "%d ", m.msg.RxMessage[4]);
2819 makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 1, 1, NULL, m.msg.TxMessage);
2820 if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
2823 p += sprintf(p, "%d:%d\n", (m.msg.RxMessage[4] >> 8) & 0xFF, m.msg.RxMessage[4] & 0xFF);
2826 } else if (strcmp(entry->name, "version") == 0) {
2827 if (*ppos > 0) /* Assume reading completed in previous read */
2829 p += sprintf (p, "IFX MEI V%ld.%ld.%ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
2832 } else if (entry->flag != (int *) DSL_DEV_PRIVATE(pDev)->Recent_indicator) {
2833 if (*ppos > 0) /* Assume reading completed in previous read */
2834 return 0; // indicates end of file
2835 p += sprintf (p, "0x%08X\n\n", *(entry->flag));
2837 if ((p - buf) > nbytes) /* Assume output can be read at one time */
2840 if ((int) (*ppos) / ((int) 7) == 16)
2841 return 0; // indicate end of the message
2842 p += sprintf (p, "0x%04X\n\n", *(((u16 *) (entry->flag)) + (int) (*ppos) / ((int) 7)));
2849 * Writing function for linux proc filesystem
2852 IFX_MEI_ProcWrite (struct file *file, const char *buffer, size_t count, loff_t * ppos)
2854 int i_ino = (file->f_dentry->d_inode)->i_ino;
2855 reg_entry_t *current_reg = NULL;
2858 unsigned long newRegValue = 0;
2860 DSL_DEV_Device_t *pDev = NULL;
2862 for (num = 0; num < BSP_MAX_DEVICES; num++) {
2863 for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
2864 if (regs[num][i].low_ino == i_ino) {
2865 current_reg = ®s[num][i];
2866 pDev = &dsl_devices[num];
2871 if ((current_reg == NULL)
2872 || (current_reg->flag ==
2873 (int *) DSL_DEV_PRIVATE(pDev)->
2877 newRegValue = simple_strtoul (buffer, &endp, 0);
2878 *(current_reg->flag) = (int) newRegValue;
2879 return (count + endp - buffer);
2881 #endif //CONFIG_PROC_FS
2883 static int adsl_dummy_ledcallback(void)
2888 int ifx_mei_atm_led_blink(void)
2890 return g_adsl_ledcallback();
2892 EXPORT_SYMBOL(ifx_mei_atm_led_blink);
2894 int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
2898 if ( is_showtime ) {
2899 *is_showtime = g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ? 0 : 1;
2903 for ( i = 0; i < port_cell->port_num && i < 2; i++ )
2904 port_cell->tx_link_rate[i] = g_tx_link_rate[i];
2908 if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 )
2911 *xdata_addr = g_xdata_addr;
2916 EXPORT_SYMBOL(ifx_mei_atm_showtime_check);
2919 * Writing function for linux proc filesystem
2922 IFX_MEI_ModuleInit (void)
2925 static struct class *dsl_class;
2927 pr_info("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
2929 for (i = 0; i < BSP_MAX_DEVICES; i++) {
2930 if (IFX_MEI_InitDevice (i) != 0) {
2931 IFX_MEI_EMSG("Init device fail!\n");
2934 IFX_MEI_InitDevNode (i);
2935 #ifdef CONFIG_PROC_FS
2936 IFX_MEI_InitProcFS (i);
2939 for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
2940 dsl_bsp_event_callback[i].function = NULL;
2942 #ifdef CONFIG_LQ_MEI_FW_LOOPBACK
2943 IFX_MEI_DMSG("Start loopback test...\n");
2944 DFE_Loopback_Test ();
2946 dsl_class = class_create(THIS_MODULE, "ifx_mei");
2947 device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei");
2952 IFX_MEI_ModuleExit (void)
2957 for (num = 0; num < BSP_MAX_DEVICES; num++) {
2958 IFX_MEI_CleanUpDevNode (num);
2959 #ifdef CONFIG_PROC_FS
2960 for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
2961 remove_proc_entry (regs[num][i].name, meidir);
2966 remove_proc_entry (MEI_DIRNAME, NULL);
2967 for (i = 0; i < BSP_MAX_DEVICES; i++) {
2968 for (i = 0; i < BSP_MAX_DEVICES; i++) {
2969 IFX_MEI_ExitDevice (i);
2974 /* export function for DSL Driver */
2976 /* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are
2977 something like open/close in kernel space , where the open could be used
2978 to register a callback for autonomous messages and returns a mei driver context pointer (comparable to the file descriptor in user space)
2979 The context will be required for the multi line chips future! */
2981 EXPORT_SYMBOL (DSL_BSP_DriverHandleGet);
2982 EXPORT_SYMBOL (DSL_BSP_DriverHandleDelete);
2984 EXPORT_SYMBOL (DSL_BSP_ATMLedCBRegister);
2985 EXPORT_SYMBOL (DSL_BSP_ATMLedCBUnregister);
2986 EXPORT_SYMBOL (DSL_BSP_KernelIoctls);
2987 EXPORT_SYMBOL (DSL_BSP_AdslLedInit);
2988 //EXPORT_SYMBOL (DSL_BSP_AdslLedSet);
2989 EXPORT_SYMBOL (DSL_BSP_FWDownload);
2990 EXPORT_SYMBOL (DSL_BSP_Showtime);
2992 EXPORT_SYMBOL (DSL_BSP_MemoryDebugAccess);
2993 EXPORT_SYMBOL (DSL_BSP_SendCMV);
2995 // provide a register/unregister function for DSL driver to register a event callback function
2996 EXPORT_SYMBOL (DSL_BSP_EventCBRegister);
2997 EXPORT_SYMBOL (DSL_BSP_EventCBUnregister);
2999 module_init (IFX_MEI_ModuleInit);
3000 module_exit (IFX_MEI_ModuleExit);
3002 MODULE_LICENSE("Dual BSD/GPL");