1 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
2 #define IFXMIPS_ATM_FW_REGS_COMMON_H
6 #if defined(CONFIG_DANUBE)
7 #include "ifxmips_atm_fw_regs_danube.h"
8 #elif defined(CONFIG_AMAZON_SE)
9 #include "ifxmips_atm_fw_regs_amazon_se.h"
10 #elif defined(CONFIG_AR9)
11 #include "ifxmips_atm_fw_regs_ar9.h"
12 #elif defined(CONFIG_VR9)
13 #include "ifxmips_atm_fw_regs_vr9.h"
15 #error Platform is not specified!
23 #if defined(__BIG_ENDIAN)
24 struct uni_cell_header {
32 struct uni_cell_header {
39 #endif // defined(__BIG_ENDIAN)
42 * Inband Header and Trailer
44 #if defined(__BIG_ENDIAN)
45 struct rx_inband_trailer {
49 unsigned int stw_res1:4;
50 unsigned int stw_clp :1;
51 unsigned int stw_ec :1;
52 unsigned int stw_uu :1;
53 unsigned int stw_cpi :1;
54 unsigned int stw_ovz :1;
55 unsigned int stw_mfl :1;
56 unsigned int stw_usz :1;
57 unsigned int stw_crc :1;
58 unsigned int stw_il :1;
59 unsigned int stw_ra :1;
60 unsigned int stw_res2:2;
69 struct tx_inband_header {
83 struct rx_inband_trailer {
85 unsigned int stw_res2:2;
86 unsigned int stw_ra :1;
87 unsigned int stw_il :1;
88 unsigned int stw_crc :1;
89 unsigned int stw_usz :1;
90 unsigned int stw_mfl :1;
91 unsigned int stw_ovz :1;
92 unsigned int stw_cpi :1;
93 unsigned int stw_uu :1;
94 unsigned int stw_ec :1;
95 unsigned int stw_clp :1;
96 unsigned int stw_res1:4;
102 unsigned int vci :16;
107 struct tx_inband_header {
111 unsigned int vci :16;
115 unsigned int res1 :8;
120 #endif // defined(__BIG_ENDIAN)
123 * MIB Table Maintained by Firmware
125 struct wan_mib_table {
127 u32 wrx_drophtu_cell;
131 u32 wrx_dropdes_cell;
132 u32 wrx_correct_cell;
142 * Host-PPE Communication Data Structure
145 #if defined(__BIG_ENDIAN)
146 struct wrx_queue_config {
148 unsigned int res2 :27;
149 unsigned int dmach :4;
150 unsigned int errdp :1;
152 unsigned int oversize :16;
153 unsigned int undersize :16;
155 unsigned int res1 :16;
156 unsigned int mfs :16;
158 unsigned int uumask :8;
159 unsigned int cpimask :8;
160 unsigned int uuexp :8;
161 unsigned int cpiexp :8;
164 struct wtx_port_config {
165 unsigned int res1 :27;
167 unsigned int qsben :1;
170 struct wtx_queue_config {
171 unsigned int res1 :25;
172 unsigned int sbid :1;
173 unsigned int res2 :3;
174 unsigned int type :2;
175 unsigned int qsben :1;
178 struct wrx_dma_channel_config {
180 unsigned int res1 :1;
181 unsigned int mode :2;
182 unsigned int rlcfg :1;
183 unsigned int desba :28;
185 unsigned int chrl :16;
186 unsigned int clp1th :16;
188 unsigned int deslen :16;
189 unsigned int vlddes :16;
192 struct wtx_dma_channel_config {
194 unsigned int res2 :1;
195 unsigned int mode :2;
196 unsigned int res3 :1;
197 unsigned int desba :28;
199 unsigned int res1 :32;
201 unsigned int deslen :16;
202 unsigned int vlddes :16;
206 unsigned int res1 :1;
210 unsigned int vci :16;
218 unsigned int pid_mask :2;
219 unsigned int vpi_mask :8;
220 unsigned int vci_mask :16;
221 unsigned int pti_mask :3;
222 unsigned int clear :1;
226 unsigned int res1 :12;
227 unsigned int cellid :4;
228 unsigned int res2 :5;
229 unsigned int type :1;
231 unsigned int res3 :5;
235 struct rx_descriptor {
241 unsigned int res1 :3;
242 unsigned int byteoff :2;
243 unsigned int res2 :2;
246 unsigned int datalen :16;
248 unsigned int res3 :4;
249 unsigned int dataptr :28;
252 struct tx_descriptor {
258 unsigned int byteoff :5;
259 unsigned int res1 :5;
260 unsigned int iscell :1;
262 unsigned int datalen :16;
264 unsigned int res2 :4;
265 unsigned int dataptr :28;
268 struct wrx_queue_config {
270 unsigned int errdp :1;
271 unsigned int dmach :4;
272 unsigned int res2 :27;
274 unsigned int undersize :16;
275 unsigned int oversize :16;
277 unsigned int mfs :16;
278 unsigned int res1 :16;
280 unsigned int cpiexp :8;
281 unsigned int uuexp :8;
282 unsigned int cpimask :8;
283 unsigned int uumask :8;
286 struct wtx_port_config {
287 unsigned int qsben :1;
289 unsigned int res1 :27;
292 struct wtx_queue_config {
293 unsigned int qsben :1;
294 unsigned int type :2;
295 unsigned int res2 :3;
296 unsigned int sbid :1;
297 unsigned int res1 :25;
300 struct wrx_dma_channel_config
303 unsigned int desba :28;
304 unsigned int rlcfg :1;
305 unsigned int mode :2;
306 unsigned int res1 :1;
308 unsigned int clp1th :16;
309 unsigned int chrl :16;
311 unsigned int vlddes :16;
312 unsigned int deslen :16;
315 struct wtx_dma_channel_config {
317 unsigned int desba :28;
318 unsigned int res3 :1;
319 unsigned int mode :2;
320 unsigned int res2 :1;
322 unsigned int res1 :32;
324 unsigned int vlddes :16;
325 unsigned int deslen :16;
328 struct rx_descriptor {
330 unsigned int dataptr :28;
331 unsigned int res3 :4;
333 unsigned int datalen :16;
336 unsigned int res2 :2;
337 unsigned int byteoff :2;
338 unsigned int res1 :3;
345 struct tx_descriptor {
347 unsigned int dataptr :28;
348 unsigned int res2 :4;
350 unsigned int datalen :16;
352 unsigned int iscell :1;
353 unsigned int res1 :5;
354 unsigned int byteoff :5;
360 #endif // defined(__BIG_ENDIAN)
364 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H