2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
4 * Copyright 2004, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
24 #include <asm/paccess.h>
35 /* Global SB handle */
36 extern void *bcm947xx_sbh;
37 extern spinlock_t bcm947xx_sbh_lock;
40 #define sbh bcm947xx_sbh
41 #define sbh_lock bcm947xx_sbh_lock
44 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
49 spin_lock_irqsave(&sbh_lock, flags);
50 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
51 spin_unlock_irqrestore(&sbh_lock, flags);
52 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
56 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
61 spin_lock_irqsave(&sbh_lock, flags);
62 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
63 spin_unlock_irqrestore(&sbh_lock, flags);
64 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
68 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
73 spin_lock_irqsave(&sbh_lock, flags);
74 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
75 spin_unlock_irqrestore(&sbh_lock, flags);
76 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
80 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
85 spin_lock_irqsave(&sbh_lock, flags);
86 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
87 spin_unlock_irqrestore(&sbh_lock, flags);
88 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
92 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
97 spin_lock_irqsave(&sbh_lock, flags);
98 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
99 spin_unlock_irqrestore(&sbh_lock, flags);
100 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
104 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
109 spin_lock_irqsave(&sbh_lock, flags);
110 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
111 spin_unlock_irqrestore(&sbh_lock, flags);
112 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
115 static struct pci_ops pcibios_ops = {
116 sbpci_read_config_byte,
117 sbpci_read_config_word,
118 sbpci_read_config_dword,
119 sbpci_write_config_byte,
120 sbpci_write_config_word,
121 sbpci_write_config_dword
130 if (!(sbh = sb_kattach()))
131 panic("sb_kattach failed");
132 spin_lock_init(&sbh_lock);
134 spin_lock_irqsave(&sbh_lock, flags);
136 spin_unlock_irqrestore(&sbh_lock, flags);
138 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
140 /* Scan the SB bus */
141 pci_scan_bus(0, &pcibios_ops, NULL);
146 pcibios_setup(char *str)
148 if (!strncmp(str, "ban=", 4)) {
149 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
156 static u32 pci_iobase = 0x100;
157 static u32 pci_membase = SB_PCI_DMA;
160 pcibios_fixup_bus(struct pci_bus *b)
162 struct list_head *ln;
164 struct resource *res;
169 printk("PCI: Fixing up bus %d\n", b->number);
172 if (b->number == 0) {
173 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
175 /* Fix up interrupt lines */
176 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
178 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
182 /* Fix up external PCI */
184 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
186 /* Fix up resource bases */
187 for (pos = 0; pos < 6; pos++) {
188 res = &d->resource[pos];
189 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
191 size = res->end - res->start + 1;
192 if (*base & (size - 1))
193 *base = (*base + size) & ~(size - 1);
195 res->end = res->start + size - 1;
197 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
199 /* Fix up PCI bridge BAR0 only */
200 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
203 /* Fix up interrupt lines */
204 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
205 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
206 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
212 pcibios_assign_all_busses(void)
218 pcibios_align_resource(void *data, struct resource *res,
219 unsigned long size, unsigned long align)
224 pcibios_enable_resources(struct pci_dev *dev)
230 /* External PCI only */
231 if (dev->bus->number == 0)
234 pci_read_config_word(dev, PCI_COMMAND, &cmd);
236 for(idx=0; idx<6; idx++) {
237 r = &dev->resource[idx];
238 if (r->flags & IORESOURCE_IO)
239 cmd |= PCI_COMMAND_IO;
240 if (r->flags & IORESOURCE_MEM)
241 cmd |= PCI_COMMAND_MEMORY;
243 if (dev->resource[PCI_ROM_RESOURCE].start)
244 cmd |= PCI_COMMAND_MEMORY;
245 if (cmd != old_cmd) {
246 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
247 pci_write_config_word(dev, PCI_COMMAND, cmd);
253 pcibios_enable_device(struct pci_dev *dev, int mask)
258 /* External PCI device enable */
259 if (dev->bus->number != 0)
260 return pcibios_enable_resources(dev);
262 /* These cores come out of reset enabled */
263 if (dev->device == SB_MIPS ||
264 dev->device == SB_MIPS33 ||
265 dev->device == SB_EXTIF ||
266 dev->device == SB_CC)
269 spin_lock_irqsave(&sbh_lock, flags);
270 coreidx = sb_coreidx(sbh);
271 if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
272 return PCIBIOS_DEVICE_NOT_FOUND;
275 * The USB core requires a special bit to be set during core
276 * reset to enable host (OHCI) mode. Resetting the SB core in
277 * pcibios_enable_device() is a hack for compatibility with
278 * vanilla usb-ohci so that it does not have to know about
279 * SB. A driver that wants to use the USB core in device mode
280 * should know about SB and should reset the bit back to 0
281 * after calling pcibios_enable_device().
283 if (sb_coreid(sbh) == SB_USB) {
284 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
285 sb_core_reset(sbh, 1 << 29);
287 sb_core_reset(sbh, 0);
289 sb_setcoreidx(sbh, coreidx);
290 spin_unlock_irqrestore(&sbh_lock, flags);
296 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
297 struct resource *res, int resource)
299 unsigned long where, size;
302 /* External PCI only */
303 if (dev->bus->number == 0)
306 where = PCI_BASE_ADDRESS_0 + (resource * 4);
307 size = res->end - res->start;
308 pci_read_config_dword(dev, where, ®);
309 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
310 pci_write_config_dword(dev, where, reg);
314 quirk_sbpci_bridge(struct pci_dev *dev)
316 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
319 printk("PCI: Fixing up bridge\n");
321 /* Enable PCI bridge bus mastering and memory space */
323 pcibios_enable_resources(dev);
325 /* Enable PCI bridge BAR1 prefetch and burst */
326 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
330 * If we set up a device for bus mastering, we need to check the latency
331 * timer as certain crappy BIOSes forget to set it properly.
333 unsigned int pcibios_max_latency = 255;
335 void pcibios_set_master(struct pci_dev *dev)
338 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
340 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
341 else if (lat > pcibios_max_latency)
342 lat = pcibios_max_latency;
345 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
346 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
349 struct pci_fixup pcibios_fixups[] = {
350 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },