4 #include <linux/interrupt.h>
5 #include <linux/ssb/ssb_embedded.h>
6 #include <linux/gpio.h>
9 static inline u32 gpio_in(void)
11 switch (bcm47xx_bus_type) {
12 #ifdef CONFIG_BCM47XX_SSB
13 case BCM47XX_BUS_TYPE_SSB:
14 return ssb_gpio_in(&bcm47xx_bus.ssb, ~0);
16 #ifdef CONFIG_BCM47XX_BCMA
17 case BCM47XX_BUS_TYPE_BCMA:
18 return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, ~0);
24 static inline u32 gpio_out(u32 mask, u32 value)
26 switch (bcm47xx_bus_type) {
27 #ifdef CONFIG_BCM47XX_SSB
28 case BCM47XX_BUS_TYPE_SSB:
29 return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
31 #ifdef CONFIG_BCM47XX_BCMA
32 case BCM47XX_BUS_TYPE_BCMA:
33 return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
39 static inline u32 gpio_outen(u32 mask, u32 value)
41 switch (bcm47xx_bus_type) {
42 #ifdef CONFIG_BCM47XX_SSB
43 case BCM47XX_BUS_TYPE_SSB:
44 ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
47 #ifdef CONFIG_BCM47XX_BCMA
48 case BCM47XX_BUS_TYPE_BCMA:
49 bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
56 static inline u32 gpio_control(u32 mask, u32 value)
58 switch (bcm47xx_bus_type) {
59 #ifdef CONFIG_BCM47XX_SSB
60 case BCM47XX_BUS_TYPE_SSB:
61 return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
63 #ifdef CONFIG_BCM47XX_BCMA
64 case BCM47XX_BUS_TYPE_BCMA:
65 return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
71 static inline u32 gpio_setintmask(u32 mask, u32 value)
73 switch (bcm47xx_bus_type) {
74 #ifdef CONFIG_BCM47XX_SSB
75 case BCM47XX_BUS_TYPE_SSB:
76 return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
78 #ifdef CONFIG_BCM47XX_BCMA
79 case BCM47XX_BUS_TYPE_BCMA:
80 return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
86 static inline u32 gpio_intpolarity(u32 mask, u32 value)
88 switch (bcm47xx_bus_type) {
89 #ifdef CONFIG_BCM47XX_SSB
90 case BCM47XX_BUS_TYPE_SSB:
91 return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
93 #ifdef CONFIG_BCM47XX_BCMA
94 case BCM47XX_BUS_TYPE_BCMA:
95 return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
101 #ifdef CONFIG_BCM47XX_SSB
102 static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
106 value |= ssb_read32(dev, offset) & ~mask;
107 ssb_write32(dev, offset, value);
112 #ifdef CONFIG_BCM47XX_BCMA
113 static inline u32 __bcma_write32_masked(struct bcma_device *dev, u16 offset,
117 value |= bcma_read32(dev, offset) & ~mask;
118 bcma_write32(dev, offset, value);
123 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
127 irq = gpio_to_irq(0);
128 if (irq == -EINVAL) return;
131 if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
134 free_irq(irq, handler);
137 switch (bcm47xx_bus_type) {
138 #ifdef CONFIG_BCM47XX_SSB
139 case BCM47XX_BUS_TYPE_SSB:
140 if (bcm47xx_bus.ssb.chipco.dev)
141 __ssb_write32_masked(bcm47xx_bus.ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
143 #ifdef CONFIG_BCM47XX_BCMA
144 case BCM47XX_BUS_TYPE_BCMA:
145 if (bcm47xx_bus.bcma.bus.drv_cc.core)
146 __bcma_write32_masked(bcm47xx_bus.bcma.bus.drv_cc.core, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO, (enabled ? BCMA_CC_IRQ_GPIO : 0));
151 #define EXTIF_ADDR 0x1f000000
152 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)
154 #define GPIO_TYPE_NORMAL (0x0 << 24)
155 #define GPIO_TYPE_EXTIF (0x1 << 24)
156 #define GPIO_TYPE_MASK (0xf << 24)
158 static inline void gpio_set_extif(int gpio, int value)
160 volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
167 #endif /* __DIAG_GPIO_H */