package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.c

   1 /*
   2
   3   Broadcom BCM43xx wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "bcm43xx.h"
  31 #include "bcm43xx_dma.h"
  32 #include "bcm43xx_main.h"
  33 #include "bcm43xx_debugfs.h"
  34 #include "bcm43xx_power.h"
  35 #include "bcm43xx_xmit.h"
  36
  37 #include <linux/dma-mapping.h>
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40 #include <linux/skbuff.h>
  41
  42
  43 /* 32bit DMA ops. */
  44 static
  45 struct bcm43xx_dmadesc_generic * op32_idx2desc(struct bcm43xx_dmaring *ring,
  46                                                int slot,
  47                                                struct bcm43xx_dmadesc_meta **meta)
  48 {
  49         struct bcm43xx_dmadesc32 *desc;
  50
  51         *meta = &(ring->meta[slot]);
  52         desc = ring->descbase;
  53         desc = &(desc[slot]);
  54
  55         return (struct bcm43xx_dmadesc_generic *)desc;
  56 }
  57
  58 static void op32_fill_descriptor(struct bcm43xx_dmaring *ring,
  59                                  struct bcm43xx_dmadesc_generic *desc,
  60                                  dma_addr_t dmaaddr, u16 bufsize,
  61                                  int start, int end, int irq)
  62 {
  63         struct bcm43xx_dmadesc32 *descbase = ring->descbase;
  64         int slot;
  65         u32 ctl;
  66         u32 addr;
  67         u32 addrext;
  68
  69         slot = (int)(&(desc->dma32) - descbase);
  70         assert(slot >= 0 && slot < ring->nr_slots);
  71
  72         addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
  73         addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
  74                    >> SSB_DMA_TRANSLATION_SHIFT;
  75         addr |= ssb_dma_translation(ring->dev->dev);
  76         ctl = (bufsize - ring->frameoffset)
  77               & BCM43xx_DMA32_DCTL_BYTECNT;
  78         if (slot == ring->nr_slots - 1)
  79                 ctl |= BCM43xx_DMA32_DCTL_DTABLEEND;
  80         if (start)
  81                 ctl |= BCM43xx_DMA32_DCTL_FRAMESTART;
  82         if (end)
  83                 ctl |= BCM43xx_DMA32_DCTL_FRAMEEND;
  84         if (irq)
  85                 ctl |= BCM43xx_DMA32_DCTL_IRQ;
  86         ctl |= (addrext << BCM43xx_DMA32_DCTL_ADDREXT_SHIFT)
  87                & BCM43xx_DMA32_DCTL_ADDREXT_MASK;
  88
  89         desc->dma32.control = cpu_to_le32(ctl);
  90         desc->dma32.address = cpu_to_le32(addr);
  91 }
  92
  93 static void op32_poke_tx(struct bcm43xx_dmaring *ring, int slot)
  94 {
  95         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXINDEX,
  96                           (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
  97 }
  98
  99 static void op32_tx_suspend(struct bcm43xx_dmaring *ring)
 100 {
 101         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
 102                           bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
 103                           | BCM43xx_DMA32_TXSUSPEND);
 104 }
 105
 106 static void op32_tx_resume(struct bcm43xx_dmaring *ring)
 107 {
 108         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
 109                           bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
 110                           & ~BCM43xx_DMA32_TXSUSPEND);
 111 }
 112
 113 static int op32_get_current_rxslot(struct bcm43xx_dmaring *ring)
 114 {
 115         u32 val;
 116
 117         val = bcm43xx_dma_read(ring, BCM43xx_DMA32_RXSTATUS);
 118         val &= BCM43xx_DMA32_RXDPTR;
 119
 120         return (val / sizeof(struct bcm43xx_dmadesc32));
 121 }
 122
 123 static void op32_set_current_rxslot(struct bcm43xx_dmaring *ring,
 124                                     int slot)
 125 {
 126         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX,
 127                           (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
 128 }
 129
 130 static const struct bcm43xx_dma_ops dma32_ops = {
 131         .idx2desc               = op32_idx2desc,
 132         .fill_descriptor        = op32_fill_descriptor,
 133         .poke_tx                = op32_poke_tx,
 134         .tx_suspend             = op32_tx_suspend,
 135         .tx_resume              = op32_tx_resume,
 136         .get_current_rxslot     = op32_get_current_rxslot,
 137         .set_current_rxslot     = op32_set_current_rxslot,
 138 };
 139
 140 /* 64bit DMA ops. */
 141 static
 142 struct bcm43xx_dmadesc_generic * op64_idx2desc(struct bcm43xx_dmaring *ring,
 143                                                int slot,
 144                                                struct bcm43xx_dmadesc_meta **meta)
 145 {
 146         struct bcm43xx_dmadesc64 *desc;
 147
 148         *meta = &(ring->meta[slot]);
 149         desc = ring->descbase;
 150         desc = &(desc[slot]);
 151
 152         return (struct bcm43xx_dmadesc_generic *)desc;
 153 }
 154
 155 static void op64_fill_descriptor(struct bcm43xx_dmaring *ring,
 156                                  struct bcm43xx_dmadesc_generic *desc,
 157                                  dma_addr_t dmaaddr, u16 bufsize,
 158                                  int start, int end, int irq)
 159 {
 160         struct bcm43xx_dmadesc64 *descbase = ring->descbase;
 161         int slot;
 162         u32 ctl0 = 0, ctl1 = 0;
 163         u32 addrlo, addrhi;
 164         u32 addrext;
 165
 166         slot = (int)(&(desc->dma64) - descbase);
 167         assert(slot >= 0 && slot < ring->nr_slots);
 168
 169         addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
 170         addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 171         addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 172                   >> SSB_DMA_TRANSLATION_SHIFT;
 173         addrhi |= ssb_dma_translation(ring->dev->dev);
 174         if (slot == ring->nr_slots - 1)
 175                 ctl0 |= BCM43xx_DMA64_DCTL0_DTABLEEND;
 176         if (start)
 177                 ctl0 |= BCM43xx_DMA64_DCTL0_FRAMESTART;
 178         if (end)
 179                 ctl0 |= BCM43xx_DMA64_DCTL0_FRAMEEND;
 180         if (irq)
 181                 ctl0 |= BCM43xx_DMA64_DCTL0_IRQ;
 182         ctl1 |= (bufsize - ring->frameoffset)
 183                 & BCM43xx_DMA64_DCTL1_BYTECNT;
 184         ctl1 |= (addrext << BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT)
 185                 & BCM43xx_DMA64_DCTL1_ADDREXT_MASK;
 186
 187         desc->dma64.control0 = cpu_to_le32(ctl0);
 188         desc->dma64.control1 = cpu_to_le32(ctl1);
 189         desc->dma64.address_low = cpu_to_le32(addrlo);
 190         desc->dma64.address_high = cpu_to_le32(addrhi);
 191 }
 192
 193 static void op64_poke_tx(struct bcm43xx_dmaring *ring, int slot)
 194 {
 195         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXINDEX,
 196                           (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
 197 }
 198
 199 static void op64_tx_suspend(struct bcm43xx_dmaring *ring)
 200 {
 201         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
 202                           bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
 203                           | BCM43xx_DMA64_TXSUSPEND);
 204 }
 205
 206 static void op64_tx_resume(struct bcm43xx_dmaring *ring)
 207 {
 208         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
 209                           bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
 210                           & ~BCM43xx_DMA64_TXSUSPEND);
 211 }
 212
 213 static int op64_get_current_rxslot(struct bcm43xx_dmaring *ring)
 214 {
 215         u32 val;
 216
 217         val = bcm43xx_dma_read(ring, BCM43xx_DMA64_RXSTATUS);
 218         val &= BCM43xx_DMA64_RXSTATDPTR;
 219
 220         return (val / sizeof(struct bcm43xx_dmadesc64));
 221 }
 222
 223 static void op64_set_current_rxslot(struct bcm43xx_dmaring *ring,
 224                                     int slot)
 225 {
 226         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX,
 227                           (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
 228 }
 229
 230 static const struct bcm43xx_dma_ops dma64_ops = {
 231         .idx2desc               = op64_idx2desc,
 232         .fill_descriptor        = op64_fill_descriptor,
 233         .poke_tx                = op64_poke_tx,
 234         .tx_suspend             = op64_tx_suspend,
 235         .tx_resume              = op64_tx_resume,
 236         .get_current_rxslot     = op64_get_current_rxslot,
 237         .set_current_rxslot     = op64_set_current_rxslot,
 238 };
 239
 240
 241 static inline int free_slots(struct bcm43xx_dmaring *ring)
 242 {
 243         return (ring->nr_slots - ring->used_slots);
 244 }
 245
 246 static inline int next_slot(struct bcm43xx_dmaring *ring, int slot)
 247 {
 248         assert(slot >= -1 && slot <= ring->nr_slots - 1);
 249         if (slot == ring->nr_slots - 1)
 250                 return 0;
 251         return slot + 1;
 252 }
 253
 254 static inline int prev_slot(struct bcm43xx_dmaring *ring, int slot)
 255 {
 256         assert(slot >= 0 && slot <= ring->nr_slots - 1);
 257         if (slot == 0)
 258                 return ring->nr_slots - 1;
 259         return slot - 1;
 260 }
 261
 262 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 263 static void update_max_used_slots(struct bcm43xx_dmaring *ring,
 264                                   int current_used_slots)
 265 {
 266         if (current_used_slots <= ring->max_used_slots)
 267                 return;
 268         ring->max_used_slots = current_used_slots;
 269         if (bcm43xx_debug(ring->dev, BCM43xx_DBG_DMAVERBOSE)) {
 270                 dprintk(KERN_DEBUG PFX
 271                         "max_used_slots increased to %d on %s ring %d\n",
 272                         ring->max_used_slots,
 273                         ring->tx ? "TX" : "RX",
 274                         ring->index);
 275         }
 276 }
 277 #else
 278 static inline
 279 void update_max_used_slots(struct bcm43xx_dmaring *ring,
 280                            int current_used_slots)
 281 { }
 282 #endif /* DEBUG */
 283
 284 /* Request a slot for usage. */
 285 static inline
 286 int request_slot(struct bcm43xx_dmaring *ring)
 287 {
 288         int slot;
 289
 290         assert(ring->tx);
 291         assert(!ring->stopped);
 292         assert(free_slots(ring) != 0);
 293
 294         slot = next_slot(ring, ring->current_slot);
 295         ring->current_slot = slot;
 296         ring->used_slots++;
 297
 298         update_max_used_slots(ring, ring->used_slots);
 299
 300         return slot;
 301 }
 302
 303 /* Mac80211-queue to bcm43xx-ring mapping */
 304 static struct bcm43xx_dmaring * priority_to_txring(struct bcm43xx_wldev *dev,
 305                                                    int queue_priority)
 306 {
 307         struct bcm43xx_dmaring *ring;
 308
 309 /*FIXME: For now we always run on TX-ring-1 */
 310 return dev->dma.tx_ring1;
 311
 312         /* 0 = highest priority */
 313         switch (queue_priority) {
 314         default:
 315                 assert(0);
 316                 /* fallthrough */
 317         case 0:
 318                 ring = dev->dma.tx_ring3;
 319                 break;
 320         case 1:
 321                 ring = dev->dma.tx_ring2;
 322                 break;
 323         case 2:
 324                 ring = dev->dma.tx_ring1;
 325                 break;
 326         case 3:
 327                 ring = dev->dma.tx_ring0;
 328                 break;
 329         case 4:
 330                 ring = dev->dma.tx_ring4;
 331                 break;
 332         case 5:
 333                 ring = dev->dma.tx_ring5;
 334                 break;
 335         }
 336
 337         return ring;
 338 }
 339
 340 /* Bcm43xx-ring to mac80211-queue mapping */
 341 static inline int txring_to_priority(struct bcm43xx_dmaring *ring)
 342 {
 343         static const u8 idx_to_prio[] =
 344                 { 3, 2, 1, 0, 4, 5, };
 345
 346 /*FIXME: have only one queue, for now */
 347 return 0;
 348
 349         return idx_to_prio[ring->index];
 350 }
 351
 352
 353 u16 bcm43xx_dmacontroller_base(int dma64bit, int controller_idx)
 354 {
 355         static const u16 map64[] = {
 356                 BCM43xx_MMIO_DMA64_BASE0,
 357                 BCM43xx_MMIO_DMA64_BASE1,
 358                 BCM43xx_MMIO_DMA64_BASE2,
 359                 BCM43xx_MMIO_DMA64_BASE3,
 360                 BCM43xx_MMIO_DMA64_BASE4,
 361                 BCM43xx_MMIO_DMA64_BASE5,
 362         };
 363         static const u16 map32[] = {
 364                 BCM43xx_MMIO_DMA32_BASE0,
 365                 BCM43xx_MMIO_DMA32_BASE1,
 366                 BCM43xx_MMIO_DMA32_BASE2,
 367                 BCM43xx_MMIO_DMA32_BASE3,
 368                 BCM43xx_MMIO_DMA32_BASE4,
 369                 BCM43xx_MMIO_DMA32_BASE5,
 370         };
 371
 372         if (dma64bit) {
 373                 assert(controller_idx >= 0 &&
 374                        controller_idx < ARRAY_SIZE(map64));
 375                 return map64[controller_idx];
 376         }
 377         assert(controller_idx >= 0 &&
 378                controller_idx < ARRAY_SIZE(map32));
 379         return map32[controller_idx];
 380 }
 381
 382 static inline
 383 dma_addr_t map_descbuffer(struct bcm43xx_dmaring *ring,
 384                           unsigned char *buf,
 385                           size_t len,
 386                           int tx)
 387 {
 388         dma_addr_t dmaaddr;
 389
 390         if (tx) {
 391                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 392                                          buf, len,
 393                                          DMA_TO_DEVICE);
 394         } else {
 395                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 396                                          buf, len,
 397                                          DMA_FROM_DEVICE);
 398         }
 399
 400         return dmaaddr;
 401 }
 402
 403 static inline
 404 void unmap_descbuffer(struct bcm43xx_dmaring *ring,
 405                       dma_addr_t addr,
 406                       size_t len,
 407                       int tx)
 408 {
 409         if (tx) {
 410                 dma_unmap_single(ring->dev->dev->dev,
 411                                  addr, len,
 412                                  DMA_TO_DEVICE);
 413         } else {
 414                 dma_unmap_single(ring->dev->dev->dev,
 415                                  addr, len,
 416                                  DMA_FROM_DEVICE);
 417         }
 418 }
 419
 420 static inline
 421 void sync_descbuffer_for_cpu(struct bcm43xx_dmaring *ring,
 422                              dma_addr_t addr,
 423                              size_t len)
 424 {
 425         assert(!ring->tx);
 426
 427         dma_sync_single_for_cpu(ring->dev->dev->dev,
 428                                 addr, len, DMA_FROM_DEVICE);
 429 }
 430
 431 static inline
 432 void sync_descbuffer_for_device(struct bcm43xx_dmaring *ring,
 433                                 dma_addr_t addr,
 434                                 size_t len)
 435 {
 436         assert(!ring->tx);
 437
 438         dma_sync_single_for_device(ring->dev->dev->dev,
 439                                    addr, len, DMA_FROM_DEVICE);
 440 }
 441
 442 static inline
 443 void free_descriptor_buffer(struct bcm43xx_dmaring *ring,
 444                             struct bcm43xx_dmadesc_meta *meta,
 445                             int irq_context)
 446 {
 447         if (meta->skb) {
 448                 if (irq_context)
 449                         dev_kfree_skb_irq(meta->skb);
 450                 else
 451                         dev_kfree_skb(meta->skb);
 452                 meta->skb = NULL;
 453         }
 454 }
 455
 456 static int alloc_ringmemory(struct bcm43xx_dmaring *ring)
 457 {
 458         struct device *dev = ring->dev->dev->dev;
 459
 460         ring->descbase = dma_alloc_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
 461                                             &(ring->dmabase), GFP_KERNEL);
 462         if (!ring->descbase) {
 463                 printk(KERN_ERR PFX "DMA ringmemory allocation failed\n");
 464                 return -ENOMEM;
 465         }
 466         memset(ring->descbase, 0, BCM43xx_DMA_RINGMEMSIZE);
 467
 468         return 0;
 469 }
 470
 471 static void free_ringmemory(struct bcm43xx_dmaring *ring)
 472 {
 473         struct device *dev = ring->dev->dev->dev;
 474
 475         dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
 476                           ring->descbase, ring->dmabase);
 477 }
 478
 479 /* Reset the RX DMA channel */
 480 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
 481                                    u16 mmio_base, int dma64)
 482 {
 483         int i;
 484         u32 value;
 485         u16 offset;
 486
 487         might_sleep();
 488
 489         offset = dma64 ? BCM43xx_DMA64_RXCTL : BCM43xx_DMA32_RXCTL;
 490         bcm43xx_write32(dev, mmio_base + offset, 0);
 491         for (i = 0; i < 10; i++) {
 492                 offset = dma64 ? BCM43xx_DMA64_RXSTATUS : BCM43xx_DMA32_RXSTATUS;
 493                 value = bcm43xx_read32(dev, mmio_base + offset);
 494                 if (dma64) {
 495                         value &= BCM43xx_DMA64_RXSTAT;
 496                         if (value == BCM43xx_DMA64_RXSTAT_DISABLED) {
 497                                 i = -1;
 498                                 break;
 499                         }
 500                 } else {
 501                         value &= BCM43xx_DMA32_RXSTATE;
 502                         if (value == BCM43xx_DMA32_RXSTAT_DISABLED) {
 503                                 i = -1;
 504                                 break;
 505                         }
 506                 }
 507                 msleep(1);
 508         }
 509         if (i != -1) {
 510                 printk(KERN_ERR PFX "ERROR: DMA RX reset timed out\n");
 511                 return -ENODEV;
 512         }
 513
 514         return 0;
 515 }
 516
 517 /* Reset the RX DMA channel */
 518 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
 519                                    u16 mmio_base, int dma64)
 520 {
 521         int i;
 522         u32 value;
 523         u16 offset;
 524
 525         might_sleep();
 526
 527         for (i = 0; i < 10; i++) {
 528                 offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
 529                 value = bcm43xx_read32(dev, mmio_base + offset);
 530                 if (dma64) {
 531                         value &= BCM43xx_DMA64_TXSTAT;
 532                         if (value == BCM43xx_DMA64_TXSTAT_DISABLED ||
 533                             value == BCM43xx_DMA64_TXSTAT_IDLEWAIT ||
 534                             value == BCM43xx_DMA64_TXSTAT_STOPPED)
 535                                 break;
 536                 } else {
 537                         value &= BCM43xx_DMA32_TXSTATE;
 538                         if (value == BCM43xx_DMA32_TXSTAT_DISABLED ||
 539                             value == BCM43xx_DMA32_TXSTAT_IDLEWAIT ||
 540                             value == BCM43xx_DMA32_TXSTAT_STOPPED)
 541                                 break;
 542                 }
 543                 msleep(1);
 544         }
 545         offset = dma64 ? BCM43xx_DMA64_TXCTL : BCM43xx_DMA32_TXCTL;
 546         bcm43xx_write32(dev, mmio_base + offset, 0);
 547         for (i = 0; i < 10; i++) {
 548                 offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
 549                 value = bcm43xx_read32(dev, mmio_base + offset);
 550                 if (dma64) {
 551                         value &= BCM43xx_DMA64_TXSTAT;
 552                         if (value == BCM43xx_DMA64_TXSTAT_DISABLED) {
 553                                 i = -1;
 554                                 break;
 555                         }
 556                 } else {
 557                         value &= BCM43xx_DMA32_TXSTATE;
 558                         if (value == BCM43xx_DMA32_TXSTAT_DISABLED) {
 559                                 i = -1;
 560                                 break;
 561                         }
 562                 }
 563                 msleep(1);
 564         }
 565         if (i != -1) {
 566                 printk(KERN_ERR PFX "ERROR: DMA TX reset timed out\n");
 567                 return -ENODEV;
 568         }
 569         /* ensure the reset is completed. */
 570         msleep(1);
 571
 572         return 0;
 573 }
 574
 575 static int setup_rx_descbuffer(struct bcm43xx_dmaring *ring,
 576                                struct bcm43xx_dmadesc_generic *desc,
 577                                struct bcm43xx_dmadesc_meta *meta,
 578                                gfp_t gfp_flags)
 579 {
 580         struct bcm43xx_rxhdr_fw4 *rxhdr;
 581         struct bcm43xx_hwtxstatus *txstat;
 582         dma_addr_t dmaaddr;
 583         struct sk_buff *skb;
 584
 585         assert(!ring->tx);
 586
 587         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 588         if (unlikely(!skb))
 589                 return -ENOMEM;
 590         dmaaddr = map_descbuffer(ring, skb->data,
 591                                  ring->rx_buffersize, 0);
 592         if (dma_mapping_error(dmaaddr)) {
 593                 /* ugh. try to realloc in zone_dma */
 594                 gfp_flags |= GFP_DMA;
 595
 596                 dev_kfree_skb_any(skb);
 597
 598                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 599                 if (unlikely(!skb))
 600                         return -ENOMEM;
 601                 dmaaddr = map_descbuffer(ring, skb->data,
 602                                          ring->rx_buffersize, 0);
 603         }
 604
 605         if (dma_mapping_error(dmaaddr)) {
 606                 dev_kfree_skb_any(skb);
 607                 return -EIO;
 608         }
 609
 610         meta->skb = skb;
 611         meta->dmaaddr = dmaaddr;
 612         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 613                                    ring->rx_buffersize, 0, 0, 0);
 614
 615         rxhdr = (struct bcm43xx_rxhdr_fw4 *)(skb->data);
 616         rxhdr->frame_len = 0;
 617         txstat = (struct bcm43xx_hwtxstatus *)(skb->data);
 618         txstat->cookie = 0;
 619
 620         return 0;
 621 }
 622
 623 /* Allocate the initial descbuffers.
 624  * This is used for an RX ring only.
 625  */
 626 static int alloc_initial_descbuffers(struct bcm43xx_dmaring *ring)
 627 {
 628         int i, err = -ENOMEM;
 629         struct bcm43xx_dmadesc_generic *desc;
 630         struct bcm43xx_dmadesc_meta *meta;
 631
 632         for (i = 0; i < ring->nr_slots; i++) {
 633                 desc = ring->ops->idx2desc(ring, i, &meta);
 634
 635                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 636                 if (err) {
 637                         printk(KERN_ERR PFX "Failed to allocate initial descbuffers\n");
 638                         goto err_unwind;
 639                 }
 640         }
 641         mb();
 642         ring->used_slots = ring->nr_slots;
 643         err = 0;
 644 out:
 645         return err;
 646
 647 err_unwind:
 648         for (i--; i >= 0; i--) {
 649                 desc = ring->ops->idx2desc(ring, i, &meta);
 650
 651                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 652                 dev_kfree_skb(meta->skb);
 653         }
 654         goto out;
 655 }
 656
 657 /* Do initial setup of the DMA controller.
 658  * Reset the controller, write the ring busaddress
 659  * and switch the "enable" bit on.
 660  */
 661 static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
 662 {
 663         int err = 0;
 664         u32 value;
 665         u32 addrext;
 666         u32 trans = ssb_dma_translation(ring->dev->dev);
 667
 668         if (ring->tx) {
 669                 if (ring->dma64) {
 670                         u64 ringbase = (u64)(ring->dmabase);
 671
 672                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 673                                   >> SSB_DMA_TRANSLATION_SHIFT;
 674                         value = BCM43xx_DMA64_TXENABLE;
 675                         value |= (addrext << BCM43xx_DMA64_TXADDREXT_SHIFT)
 676                                 & BCM43xx_DMA64_TXADDREXT_MASK;
 677                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL, value);
 678                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO,
 679                                         (ringbase & 0xFFFFFFFF));
 680                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI,
 681                                         ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
 682                                         | trans);
 683                 } else {
 684                         u32 ringbase = (u32)(ring->dmabase);
 685
 686                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 687                                   >> SSB_DMA_TRANSLATION_SHIFT;
 688                         value = BCM43xx_DMA32_TXENABLE;
 689                         value |= (addrext << BCM43xx_DMA32_TXADDREXT_SHIFT)
 690                                 & BCM43xx_DMA32_TXADDREXT_MASK;
 691                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL, value);
 692                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING,
 693                                         (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 694                                         | trans);
 695                 }
 696         } else {
 697                 err = alloc_initial_descbuffers(ring);
 698                 if (err)
 699                         goto out;
 700                 if (ring->dma64) {
 701                         u64 ringbase = (u64)(ring->dmabase);
 702
 703                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 704                                   >> SSB_DMA_TRANSLATION_SHIFT;
 705                         value = (ring->frameoffset << BCM43xx_DMA64_RXFROFF_SHIFT);
 706                         value |= BCM43xx_DMA64_RXENABLE;
 707                         value |= (addrext << BCM43xx_DMA64_RXADDREXT_SHIFT)
 708                                 & BCM43xx_DMA64_RXADDREXT_MASK;
 709                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXCTL, value);
 710                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO,
 711                                         (ringbase & 0xFFFFFFFF));
 712                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI,
 713                                         ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
 714                                         | trans);
 715                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX, 200);
 716                 } else {
 717                         u32 ringbase = (u32)(ring->dmabase);
 718
 719                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 720                                   >> SSB_DMA_TRANSLATION_SHIFT;
 721                         value = (ring->frameoffset << BCM43xx_DMA32_RXFROFF_SHIFT);
 722                         value |= BCM43xx_DMA32_RXENABLE;
 723                         value |= (addrext << BCM43xx_DMA32_RXADDREXT_SHIFT)
 724                                 & BCM43xx_DMA32_RXADDREXT_MASK;
 725                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXCTL, value);
 726                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING,
 727                                         (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 728                                         | trans);
 729                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX, 200);
 730                 }
 731         }
 732
 733 out:
 734         return err;
 735 }
 736
 737 /* Shutdown the DMA controller. */
 738 static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
 739 {
 740         if (ring->tx) {
 741                 bcm43xx_dmacontroller_tx_reset(ring->dev, ring->mmio_base, ring->dma64);
 742                 if (ring->dma64) {
 743                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO, 0);
 744                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI, 0);
 745                 } else
 746                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING, 0);
 747         } else {
 748                 bcm43xx_dmacontroller_rx_reset(ring->dev, ring->mmio_base, ring->dma64);
 749                 if (ring->dma64) {
 750                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO, 0);
 751                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI, 0);
 752                 } else
 753                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING, 0);
 754         }
 755 }
 756
 757 static void free_all_descbuffers(struct bcm43xx_dmaring *ring)
 758 {
 759         struct bcm43xx_dmadesc_generic *desc;
 760         struct bcm43xx_dmadesc_meta *meta;
 761         int i;
 762
 763         if (!ring->used_slots)
 764                 return;
 765         for (i = 0; i < ring->nr_slots; i++) {
 766                 desc = ring->ops->idx2desc(ring, i, &meta);
 767
 768                 if (!meta->skb) {
 769                         assert(ring->tx);
 770                         continue;
 771                 }
 772                 if (ring->tx) {
 773                         unmap_descbuffer(ring, meta->dmaaddr,
 774                                         meta->skb->len, 1);
 775                 } else {
 776                         unmap_descbuffer(ring, meta->dmaaddr,
 777                                         ring->rx_buffersize, 0);
 778                 }
 779                 free_descriptor_buffer(ring, meta, 0);
 780         }
 781 }
 782
 783 static u64 supported_dma_mask(struct bcm43xx_wldev *dev)
 784 {
 785         u32 tmp;
 786         u16 mmio_base;
 787
 788         tmp = bcm43xx_read32(dev, SSB_TMSHIGH);
 789         if (tmp & SSB_TMSHIGH_DMA64)
 790                 return DMA_64BIT_MASK;
 791         mmio_base = bcm43xx_dmacontroller_base(0, 0);
 792         bcm43xx_write32(dev,
 793                         mmio_base + BCM43xx_DMA32_TXCTL,
 794                         BCM43xx_DMA32_TXADDREXT_MASK);
 795         tmp = bcm43xx_read32(dev,
 796                              mmio_base + BCM43xx_DMA32_TXCTL);
 797         if (tmp & BCM43xx_DMA32_TXADDREXT_MASK)
 798                 return DMA_32BIT_MASK;
 799
 800         return DMA_30BIT_MASK;
 801 }
 802
 803 /* Main initialization function. */
 804 static
 805 struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_wldev *dev,
 806                                                int controller_index,
 807                                                int for_tx,
 808                                                int dma64)
 809 {
 810         struct bcm43xx_dmaring *ring;
 811         int err;
 812         int nr_slots;
 813         dma_addr_t dma_test;
 814
 815         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 816         if (!ring)
 817                 goto out;
 818
 819         nr_slots = BCM43xx_RXRING_SLOTS;
 820         if (for_tx)
 821                 nr_slots = BCM43xx_TXRING_SLOTS;
 822
 823         ring->meta = kcalloc(nr_slots, sizeof(struct bcm43xx_dmadesc_meta),
 824                              GFP_KERNEL);
 825         if (!ring->meta)
 826                 goto err_kfree_ring;
 827         if (for_tx) {
 828                 ring->txhdr_cache = kcalloc(nr_slots,
 829                                             sizeof(struct bcm43xx_txhdr_fw4),
 830                                             GFP_KERNEL);
 831                 if (!ring->txhdr_cache)
 832                         goto err_kfree_meta;
 833
 834                 /* test for ability to dma to txhdr_cache */
 835                 dma_test = dma_map_single(dev->dev->dev,
 836                                 ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
 837                                 DMA_TO_DEVICE);
 838
 839                 if (dma_mapping_error(dma_test)) {
 840                         /* ugh realloc */
 841                         kfree(ring->txhdr_cache);
 842                         ring->txhdr_cache = kcalloc(nr_slots,
 843                                                         sizeof(struct bcm43xx_txhdr_fw4),
 844                                                         GFP_KERNEL | GFP_DMA);
 845                         if (!ring->txhdr_cache)
 846                                 goto err_kfree_meta;
 847
 848                         dma_test = dma_map_single(dev->dev->dev,
 849                                         ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
 850                                         DMA_TO_DEVICE);
 851
 852                         if (dma_mapping_error(dma_test))
 853                                 goto err_kfree_txhdr_cache;
 854                 }
 855
 856                 dma_unmap_single(dev->dev->dev,
 857                                 dma_test, sizeof(struct bcm43xx_txhdr_fw4),
 858                                 DMA_TO_DEVICE);
 859         }
 860
 861         ring->dev = dev;
 862         ring->nr_slots = nr_slots;
 863         ring->mmio_base = bcm43xx_dmacontroller_base(dma64, controller_index);
 864         ring->index = controller_index;
 865         ring->dma64 = !!dma64;
 866         if (dma64)
 867                 ring->ops = &dma64_ops;
 868         else
 869                 ring->ops = &dma32_ops;
 870         if (for_tx) {
 871                 ring->tx = 1;
 872                 ring->current_slot = -1;
 873         } else {
 874                 if (ring->index == 0) {
 875                         ring->rx_buffersize = BCM43xx_DMA0_RX_BUFFERSIZE;
 876                         ring->frameoffset = BCM43xx_DMA0_RX_FRAMEOFFSET;
 877                 } else if (ring->index == 3) {
 878                         ring->rx_buffersize = BCM43xx_DMA3_RX_BUFFERSIZE;
 879                         ring->frameoffset = BCM43xx_DMA3_RX_FRAMEOFFSET;
 880                 } else
 881                         assert(0);
 882         }
 883         spin_lock_init(&ring->lock);
 884 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 885         ring->last_injected_overflow = jiffies;
 886 #endif
 887
 888         err = alloc_ringmemory(ring);
 889         if (err)
 890                 goto err_kfree_txhdr_cache;
 891         err = dmacontroller_setup(ring);
 892         if (err)
 893                 goto err_free_ringmemory;
 894
 895 out:
 896         return ring;
 897
 898 err_free_ringmemory:
 899         free_ringmemory(ring);
 900 err_kfree_txhdr_cache:
 901         kfree(ring->txhdr_cache);
 902 err_kfree_meta:
 903         kfree(ring->meta);
 904 err_kfree_ring:
 905         kfree(ring);
 906         ring = NULL;
 907         goto out;
 908 }
 909
 910 /* Main cleanup function. */
 911 static void bcm43xx_destroy_dmaring(struct bcm43xx_dmaring *ring)
 912 {
 913         if (!ring)
 914                 return;
 915
 916         dprintk(KERN_INFO PFX "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
 917                 (ring->dma64) ? "64" : "32",
 918                 ring->mmio_base,
 919                 (ring->tx) ? "TX" : "RX",
 920                 ring->max_used_slots, ring->nr_slots);
 921         /* Device IRQs are disabled prior entering this function,
 922          * so no need to take care of concurrency with rx handler stuff.
 923          */
 924         dmacontroller_cleanup(ring);
 925         free_all_descbuffers(ring);
 926         free_ringmemory(ring);
 927
 928         kfree(ring->txhdr_cache);
 929         kfree(ring->meta);
 930         kfree(ring);
 931 }
 932
 933 void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
 934 {
 935         struct bcm43xx_dma *dma;
 936
 937         if (bcm43xx_using_pio(dev))
 938                 return;
 939         dma = &dev->dma;
 940
 941         bcm43xx_destroy_dmaring(dma->rx_ring3);
 942         dma->rx_ring3 = NULL;
 943         bcm43xx_destroy_dmaring(dma->rx_ring0);
 944         dma->rx_ring0 = NULL;
 945
 946         bcm43xx_destroy_dmaring(dma->tx_ring5);
 947         dma->tx_ring5 = NULL;
 948         bcm43xx_destroy_dmaring(dma->tx_ring4);
 949         dma->tx_ring4 = NULL;
 950         bcm43xx_destroy_dmaring(dma->tx_ring3);
 951         dma->tx_ring3 = NULL;
 952         bcm43xx_destroy_dmaring(dma->tx_ring2);
 953         dma->tx_ring2 = NULL;
 954         bcm43xx_destroy_dmaring(dma->tx_ring1);
 955         dma->tx_ring1 = NULL;
 956         bcm43xx_destroy_dmaring(dma->tx_ring0);
 957         dma->tx_ring0 = NULL;
 958 }
 959
 960 int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
 961 {
 962         struct bcm43xx_dma *dma = &dev->dma;
 963         struct bcm43xx_dmaring *ring;
 964         int err;
 965         u64 dmamask;
 966         int dma64 = 0;
 967
 968         dmamask = supported_dma_mask(dev);
 969         if (dmamask == DMA_64BIT_MASK)
 970                 dma64 = 1;
 971
 972         err = ssb_dma_set_mask(dev->dev, dmamask);
 973         if (err) {
 974 #ifdef BCM43XX_MAC80211_PIO
 975                 printk(KERN_WARNING PFX "DMA for this device not supported. "
 976                                         "Falling back to PIO\n");
 977                 dev->__using_pio = 1;
 978                 return -EAGAIN;
 979 #else
 980                 printk(KERN_ERR PFX "DMA for this device not supported and "
 981                                     "no PIO support compiled in\n");
 982                 return -EOPNOTSUPP;
 983 #endif
 984         }
 985
 986         err = -ENOMEM;
 987         /* setup TX DMA channels. */
 988         ring = bcm43xx_setup_dmaring(dev, 0, 1, dma64);
 989         if (!ring)
 990                 goto out;
 991         dma->tx_ring0 = ring;
 992
 993         ring = bcm43xx_setup_dmaring(dev, 1, 1, dma64);
 994         if (!ring)
 995                 goto err_destroy_tx0;
 996         dma->tx_ring1 = ring;
 997
 998         ring = bcm43xx_setup_dmaring(dev, 2, 1, dma64);
 999         if (!ring)
1000                 goto err_destroy_tx1;
1001         dma->tx_ring2 = ring;
1002
1003         ring = bcm43xx_setup_dmaring(dev, 3, 1, dma64);
1004         if (!ring)
1005                 goto err_destroy_tx2;
1006         dma->tx_ring3 = ring;
1007
1008         ring = bcm43xx_setup_dmaring(dev, 4, 1, dma64);
1009         if (!ring)
1010                 goto err_destroy_tx3;
1011         dma->tx_ring4 = ring;
1012
1013         ring = bcm43xx_setup_dmaring(dev, 5, 1, dma64);
1014         if (!ring)
1015                 goto err_destroy_tx4;
1016         dma->tx_ring5 = ring;
1017
1018         /* setup RX DMA channels. */
1019         ring = bcm43xx_setup_dmaring(dev, 0, 0, dma64);
1020         if (!ring)
1021                 goto err_destroy_tx5;
1022         dma->rx_ring0 = ring;
1023
1024         if (dev->dev->id.revision < 5) {
1025                 ring = bcm43xx_setup_dmaring(dev, 3, 0, dma64);
1026                 if (!ring)
1027                         goto err_destroy_rx0;
1028                 dma->rx_ring3 = ring;
1029         }
1030
1031         dprintk(KERN_INFO PFX "%d-bit DMA initialized\n",
1032                 (dmamask == DMA_64BIT_MASK) ? 64 :
1033                 (dmamask == DMA_32BIT_MASK) ? 32 : 30);
1034         err = 0;
1035 out:
1036         return err;
1037
1038 err_destroy_rx0:
1039         bcm43xx_destroy_dmaring(dma->rx_ring0);
1040         dma->rx_ring0 = NULL;
1041 err_destroy_tx5:
1042         bcm43xx_destroy_dmaring(dma->tx_ring5);
1043         dma->tx_ring5 = NULL;
1044 err_destroy_tx4:
1045         bcm43xx_destroy_dmaring(dma->tx_ring4);
1046         dma->tx_ring4 = NULL;
1047 err_destroy_tx3:
1048         bcm43xx_destroy_dmaring(dma->tx_ring3);
1049         dma->tx_ring3 = NULL;
1050 err_destroy_tx2:
1051         bcm43xx_destroy_dmaring(dma->tx_ring2);
1052         dma->tx_ring2 = NULL;
1053 err_destroy_tx1:
1054         bcm43xx_destroy_dmaring(dma->tx_ring1);
1055         dma->tx_ring1 = NULL;
1056 err_destroy_tx0:
1057         bcm43xx_destroy_dmaring(dma->tx_ring0);
1058         dma->tx_ring0 = NULL;
1059         goto out;
1060 }
1061
1062 /* Generate a cookie for the TX header. */
1063 static u16 generate_cookie(struct bcm43xx_dmaring *ring,
1064                            int slot)
1065 {
1066         u16 cookie = 0x1000;
1067
1068         /* Use the upper 4 bits of the cookie as
1069          * DMA controller ID and store the slot number
1070          * in the lower 12 bits.
1071          * Note that the cookie must never be 0, as this
1072          * is a special value used in RX path.
1073          */
1074         switch (ring->index) {
1075         case 0:
1076                 cookie = 0xA000;
1077                 break;
1078         case 1:
1079                 cookie = 0xB000;
1080                 break;
1081         case 2:
1082                 cookie = 0xC000;
1083                 break;
1084         case 3:
1085                 cookie = 0xD000;
1086                 break;
1087         case 4:
1088                 cookie = 0xE000;
1089                 break;
1090         case 5:
1091                 cookie = 0xF000;
1092                 break;
1093         }
1094         assert(((u16)slot & 0xF000) == 0x0000);
1095         cookie |= (u16)slot;
1096
1097         return cookie;
1098 }
1099
1100 /* Inspect a cookie and find out to which controller/slot it belongs. */
1101 static
1102 struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_wldev *dev,
1103                                       u16 cookie, int *slot)
1104 {
1105         struct bcm43xx_dma *dma = &dev->dma;
1106         struct bcm43xx_dmaring *ring = NULL;
1107
1108         switch (cookie & 0xF000) {
1109         case 0xA000:
1110                 ring = dma->tx_ring0;
1111                 break;
1112         case 0xB000:
1113                 ring = dma->tx_ring1;
1114                 break;
1115         case 0xC000:
1116                 ring = dma->tx_ring2;
1117                 break;
1118         case 0xD000:
1119                 ring = dma->tx_ring3;
1120                 break;
1121         case 0xE000:
1122                 ring = dma->tx_ring4;
1123                 break;
1124         case 0xF000:
1125                 ring = dma->tx_ring5;
1126                 break;
1127         default:
1128                 assert(0);
1129         }
1130         *slot = (cookie & 0x0FFF);
1131         assert(ring && *slot >= 0 && *slot < ring->nr_slots);
1132
1133         return ring;
1134 }
1135
1136 static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
1137                             struct sk_buff *skb,
1138                             struct ieee80211_tx_control *ctl)
1139 {
1140         const struct bcm43xx_dma_ops *ops = ring->ops;
1141         u8 *header;
1142         int slot;
1143         int err;
1144         struct bcm43xx_dmadesc_generic *desc;
1145         struct bcm43xx_dmadesc_meta *meta;
1146         struct bcm43xx_dmadesc_meta *meta_hdr;
1147         struct sk_buff *bounce_skb;
1148
1149 #define SLOTS_PER_PACKET  2
1150         assert(skb_shinfo(skb)->nr_frags == 0);
1151
1152         /* Get a slot for the header. */
1153         slot = request_slot(ring);
1154         desc = ops->idx2desc(ring, slot, &meta_hdr);
1155         memset(meta_hdr, 0, sizeof(*meta_hdr));
1156
1157         header = &(ring->txhdr_cache[slot * sizeof(struct bcm43xx_txhdr_fw4)]);
1158         bcm43xx_generate_txhdr(ring->dev, header,
1159                                skb->data, skb->len, ctl,
1160                                generate_cookie(ring, slot));
1161
1162         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1163                                        sizeof(struct bcm43xx_txhdr_fw4), 1);
1164         if (dma_mapping_error(meta_hdr->dmaaddr))
1165                 return -EIO;
1166         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1167                              sizeof(struct bcm43xx_txhdr_fw4), 1, 0, 0);
1168
1169         /* Get a slot for the payload. */
1170         slot = request_slot(ring);
1171         desc = ops->idx2desc(ring, slot, &meta);
1172         memset(meta, 0, sizeof(*meta));
1173
1174         memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1175         meta->skb = skb;
1176         meta->is_last_fragment = 1;
1177
1178         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1179         /* create a bounce buffer in zone_dma on mapping failure. */
1180         if (dma_mapping_error(meta->dmaaddr)) {
1181                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1182                 if (!bounce_skb) {
1183                         err = -ENOMEM;
1184                         goto out_unmap_hdr;
1185                 }
1186
1187                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1188                 dev_kfree_skb_any(skb);
1189                 skb = bounce_skb;
1190                 meta->skb = skb;
1191                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1192                 if (dma_mapping_error(meta->dmaaddr)) {
1193                         err = -EIO;
1194                         goto out_free_bounce;
1195                 }
1196         }
1197
1198         ops->fill_descriptor(ring, desc, meta->dmaaddr,
1199                              skb->len, 0, 1, 1);
1200
1201         /* Now transfer the whole frame. */
1202         wmb();
1203         ops->poke_tx(ring, next_slot(ring, slot));
1204         return 0;
1205
1206 out_free_bounce:
1207         dev_kfree_skb_any(skb);
1208 out_unmap_hdr:
1209         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1210                         sizeof(struct bcm43xx_txhdr_fw4), 1);
1211         return err;
1212 }
1213
1214 static inline
1215 int should_inject_overflow(struct bcm43xx_dmaring *ring)
1216 {
1217 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
1218         if (unlikely(bcm43xx_debug(ring->dev, BCM43xx_DBG_DMAOVERFLOW))) {
1219                 /* Check if we should inject another ringbuffer overflow
1220                  * to test handling of this situation in the stack. */
1221                 unsigned long next_overflow;
1222
1223                 next_overflow = ring->last_injected_overflow + HZ;
1224                 if (time_after(jiffies, next_overflow)) {
1225                         ring->last_injected_overflow = jiffies;
1226                         dprintk(KERN_DEBUG PFX "Injecting TX ring overflow on "
1227                                 "DMA controller %d\n", ring->index);
1228                         return 1;
1229                 }
1230         }
1231 #endif /* CONFIG_BCM43XX_MAC80211_DEBUG */
1232         return 0;
1233 }
1234
1235 int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
1236                    struct sk_buff *skb,
1237                    struct ieee80211_tx_control *ctl)
1238 {
1239         struct bcm43xx_dmaring *ring;
1240         int err = 0;
1241         unsigned long flags;
1242
1243         ring = priority_to_txring(dev, ctl->queue);
1244         spin_lock_irqsave(&ring->lock, flags);
1245         assert(ring->tx);
1246         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1247                 printkl(KERN_ERR PFX "DMA queue overflow\n");
1248                 err = -ENOSPC;
1249                 goto out_unlock;
1250         }
1251         /* Check if the queue was stopped in mac80211,
1252          * but we got called nevertheless.
1253          * That would be a mac80211 bug. */
1254         assert(!ring->stopped);
1255
1256         err = dma_tx_fragment(ring, skb, ctl);
1257         if (unlikely(err)) {
1258                 printkl(KERN_ERR PFX "DMA tx mapping failure\n");
1259                 goto out_unlock;
1260         }
1261         ring->nr_tx_packets++;
1262         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1263             should_inject_overflow(ring)) {
1264                 /* This TX ring is full. */
1265                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1266                 ring->stopped = 1;
1267                 if (bcm43xx_debug(dev, BCM43xx_DBG_DMAVERBOSE)) {
1268                         dprintk(KERN_DEBUG PFX "Stopped TX ring %d\n",
1269                                 ring->index);
1270                 }
1271         }
1272 out_unlock:
1273         spin_unlock_irqrestore(&ring->lock, flags);
1274
1275         return err;
1276 }
1277
1278 void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
1279                                  const struct bcm43xx_txstatus *status)
1280 {
1281         const struct bcm43xx_dma_ops *ops;
1282         struct bcm43xx_dmaring *ring;
1283         struct bcm43xx_dmadesc_generic *desc;
1284         struct bcm43xx_dmadesc_meta *meta;
1285         int slot;
1286
1287         ring = parse_cookie(dev, status->cookie, &slot);
1288         if (unlikely(!ring))
1289                 return;
1290         assert(irqs_disabled());
1291         spin_lock(&ring->lock);
1292
1293         assert(ring->tx);
1294         ops = ring->ops;
1295         while (1) {
1296                 assert(slot >= 0 && slot < ring->nr_slots);
1297                 desc = ops->idx2desc(ring, slot, &meta);
1298
1299                 if (meta->skb)
1300                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1301                 else
1302                         unmap_descbuffer(ring, meta->dmaaddr, sizeof(struct bcm43xx_txhdr_fw4), 1);
1303
1304                 if (meta->is_last_fragment) {
1305                         assert(meta->skb);
1306                         /* Call back to inform the ieee80211 subsystem about the
1307                          * status of the transmission.
1308                          * Some fields of txstat are already filled in dma_tx().
1309                          */
1310                         if (status->acked)
1311                                 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1312                         meta->txstat.retry_count = status->frame_count - 1;
1313                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, &(meta->txstat));
1314                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1315                         meta->skb = NULL;
1316                 } else {
1317                         /* No need to call free_descriptor_buffer here, as
1318                          * this is only the txhdr, which is not allocated.
1319                          */
1320                         assert(meta->skb == NULL);
1321                 }
1322
1323                 /* Everything unmapped and free'd. So it's not used anymore. */
1324                 ring->used_slots--;
1325
1326                 if (meta->is_last_fragment)
1327                         break;
1328                 slot = next_slot(ring, slot);
1329         }
1330         dev->stats.last_tx = jiffies;
1331         if (ring->stopped) {
1332                 assert(free_slots(ring) >= SLOTS_PER_PACKET);
1333                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1334                 ring->stopped = 0;
1335                 if (bcm43xx_debug(dev, BCM43xx_DBG_DMAVERBOSE)) {
1336                         dprintk(KERN_DEBUG PFX "Woke up TX ring %d\n",
1337                                 ring->index);
1338                 }
1339         }
1340
1341         spin_unlock(&ring->lock);
1342 }
1343
1344 void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
1345                               struct ieee80211_tx_queue_stats *stats)
1346 {
1347         const int nr_queues = dev->wl->hw->queues;
1348         struct bcm43xx_dmaring *ring;
1349         struct ieee80211_tx_queue_stats_data *data;
1350         unsigned long flags;
1351         int i;
1352
1353         for (i = 0; i < nr_queues; i++) {
1354                 data = &(stats->data[i]);
1355                 ring = priority_to_txring(dev, i);
1356
1357                 spin_lock_irqsave(&ring->lock, flags);
1358                 data->len = ring->used_slots / SLOTS_PER_PACKET;
1359                 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1360                 data->count = ring->nr_tx_packets;
1361                 spin_unlock_irqrestore(&ring->lock, flags);
1362         }
1363 }
1364
1365 static void dma_rx(struct bcm43xx_dmaring *ring,
1366                    int *slot)
1367 {
1368         const struct bcm43xx_dma_ops *ops = ring->ops;
1369         struct bcm43xx_dmadesc_generic *desc;
1370         struct bcm43xx_dmadesc_meta *meta;
1371         struct bcm43xx_rxhdr_fw4 *rxhdr;
1372         struct sk_buff *skb;
1373         u16 len;
1374         int err;
1375         dma_addr_t dmaaddr;
1376
1377         desc = ops->idx2desc(ring, *slot, &meta);
1378
1379         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1380         skb = meta->skb;
1381
1382         if (ring->index == 3) {
1383                 /* We received an xmit status. */
1384                 struct bcm43xx_hwtxstatus *hw = (struct bcm43xx_hwtxstatus *)skb->data;
1385                 int i = 0;
1386
1387                 while (hw->cookie == 0) {
1388                         if (i > 100)
1389                                 break;
1390                         i++;
1391                         udelay(2);
1392                         barrier();
1393                 }
1394                 bcm43xx_handle_hwtxstatus(ring->dev, hw);
1395                 /* recycle the descriptor buffer. */
1396                 sync_descbuffer_for_device(ring, meta->dmaaddr, ring->rx_buffersize);
1397
1398                 return;
1399         }
1400         rxhdr = (struct bcm43xx_rxhdr_fw4 *)skb->data;
1401         len = le16_to_cpu(rxhdr->frame_len);
1402         if (len == 0) {
1403                 int i = 0;
1404
1405                 do {
1406                         udelay(2);
1407                         barrier();
1408                         len = le16_to_cpu(rxhdr->frame_len);
1409                 } while (len == 0 && i++ < 5);
1410                 if (unlikely(len == 0)) {
1411                         /* recycle the descriptor buffer. */
1412                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1413                                                    ring->rx_buffersize);
1414                         goto drop;
1415                 }
1416         }
1417         if (unlikely(len > ring->rx_buffersize)) {
1418                 /* The data did not fit into one descriptor buffer
1419                  * and is split over multiple buffers.
1420                  * This should never happen, as we try to allocate buffers
1421                  * big enough. So simply ignore this packet.
1422                  */
1423                 int cnt = 0;
1424                 s32 tmp = len;
1425
1426                 while (1) {
1427                         desc = ops->idx2desc(ring, *slot, &meta);
1428                         /* recycle the descriptor buffer. */
1429                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1430                                                    ring->rx_buffersize);
1431                         *slot = next_slot(ring, *slot);
1432                         cnt++;
1433                         tmp -= ring->rx_buffersize;
1434                         if (tmp <= 0)
1435                                 break;
1436                 }
1437                 printkl(KERN_ERR PFX "DMA RX buffer too small "
1438                         "(len: %u, buffer: %u, nr-dropped: %d)\n",
1439                         len, ring->rx_buffersize, cnt);
1440                 goto drop;
1441         }
1442
1443         dmaaddr = meta->dmaaddr;
1444         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1445         if (unlikely(err)) {
1446                 dprintkl(KERN_ERR PFX "DMA RX: setup_rx_descbuffer() failed\n");
1447                 sync_descbuffer_for_device(ring, dmaaddr,
1448                                            ring->rx_buffersize);
1449                 goto drop;
1450         }
1451
1452         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1453         skb_put(skb, len + ring->frameoffset);
1454         skb_pull(skb, ring->frameoffset);
1455
1456         bcm43xx_rx(ring->dev, skb, rxhdr);
1457 drop:
1458         return;
1459 }
1460
1461 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
1462 {
1463         const struct bcm43xx_dma_ops *ops = ring->ops;
1464         int slot, current_slot;
1465         int used_slots = 0;
1466
1467         assert(!ring->tx);
1468         current_slot = ops->get_current_rxslot(ring);
1469         assert(current_slot >= 0 && current_slot < ring->nr_slots);
1470
1471         slot = ring->current_slot;
1472         for ( ; slot != current_slot; slot = next_slot(ring, slot)) {
1473                 dma_rx(ring, &slot);
1474                 update_max_used_slots(ring, ++used_slots);
1475         }
1476         ops->set_current_rxslot(ring, slot);
1477         ring->current_slot = slot;
1478 }
1479
1480 static void bcm43xx_dma_tx_suspend_ring(struct bcm43xx_dmaring *ring)
1481 {
1482         unsigned long flags;
1483
1484         spin_lock_irqsave(&ring->lock, flags);
1485         assert(ring->tx);
1486         ring->ops->tx_suspend(ring);
1487         spin_unlock_irqrestore(&ring->lock, flags);
1488 }
1489
1490 static void bcm43xx_dma_tx_resume_ring(struct bcm43xx_dmaring *ring)
1491 {
1492         unsigned long flags;
1493
1494         spin_lock_irqsave(&ring->lock, flags);
1495         assert(ring->tx);
1496         ring->ops->tx_resume(ring);
1497         spin_unlock_irqrestore(&ring->lock, flags);
1498 }
1499
1500 void bcm43xx_dma_tx_suspend(struct bcm43xx_wldev *dev)
1501 {
1502         bcm43xx_power_saving_ctl_bits(dev, -1, 1);
1503         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring0);
1504         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring1);
1505         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring2);
1506         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring3);
1507         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring4);
1508         bcm43xx_dma_tx_suspend_ring(dev->dma.tx_ring5);
1509 }
1510
1511 void bcm43xx_dma_tx_resume(struct bcm43xx_wldev *dev)
1512 {
1513         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring5);
1514         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring4);
1515         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring3);
1516         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring2);
1517         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring1);
1518         bcm43xx_dma_tx_resume_ring(dev->dma.tx_ring0);
1519         bcm43xx_power_saving_ctl_bits(dev, -1, -1);
1520 }