package/ath9k/src/drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18
  19 #include "ath9k.h"
  20 #include "hw.h"
  21 #include "reg.h"
  22 #include "phy.h"
  23 #include "initvals.h"
  24
  25 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
  26 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains);
  27 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
  28 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
  29                                            u_int8_t numChains);
  30 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
  31 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
  32                                          u_int8_t numChains);
  33
  34 static const u_int8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  35 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
  36
  37 static const struct hal_percal_data iq_cal_multi_sample = {
  38         IQ_MISMATCH_CAL,
  39         MAX_CAL_SAMPLES,
  40         PER_MIN_LOG_COUNT,
  41         ath9k_hw_iqcal_collect,
  42         ath9k_hw_iqcalibrate
  43 };
  44 static const struct hal_percal_data iq_cal_single_sample = {
  45         IQ_MISMATCH_CAL,
  46         MIN_CAL_SAMPLES,
  47         PER_MAX_LOG_COUNT,
  48         ath9k_hw_iqcal_collect,
  49         ath9k_hw_iqcalibrate
  50 };
  51 static const struct hal_percal_data adc_gain_cal_multi_sample = {
  52         ADC_GAIN_CAL,
  53         MAX_CAL_SAMPLES,
  54         PER_MIN_LOG_COUNT,
  55         ath9k_hw_adc_gaincal_collect,
  56         ath9k_hw_adc_gaincal_calibrate
  57 };
  58 static const struct hal_percal_data adc_gain_cal_single_sample = {
  59         ADC_GAIN_CAL,
  60         MIN_CAL_SAMPLES,
  61         PER_MAX_LOG_COUNT,
  62         ath9k_hw_adc_gaincal_collect,
  63         ath9k_hw_adc_gaincal_calibrate
  64 };
  65 static const struct hal_percal_data adc_dc_cal_multi_sample = {
  66         ADC_DC_CAL,
  67         MAX_CAL_SAMPLES,
  68         PER_MIN_LOG_COUNT,
  69         ath9k_hw_adc_dccal_collect,
  70         ath9k_hw_adc_dccal_calibrate
  71 };
  72 static const struct hal_percal_data adc_dc_cal_single_sample = {
  73         ADC_DC_CAL,
  74         MIN_CAL_SAMPLES,
  75         PER_MAX_LOG_COUNT,
  76         ath9k_hw_adc_dccal_collect,
  77         ath9k_hw_adc_dccal_calibrate
  78 };
  79 static const struct hal_percal_data adc_init_dc_cal = {
  80         ADC_DC_INIT_CAL,
  81         MIN_CAL_SAMPLES,
  82         INIT_LOG_COUNT,
  83         ath9k_hw_adc_dccal_collect,
  84         ath9k_hw_adc_dccal_calibrate
  85 };
  86
  87 static const struct ath_hal ar5416hal = {
  88         AR5416_MAGIC,
  89         0,
  90         0,
  91         NULL,
  92         NULL,
  93         CTRY_DEFAULT,
  94         0,
  95         0,
  96         0,
  97         0,
  98         0,
  99         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 100          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 101          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 102          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 103          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 104          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 105          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 106          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 107         },
 108 };
 109
 110 static struct hal_rate_table ar5416_11a_table = {
 111         8,
 112         {0},
 113         {
 114                 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
 115                 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
 116                 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
 117                 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
 118                 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
 119                 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
 120                 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
 121                 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
 122         },
 123 };
 124
 125 static struct hal_rate_table ar5416_11b_table = {
 126         4,
 127         {0},
 128         {
 129                 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 130                 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 131                 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
 132                 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
 133         },
 134 };
 135
 136 static struct hal_rate_table ar5416_11g_table = {
 137         12,
 138         {0},
 139         {
 140                 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 141                 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 142                 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 143                 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 144
 145                 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 146                 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 147                 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 148                 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 149                 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 150                 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 151                 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 152                 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
 153         },
 154 };
 155
 156 static struct hal_rate_table ar5416_11ng_table = {
 157         28,
 158         {0},
 159         {
 160                 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 161                 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 162                 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 163                 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 164
 165                 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 166                 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 167                 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 168                 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 169                 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 170                 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 171                 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 172                 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
 173                 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 4},
 174                 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 6},
 175                 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 6},
 176                 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 8},
 177                 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 8},
 178                 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 8},
 179                 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 8},
 180                 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 8},
 181                 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 4},
 182                 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 6},
 183                 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
 184                 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
 185                 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
 186                 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
 187                 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
 188                 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
 189         },
 190 };
 191
 192 static struct hal_rate_table ar5416_11na_table = {
 193         24,
 194         {0},
 195         {
 196                 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
 197                 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
 198                 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
 199                 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
 200                 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
 201                 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
 202                 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
 203                 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
 204                 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 0},
 205                 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 2},
 206                 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 2},
 207                 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 4},
 208                 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 4},
 209                 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 4},
 210                 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 4},
 211                 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 4},
 212                 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 0},
 213                 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 2},
 214                 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
 215                 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
 216                 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
 217                 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
 218                 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
 219                 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
 220         },
 221 };
 222
 223 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 224                                        const struct hal_channel *chan)
 225 {
 226         if (IS_CHAN_CCK(chan))
 227                 return WIRELESS_MODE_11b;
 228         if (IS_CHAN_G(chan))
 229                 return WIRELESS_MODE_11g;
 230         return WIRELESS_MODE_11a;
 231 }
 232
 233 static enum hal_bool ath9k_hw_wait(struct ath_hal *ah,
 234                             u_int reg,
 235                             u_int32_t mask,
 236                             u_int32_t val)
 237 {
 238         int i;
 239
 240         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 241                 if ((REG_READ(ah, reg) & mask) == val)
 242                         return AH_TRUE;
 243
 244                 udelay(AH_TIME_QUANTUM);
 245         }
 246         HDPRINTF(ah, HAL_DBG_PHY_IO,
 247                  "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 248                  __func__, reg, REG_READ(ah, reg), mask, val);
 249         return AH_FALSE;
 250 }
 251
 252 static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
 253                                    u_int16_t *data)
 254 {
 255         (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 256
 257         if (!ath9k_hw_wait(ah,
 258                            AR_EEPROM_STATUS_DATA,
 259                            AR_EEPROM_STATUS_DATA_BUSY |
 260                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
 261                 return AH_FALSE;
 262         }
 263
 264         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 265                    AR_EEPROM_STATUS_DATA_VAL);
 266
 267         return AH_TRUE;
 268 }
 269
 270 static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
 271 {
 272         struct ath_hal_5416 *ahp = AH5416(ah);
 273
 274         ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 275
 276         if (!ahp->ah_cal_mem) {
 277                 HDPRINTF(ah, HAL_DBG_EEPROM,
 278                          "%s: cannot remap eeprom region \n", __func__);
 279                 return HAL_EIO;
 280         }
 281
 282         return HAL_OK;
 283 }
 284
 285 static enum hal_bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
 286                                   u_int16_t *data)
 287 {
 288         struct ath_hal_5416 *ahp = AH5416(ah);
 289
 290         *data = ioread16(ahp->ah_cal_mem + off);
 291         return AH_TRUE;
 292 }
 293
 294 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 295 {
 296         u_int32_t val;
 297
 298         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 299
 300         if (val == 0xFF) {
 301                 val = REG_READ(ah, AR_SREV);
 302
 303                 ah->ah_macVersion =
 304                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 305
 306                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 307                 ah->ah_isPciExpress =
 308                         (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 309
 310         } else {
 311                 if (!AR_SREV_9100(ah))
 312                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 313
 314                 ah->ah_macRev = val & AR_SREV_REVISION;
 315
 316                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 317                         ah->ah_isPciExpress = AH_TRUE;
 318         }
 319 }
 320
 321 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n)
 322 {
 323         u_int32_t retval;
 324         int i;
 325
 326         for (i = 0, retval = 0; i < n; i++) {
 327                 retval = (retval << 1) | (val & 1);
 328                 val >>= 1;
 329         }
 330         return retval;
 331 }
 332
 333 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 334 {
 335         int i;
 336
 337         ah->ah_config.ath_hal_dma_beacon_response_time = 2;
 338         ah->ah_config.ath_hal_sw_beacon_response_time = 10;
 339         ah->ah_config.ath_hal_additional_swba_backoff = 0;
 340         ah->ah_config.ath_hal_6mb_ack = 0x0;
 341         ah->ah_config.ath_hal_cwmIgnoreExtCCA = 0;
 342         ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
 343         ah->ah_config.ath_hal_pcieL1SKPEnable = 0;
 344         ah->ah_config.ath_hal_pcieClockReq = 0;
 345         ah->ah_config.ath_hal_pciePowerReset = 0x100;
 346         ah->ah_config.ath_hal_pcieRestore = 0;
 347         ah->ah_config.ath_hal_pcieWaen = 0;
 348         ah->ah_config.ath_hal_analogShiftReg = 1;
 349         ah->ah_config.ath_hal_htEnable = 1;
 350         ah->ah_config.ath_hal_ofdmTrigLow = 200;
 351         ah->ah_config.ath_hal_ofdmTrigHigh = 500;
 352         ah->ah_config.ath_hal_cckTrigHigh = 200;
 353         ah->ah_config.ath_hal_cckTrigLow = 100;
 354         ah->ah_config.ath_hal_enableANI = 0;
 355         ah->ah_config.ath_hal_noiseImmunityLvl = 4;
 356         ah->ah_config.ath_hal_ofdmWeakSigDet = 1;
 357         ah->ah_config.ath_hal_cckWeakSigThr = 0;
 358         ah->ah_config.ath_hal_spurImmunityLvl = 2;
 359         ah->ah_config.ath_hal_firStepLvl = 0;
 360         ah->ah_config.ath_hal_rssiThrHigh = 40;
 361         ah->ah_config.ath_hal_rssiThrLow = 7;
 362         ah->ah_config.ath_hal_diversityControl = 0;
 363         ah->ah_config.ath_hal_antennaSwitchSwap = 0;
 364
 365         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 366                 ah->ah_config.ath_hal_spurChans[i][0] = AR_NO_SPUR;
 367                 ah->ah_config.ath_hal_spurChans[i][1] = AR_NO_SPUR;
 368         }
 369
 370         ah->ah_config.ath_hal_intrMitigation = 0;
 371         ah->ah_config.ath_hal_debug = 0;
 372 }
 373
 374 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
 375                                          struct hal_channel *chan)
 376 {
 377         if (!AR_SREV_5416_V20_OR_LATER(ah)
 378             || AR_SREV_9280_10_OR_LATER(ah))
 379                 return;
 380
 381         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 382 }
 383
 384 static inline void ath9k_hw_init_bb(struct ath_hal *ah,
 385                                     struct hal_channel *chan)
 386 {
 387         u_int32_t synthDelay;
 388
 389         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 390         if (IS_CHAN_CCK(chan))
 391                 synthDelay = (4 * synthDelay) / 22;
 392         else
 393                 synthDelay /= 10;
 394
 395         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 396
 397         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 398 }
 399
 400 static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
 401                                                  enum hal_opmode opmode)
 402 {
 403         struct ath_hal_5416 *ahp = AH5416(ah);
 404
 405         ahp->ah_maskReg = AR_IMR_TXERR |
 406                 AR_IMR_TXURN |
 407                 AR_IMR_RXERR |
 408                 AR_IMR_RXORN |
 409                 AR_IMR_BCNMISC;
 410
 411         if (ahp->ah_intrMitigation)
 412                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 413         else
 414                 ahp->ah_maskReg |= AR_IMR_RXOK;
 415
 416         ahp->ah_maskReg |= AR_IMR_TXOK;
 417
 418         if (opmode == HAL_M_HOSTAP)
 419                 ahp->ah_maskReg |= AR_IMR_MIB;
 420
 421         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
 422         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
 423
 424         if (!AR_SREV_9100(ah)) {
 425                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 426                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 427                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 428         }
 429 }
 430
 431 static inline void ath9k_hw_init_qos(struct ath_hal *ah)
 432 {
 433         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 434         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 435
 436         REG_WRITE(ah, AR_QOS_NO_ACK,
 437                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 438                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 439                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 440
 441         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 442         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 443         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 444         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 445         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 446 }
 447
 448 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
 449                                       u_int reg,
 450                                       u_int32_t mask,
 451                                       u_int32_t shift,
 452                                       u_int32_t val)
 453 {
 454         u_int32_t regVal;
 455
 456         regVal = REG_READ(ah, reg) & ~mask;
 457         regVal |= (val << shift) & mask;
 458
 459         REG_WRITE(ah, reg, regVal);
 460
 461         if (ah->ah_config.ath_hal_analogShiftReg)
 462                 udelay(100);
 463
 464         return;
 465 }
 466
 467 static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 468                                             enum hal_freq_band freq_band)
 469 {
 470         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 471         struct modal_eep_header *pModal =
 472                 &(eep->modalHeader[HAL_FREQ_BAND_2GHZ == freq_band]);
 473         struct base_eep_header *pBase = &eep->baseEepHeader;
 474         u_int8_t num_ant_config;
 475
 476         num_ant_config = 1;
 477
 478         if (pBase->version >= 0x0E0D)
 479                 if (pModal->useAnt1)
 480                         num_ant_config += 1;
 481
 482         return num_ant_config;
 483 }
 484
 485 static enum hal_status
 486 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 487                                 struct hal_channel_internal *chan,
 488                                 u_int8_t index,
 489                                 u_int16_t *config)
 490 {
 491         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 492         struct modal_eep_header *pModal =
 493                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 494         struct base_eep_header *pBase = &eep->baseEepHeader;
 495
 496         switch (index) {
 497         case 0:
 498                 *config = pModal->antCtrlCommon & 0xFFFF;
 499                 return HAL_OK;
 500         case 1:
 501                 if (pBase->version >= 0x0E0D) {
 502                         if (pModal->useAnt1) {
 503                                 *config =
 504                                 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
 505                                 return HAL_OK;
 506                         }
 507                 }
 508                 break;
 509         default:
 510                 break;
 511         }
 512
 513         return HAL_EINVAL;
 514 }
 515
 516 static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
 517                                                 u_int off,
 518                                                 u_int16_t *data)
 519 {
 520         if (ath9k_hw_use_flash(ah))
 521                 return ath9k_hw_flash_read(ah, off, data);
 522         else
 523                 return ath9k_hw_eeprom_read(ah, off, data);
 524 }
 525
 526 static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 527 {
 528         struct ath_hal_5416 *ahp = AH5416(ah);
 529         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 530         u_int16_t *eep_data;
 531         int addr, ar5416_eep_start_loc = 0;
 532
 533         if (!ath9k_hw_use_flash(ah)) {
 534                 HDPRINTF(ah, HAL_DBG_EEPROM,
 535                          "%s: Reading from EEPROM, not flash\n", __func__);
 536                 ar5416_eep_start_loc = 256;
 537         }
 538         if (AR_SREV_9100(ah))
 539                 ar5416_eep_start_loc = 256;
 540
 541         eep_data = (u_int16_t *) eep;
 542         for (addr = 0;
 543              addr < sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
 544              addr++) {
 545                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 546                                          eep_data)) {
 547                         HDPRINTF(ah, HAL_DBG_EEPROM,
 548                                  "%s: Unable to read eeprom region \n",
 549                                  __func__);
 550                         return AH_FALSE;
 551                 }
 552                 eep_data++;
 553         }
 554         return AH_TRUE;
 555 }
 556
 557 /* XXX: Clean me up, make me more legible */
 558 static enum hal_bool
 559 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 560                                  struct hal_channel_internal *chan)
 561 {
 562         struct modal_eep_header *pModal;
 563         int i, regChainOffset;
 564         struct ath_hal_5416 *ahp = AH5416(ah);
 565         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 566         u_int8_t txRxAttenLocal;
 567         u_int16_t ant_config;
 568
 569         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 570
 571         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 572
 573         ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
 574         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
 575
 576         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 577                 if (AR_SREV_9280(ah)) {
 578                         if (i >= 2)
 579                                 break;
 580                 }
 581
 582                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
 583                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
 584                     && (i != 0))
 585                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 586                 else
 587                         regChainOffset = i * 0x1000;
 588
 589                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 590                           pModal->antCtrlChain[i]);
 591
 592                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 593                           (REG_READ(ah,
 594                                     AR_PHY_TIMING_CTRL4(0) +
 595                                     regChainOffset) &
 596                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 597                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 598                           SM(pModal->iqCalICh[i],
 599                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 600                           SM(pModal->iqCalQCh[i],
 601                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 602
 603                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 604                         if ((eep->baseEepHeader.version &
 605                         AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) {
 606                                 txRxAttenLocal = pModal->txRxAttenCh[i];
 607                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 608                                         OS_REG_RMW_FIELD(ah,
 609                                                  AR_PHY_GAIN_2GHZ +
 610                                                  regChainOffset,
 611                                          AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 612                                                  pModal->
 613                                                  bswMargin[i]);
 614                                         OS_REG_RMW_FIELD(ah,
 615                                                  AR_PHY_GAIN_2GHZ +
 616                                                  regChainOffset,
 617                                                  AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 618                                                  pModal->
 619                                                  bswAtten[i]);
 620                                         OS_REG_RMW_FIELD(ah,
 621                                                  AR_PHY_GAIN_2GHZ +
 622                                                  regChainOffset,
 623                                          AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 624                                                  pModal->
 625                                                  xatten2Margin[i]);
 626                                         OS_REG_RMW_FIELD(ah,
 627                                                  AR_PHY_GAIN_2GHZ +
 628                                                  regChainOffset,
 629                                                  AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 630                                                  pModal->
 631                                                  xatten2Db[i]);
 632                                 } else {
 633                                         REG_WRITE(ah,
 634                                                   AR_PHY_GAIN_2GHZ +
 635                                                   regChainOffset,
 636                                                   (REG_READ(ah,
 637                                                             AR_PHY_GAIN_2GHZ +
 638                                                             regChainOffset) &
 639                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 640                                                   | SM(pModal->
 641                                                bswMargin[i],
 642                                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 643                                         REG_WRITE(ah,
 644                                                   AR_PHY_GAIN_2GHZ +
 645                                                   regChainOffset,
 646                                                   (REG_READ(ah,
 647                                                             AR_PHY_GAIN_2GHZ +
 648                                                             regChainOffset) &
 649                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 650                                                   | SM(pModal->bswAtten[i],
 651                                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 652                                 }
 653                         }
 654                         if (AR_SREV_9280_10_OR_LATER(ah)) {
 655                                 OS_REG_RMW_FIELD(ah,
 656                                                  AR_PHY_RXGAIN +
 657                                                  regChainOffset,
 658                                                  AR9280_PHY_RXGAIN_TXRX_ATTEN,
 659                                                  txRxAttenLocal);
 660                                 OS_REG_RMW_FIELD(ah,
 661                                                  AR_PHY_RXGAIN +
 662                                                  regChainOffset,
 663                                                  AR9280_PHY_RXGAIN_TXRX_MARGIN,
 664                                                  pModal->rxTxMarginCh[i]);
 665                         } else {
 666                                 REG_WRITE(ah,
 667                                           AR_PHY_RXGAIN + regChainOffset,
 668                                           (REG_READ(ah,
 669                                                     AR_PHY_RXGAIN +
 670                                                     regChainOffset) &
 671                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
 672                                           SM(txRxAttenLocal,
 673                                              AR_PHY_RXGAIN_TXRX_ATTEN));
 674                                 REG_WRITE(ah,
 675                                           AR_PHY_GAIN_2GHZ +
 676                                           regChainOffset,
 677                                           (REG_READ(ah,
 678                                                     AR_PHY_GAIN_2GHZ +
 679                                                     regChainOffset) &
 680                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 681                                           SM(pModal->rxTxMarginCh[i],
 682                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 683                         }
 684                 }
 685         }
 686
 687         if (AR_SREV_9280_10_OR_LATER(ah)) {
 688                 if (IS_CHAN_2GHZ(chan)) {
 689                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 690                                                   AR_AN_RF2G1_CH0_OB,
 691                                                   AR_AN_RF2G1_CH0_OB_S,
 692                                                   pModal->ob);
 693                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 694                                                   AR_AN_RF2G1_CH0_DB,
 695                                                   AR_AN_RF2G1_CH0_DB_S,
 696                                                   pModal->db);
 697                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 698                                                   AR_AN_RF2G1_CH1_OB,
 699                                                   AR_AN_RF2G1_CH1_OB_S,
 700                                                   pModal->ob_ch1);
 701                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 702                                                   AR_AN_RF2G1_CH1_DB,
 703                                                   AR_AN_RF2G1_CH1_DB_S,
 704                                                   pModal->db_ch1);
 705                 } else {
 706                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 707                                                   AR_AN_RF5G1_CH0_OB5,
 708                                                   AR_AN_RF5G1_CH0_OB5_S,
 709                                                   pModal->ob);
 710                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 711                                                   AR_AN_RF5G1_CH0_DB5,
 712                                                   AR_AN_RF5G1_CH0_DB5_S,
 713                                                   pModal->db);
 714                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 715                                                   AR_AN_RF5G1_CH1_OB5,
 716                                                   AR_AN_RF5G1_CH1_OB5_S,
 717                                                   pModal->ob_ch1);
 718                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 719                                                   AR_AN_RF5G1_CH1_DB5,
 720                                                   AR_AN_RF5G1_CH1_DB5_S,
 721                                                   pModal->db_ch1);
 722                 }
 723                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 724                                           AR_AN_TOP2_XPABIAS_LVL,
 725                                           AR_AN_TOP2_XPABIAS_LVL_S,
 726                                           pModal->xpaBiasLvl);
 727                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 728                                           AR_AN_TOP2_LOCALBIAS,
 729                                           AR_AN_TOP2_LOCALBIAS_S,
 730                                           pModal->local_bias);
 731                 HDPRINTF(NULL, HAL_DBG_UNMASKABLE, "ForceXPAon: %d\n",
 732                          pModal->force_xpaon);
 733                 OS_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 734                                  pModal->force_xpaon);
 735         }
 736
 737         OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 738                          pModal->switchSettling);
 739         OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 740                          pModal->adcDesiredSize);
 741
 742         if (!AR_SREV_9280_10_OR_LATER(ah))
 743                 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 744                                  AR_PHY_DESIRED_SZ_PGA,
 745                                  pModal->pgaDesiredSize);
 746
 747         REG_WRITE(ah, AR_PHY_RF_CTL4,
 748                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 749                   | SM(pModal->txEndToXpaOff,
 750                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 751                   | SM(pModal->txFrameToXpaOn,
 752                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 753                   | SM(pModal->txFrameToXpaOn,
 754                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 755
 756         OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 757                          pModal->txEndToRxOn);
 758         if (AR_SREV_9280_10_OR_LATER(ah)) {
 759                 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 760                                  pModal->thresh62);
 761                 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 762                                  AR_PHY_EXT_CCA0_THRESH62,
 763                                  pModal->thresh62);
 764         } else {
 765                 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 766                                  pModal->thresh62);
 767                 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 768                                  AR_PHY_EXT_CCA_THRESH62,
 769                                  pModal->thresh62);
 770         }
 771
 772         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 773             AR5416_EEP_MINOR_VER_2) {
 774                 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 775                                  AR_PHY_TX_END_DATA_START,
 776                                  pModal->txFrameToDataStart);
 777                 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 778                                  pModal->txFrameToPaOn);
 779         }
 780
 781         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 782             AR5416_EEP_MINOR_VER_3) {
 783                 if (IS_CHAN_HT40(chan))
 784                         OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 785                                          AR_PHY_SETTLING_SWITCH,
 786                                          pModal->swSettleHt40);
 787         }
 788
 789         return AH_TRUE;
 790 }
 791
 792 static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 793 {
 794         u_int32_t sum = 0, el;
 795         u_int16_t *eepdata;
 796         int i;
 797         struct ath_hal_5416 *ahp = AH5416(ah);
 798         enum hal_bool need_swap = AH_FALSE;
 799         struct ar5416_eeprom *eep =
 800                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
 801
 802         if (!ath9k_hw_use_flash(ah)) {
 803                 u_int16_t magic, magic2;
 804                 int addr;
 805
 806                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 807                                         &magic)) {
 808                         HDPRINTF(ah, HAL_DBG_EEPROM,
 809                                  "%s: Reading Magic # failed\n", __func__);
 810                         return AH_FALSE;
 811                 }
 812                 HDPRINTF(ah, HAL_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
 813                          __func__, magic);
 814
 815                 if (magic != AR5416_EEPROM_MAGIC) {
 816                         magic2 = swab16(magic);
 817
 818                         if (magic2 == AR5416_EEPROM_MAGIC) {
 819                                 need_swap = AH_TRUE;
 820                                 eepdata = (u_int16_t *) (&ahp->ah_eeprom);
 821
 822                                 for (addr = 0;
 823                                      addr <
 824                                              sizeof(struct ar5416_eeprom) /
 825                                              sizeof(u_int16_t); addr++) {
 826                                         u_int16_t temp;
 827
 828                                         temp = swab16(*eepdata);
 829                                         *eepdata = temp;
 830                                         eepdata++;
 831
 832                                         HDPRINTF(ah, HAL_DBG_EEPROM_DUMP,
 833                                                  "0x%04X  ", *eepdata);
 834                                         if (((addr + 1) % 6) == 0)
 835                                                 HDPRINTF(ah,
 836                                                          HAL_DBG_EEPROM_DUMP,
 837                                                          "\n");
 838                                 }
 839                         } else {
 840                                 HDPRINTF(ah, HAL_DBG_EEPROM,
 841                                          "Invalid EEPROM Magic. "
 842                                         "endianness missmatch.\n");
 843                                 return HAL_EEBADSUM;
 844                         }
 845                 }
 846         }
 847         HDPRINTF(ah, HAL_DBG_EEPROM, "need_swap = %s.\n",
 848                  need_swap ? "True" : "False");
 849
 850         if (need_swap)
 851                 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
 852         else
 853                 el = ahp->ah_eeprom.baseEepHeader.length;
 854
 855         if (el < sizeof(struct ar5416_eeprom))
 856                 el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
 857         else
 858                 el = el / sizeof(u_int16_t);
 859
 860         eepdata = (u_int16_t *) (&ahp->ah_eeprom);
 861
 862         for (i = 0; i < el; i++)
 863                 sum ^= *eepdata++;
 864
 865         if (need_swap) {
 866                 u_int32_t integer, j;
 867                 u_int16_t word;
 868
 869                 HDPRINTF(ah, HAL_DBG_EEPROM,
 870                          "EEPROM Endianness is not native.. Changing \n");
 871
 872                 word = swab16(eep->baseEepHeader.length);
 873                 eep->baseEepHeader.length = word;
 874
 875                 word = swab16(eep->baseEepHeader.checksum);
 876                 eep->baseEepHeader.checksum = word;
 877
 878                 word = swab16(eep->baseEepHeader.version);
 879                 eep->baseEepHeader.version = word;
 880
 881                 word = swab16(eep->baseEepHeader.regDmn[0]);
 882                 eep->baseEepHeader.regDmn[0] = word;
 883
 884                 word = swab16(eep->baseEepHeader.regDmn[1]);
 885                 eep->baseEepHeader.regDmn[1] = word;
 886
 887                 word = swab16(eep->baseEepHeader.rfSilent);
 888                 eep->baseEepHeader.rfSilent = word;
 889
 890                 word = swab16(eep->baseEepHeader.blueToothOptions);
 891                 eep->baseEepHeader.blueToothOptions = word;
 892
 893                 word = swab16(eep->baseEepHeader.deviceCap);
 894                 eep->baseEepHeader.deviceCap = word;
 895
 896                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 897                         struct modal_eep_header *pModal =
 898                                 &eep->modalHeader[j];
 899                         integer = swab32(pModal->antCtrlCommon);
 900                         pModal->antCtrlCommon = integer;
 901
 902                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 903                                 integer = swab32(pModal->antCtrlChain[i]);
 904                                 pModal->antCtrlChain[i] = integer;
 905                         }
 906
 907                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 908                                 word = swab16(pModal->spurChans[i].spurChan);
 909                                 pModal->spurChans[i].spurChan = word;
 910                         }
 911                 }
 912         }
 913
 914         if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
 915             ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
 916                 HDPRINTF(ah, HAL_DBG_EEPROM,
 917                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 918                          sum, ar5416_get_eep_ver(ahp));
 919                 return HAL_EEBADSUM;
 920         }
 921
 922         return HAL_OK;
 923 }
 924
 925 static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
 926 {
 927         u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 928         u_int32_t regHold[2];
 929         u_int32_t patternData[4] = { 0x55555555,
 930                                      0xaaaaaaaa,
 931                                      0x66666666,
 932                                      0x99999999 };
 933         int i, j;
 934
 935         for (i = 0; i < 2; i++) {
 936                 u_int32_t addr = regAddr[i];
 937                 u_int32_t wrData, rdData;
 938
 939                 regHold[i] = REG_READ(ah, addr);
 940                 for (j = 0; j < 0x100; j++) {
 941                         wrData = (j << 16) | j;
 942                         REG_WRITE(ah, addr, wrData);
 943                         rdData = REG_READ(ah, addr);
 944                         if (rdData != wrData) {
 945                                 HDPRINTF(ah, HAL_DBG_REG_IO,
 946                                  "%s: address test failed "
 947                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 948                                  __func__, addr, wrData, rdData);
 949                                 return AH_FALSE;
 950                         }
 951                 }
 952                 for (j = 0; j < 4; j++) {
 953                         wrData = patternData[j];
 954                         REG_WRITE(ah, addr, wrData);
 955                         rdData = REG_READ(ah, addr);
 956                         if (wrData != rdData) {
 957                                 HDPRINTF(ah, HAL_DBG_REG_IO,
 958                                  "%s: address test failed "
 959                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 960                                  __func__, addr, wrData, rdData);
 961                                 return AH_FALSE;
 962                         }
 963                 }
 964                 REG_WRITE(ah, regAddr[i], regHold[i]);
 965         }
 966         udelay(100);
 967         return AH_TRUE;
 968 }
 969
 970 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
 971 {
 972         u_int32_t bits = REG_READ(ah, AR_RX_FILTER);
 973         u_int32_t phybits = REG_READ(ah, AR_PHY_ERR);
 974
 975         if (phybits & AR_PHY_ERR_RADAR)
 976                 bits |= HAL_RX_FILTER_PHYRADAR;
 977         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
 978                 bits |= HAL_RX_FILTER_PHYERR;
 979         return bits;
 980 }
 981
 982 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
 983 {
 984         u_int32_t phybits;
 985
 986         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
 987         phybits = 0;
 988         if (bits & HAL_RX_FILTER_PHYRADAR)
 989                 phybits |= AR_PHY_ERR_RADAR;
 990         if (bits & HAL_RX_FILTER_PHYERR)
 991                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
 992         REG_WRITE(ah, AR_PHY_ERR, phybits);
 993
 994         if (phybits)
 995                 REG_WRITE(ah, AR_RXCFG,
 996                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
 997         else
 998                 REG_WRITE(ah, AR_RXCFG,
 999                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
1000 }
1001
1002 enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
1003                                      enum hal_capability_type type,
1004                                      u_int32_t capability,
1005                                      u_int32_t setting,
1006                                      enum hal_status *status)
1007 {
1008         struct ath_hal_5416 *ahp = AH5416(ah);
1009         u_int32_t v;
1010
1011         switch (type) {
1012         case HAL_CAP_TKIP_MIC:
1013                 if (setting)
1014                         ahp->ah_staId1Defaults |=
1015                                 AR_STA_ID1_CRPT_MIC_ENABLE;
1016                 else
1017                         ahp->ah_staId1Defaults &=
1018                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
1019                 return AH_TRUE;
1020         case HAL_CAP_DIVERSITY:
1021                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1022                 if (setting)
1023                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1024                 else
1025                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1026                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1027                 return AH_TRUE;
1028         case HAL_CAP_MCAST_KEYSRCH:
1029                 if (setting)
1030                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1031                 else
1032                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1033                 return AH_TRUE;
1034         case HAL_CAP_TSF_ADJUST:
1035                 if (setting)
1036                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1037                 else
1038                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1039                 return AH_TRUE;
1040         default:
1041                 return AH_FALSE;
1042         }
1043 }
1044
1045 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1046 {
1047         u_int32_t val[ATH9K_NUM_DMA_DEBUG_REGS];
1048         int qcuOffset = 0, dcuOffset = 0;
1049         u_int32_t *qcuBase = &val[0], *dcuBase = &val[4];
1050         int i;
1051
1052         REG_WRITE(ah, AR_MACMISC,
1053                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1054                    (AR_MACMISC_MISC_OBS_BUS_1 <<
1055                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1056
1057         HDPRINTF(ah, HAL_DBG_REG_IO, "Raw DMA Debug values:\n");
1058         for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1059                 if (i % 4 == 0)
1060                         HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1061
1062                 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1063                 HDPRINTF(ah, HAL_DBG_REG_IO, "%d: %08x ", i, val[i]);
1064         }
1065
1066         HDPRINTF(ah, HAL_DBG_REG_IO, "\n\n");
1067         HDPRINTF(ah, HAL_DBG_REG_IO,
1068                  "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1069
1070         for (i = 0; i < ATH9K_NUM_QUEUES;
1071              i++, qcuOffset += 4, dcuOffset += 5) {
1072                 if (i == 8) {
1073                         qcuOffset = 0;
1074                         qcuBase++;
1075                 }
1076
1077                 if (i == 6) {
1078                         dcuOffset = 0;
1079                         dcuBase++;
1080                 }
1081
1082                 HDPRINTF(ah, HAL_DBG_REG_IO,
1083                          "%2d          %2x      %1x     %2x           %2x\n",
1084                          i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1085                          (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1086                                                              3),
1087                          val[2] & (0x7 << (i * 3)) >> (i * 3),
1088                          (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1089         }
1090
1091         HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1092         HDPRINTF(ah, HAL_DBG_REG_IO,
1093                  "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
1094                  (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1095         HDPRINTF(ah, HAL_DBG_REG_IO,
1096                  "qcu_complete state: %2x    dcu_complete state:     %2x\n",
1097                  (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1098         HDPRINTF(ah, HAL_DBG_REG_IO,
1099                  "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
1100                  (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1101         HDPRINTF(ah, HAL_DBG_REG_IO,
1102                  "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
1103                  (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1104         HDPRINTF(ah, HAL_DBG_REG_IO,
1105                  "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
1106                  (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1107         HDPRINTF(ah, HAL_DBG_REG_IO,
1108                  "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
1109                  (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1110
1111         HDPRINTF(ah, HAL_DBG_REG_IO, "pcu observe 0x%x \n",
1112                  REG_READ(ah, AR_OBS_BUS_1));
1113         HDPRINTF(ah, HAL_DBG_REG_IO, "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1114 }
1115
1116 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1117                                         u_int32_t *rxc_pcnt,
1118                                         u_int32_t *rxf_pcnt,
1119                                         u_int32_t *txf_pcnt)
1120 {
1121         static u_int32_t cycles, rx_clear, rx_frame, tx_frame;
1122         u_int32_t good = 1;
1123
1124         u_int32_t rc = REG_READ(ah, AR_RCCNT);
1125         u_int32_t rf = REG_READ(ah, AR_RFCNT);
1126         u_int32_t tf = REG_READ(ah, AR_TFCNT);
1127         u_int32_t cc = REG_READ(ah, AR_CCCNT);
1128
1129         if (cycles == 0 || cycles > cc) {
1130                 HDPRINTF(ah, HAL_DBG_CHANNEL,
1131                          "%s: cycle counter wrap. ExtBusy = 0\n",
1132                          __func__);
1133                 good = 0;
1134         } else {
1135                 u_int32_t cc_d = cc - cycles;
1136                 u_int32_t rc_d = rc - rx_clear;
1137                 u_int32_t rf_d = rf - rx_frame;
1138                 u_int32_t tf_d = tf - tx_frame;
1139
1140                 if (cc_d != 0) {
1141                         *rxc_pcnt = rc_d * 100 / cc_d;
1142                         *rxf_pcnt = rf_d * 100 / cc_d;
1143                         *txf_pcnt = tf_d * 100 / cc_d;
1144                 } else {
1145                         good = 0;
1146                 }
1147         }
1148
1149         cycles = cc;
1150         rx_frame = rf;
1151         rx_clear = rc;
1152         tx_frame = tf;
1153
1154         return good;
1155 }
1156
1157 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode)
1158 {
1159         u_int32_t macmode;
1160
1161         if (mode == HAL_HT_MACMODE_2040 &&
1162             !ah->ah_config.ath_hal_cwmIgnoreExtCCA)
1163                 macmode = AR_2040_JOINED_RX_CLEAR;
1164         else
1165                 macmode = 0;
1166
1167         REG_WRITE(ah, AR_2040_MODE, macmode);
1168 }
1169
1170 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1171 {
1172         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1173 }
1174
1175
1176 static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
1177                                               void __iomem *mem,
1178                                               enum hal_status *status)
1179 {
1180         static const u_int8_t defbssidmask[ETH_ALEN] =
1181                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1182         struct ath_hal_5416 *ahp;
1183         struct ath_hal *ah;
1184
1185         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1186         if (ahp == NULL) {
1187                 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
1188                          "%s: cannot allocate memory for state block\n",
1189                          __func__);
1190                 *status = HAL_ENOMEM;
1191                 return NULL;
1192         }
1193
1194         ah = &ahp->ah;
1195
1196         memcpy(&ahp->ah, &ar5416hal, sizeof(struct ath_hal));
1197
1198         ah->ah_sc = sc;
1199         ah->ah_sh = mem;
1200
1201         ah->ah_devid = devid;
1202         ah->ah_subvendorid = 0;
1203
1204         ah->ah_flags = 0;
1205         if ((devid == AR5416_AR9100_DEVID))
1206                 ah->ah_macVersion = AR_SREV_VERSION_9100;
1207         if (!AR_SREV_9100(ah))
1208                 ah->ah_flags = AH_USE_EEPROM;
1209
1210         ah->ah_powerLimit = MAX_RATE_POWER;
1211         ah->ah_tpScale = HAL_TP_SCALE_MAX;
1212
1213         ahp->ah_atimWindow = 0;
1214         ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl;
1215         ahp->ah_antennaSwitchSwap =
1216                 ah->ah_config.ath_hal_antennaSwitchSwap;
1217
1218         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1219         ahp->ah_beaconInterval = 100;
1220         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1221         ahp->ah_slottime = (u_int) -1;
1222         ahp->ah_acktimeout = (u_int) -1;
1223         ahp->ah_ctstimeout = (u_int) -1;
1224         ahp->ah_globaltxtimeout = (u_int) -1;
1225         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1226
1227         ahp->ah_gBeaconRate = 0;
1228
1229         return ahp;
1230 }
1231
1232 static enum hal_status ath9k_hw_eeprom_attach(struct ath_hal *ah)
1233 {
1234         enum hal_status status;
1235
1236         if (ath9k_hw_use_flash(ah))
1237                 ath9k_hw_flash_map(ah);
1238
1239         if (!ath9k_hw_fill_eeprom(ah))
1240                 return HAL_EIO;
1241
1242         status = ath9k_hw_check_eeprom(ah);
1243
1244         return status;
1245 }
1246
1247 u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1248                               enum eeprom_param param)
1249 {
1250         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1251         struct modal_eep_header *pModal = eep->modalHeader;
1252         struct base_eep_header *pBase = &eep->baseEepHeader;
1253
1254         switch (param) {
1255         case EEP_NFTHRESH_5:
1256                 return -pModal[0].noiseFloorThreshCh[0];
1257         case EEP_NFTHRESH_2:
1258                 return -pModal[1].noiseFloorThreshCh[0];
1259         case AR_EEPROM_MAC(0):
1260                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1261         case AR_EEPROM_MAC(1):
1262                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1263         case AR_EEPROM_MAC(2):
1264                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1265         case EEP_REG_0:
1266                 return pBase->regDmn[0];
1267         case EEP_REG_1:
1268                 return pBase->regDmn[1];
1269         case EEP_OP_CAP:
1270                 return pBase->deviceCap;
1271         case EEP_OP_MODE:
1272                 return pBase->opCapFlags;
1273         case EEP_RF_SILENT:
1274                 return pBase->rfSilent;
1275         case EEP_OB_5:
1276                 return pModal[0].ob;
1277         case EEP_DB_5:
1278                 return pModal[0].db;
1279         case EEP_OB_2:
1280                 return pModal[1].ob;
1281         case EEP_DB_2:
1282                 return pModal[1].db;
1283         case EEP_MINOR_REV:
1284                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1285         case EEP_TX_MASK:
1286                 return pBase->txMask;
1287         case EEP_RX_MASK:
1288                 return pBase->rxMask;
1289         default:
1290                 return 0;
1291         }
1292 }
1293
1294 static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
1295 {
1296         u_int32_t val;
1297         int i;
1298
1299         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1300         for (i = 0; i < 8; i++)
1301                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1302         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1303         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1304         return ath9k_hw_reverse_bits(val, 8);
1305 }
1306
1307 static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
1308 {
1309         u_int32_t sum;
1310         int i;
1311         u_int16_t eeval;
1312         struct ath_hal_5416 *ahp = AH5416(ah);
1313         DECLARE_MAC_BUF(mac);
1314
1315         sum = 0;
1316         for (i = 0; i < 3; i++) {
1317                 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1318                 sum += eeval;
1319                 ahp->ah_macaddr[2 * i] = eeval >> 8;
1320                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1321         }
1322         if (sum == 0 || sum == 0xffff * 3) {
1323                 HDPRINTF(ah, HAL_DBG_EEPROM,
1324                          "%s: mac address read failed: %s\n", __func__,
1325                          print_mac(mac, ahp->ah_macaddr));
1326                 return HAL_EEBADMAC;
1327         }
1328
1329         return HAL_OK;
1330 }
1331
1332 static inline int16_t ath9k_hw_interpolate(u_int16_t target,
1333                                            u_int16_t srcLeft,
1334                                            u_int16_t srcRight,
1335                                            int16_t targetLeft,
1336                                            int16_t targetRight)
1337 {
1338         int16_t rv;
1339
1340         if (srcRight == srcLeft) {
1341                 rv = targetLeft;
1342         } else {
1343                 rv = (int16_t) (((target - srcLeft) * targetRight +
1344                                  (srcRight - target) * targetLeft) /
1345                                 (srcRight - srcLeft));
1346         }
1347         return rv;
1348 }
1349
1350 static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
1351                                            enum hal_bool is2GHz)
1352 {
1353
1354         if (fbin == AR5416_BCHAN_UNUSED)
1355                 return fbin;
1356
1357         return (u_int16_t) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1358 }
1359
1360 static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1361                                                u_int16_t i,
1362                                                enum hal_bool is2GHz)
1363 {
1364         struct ath_hal_5416 *ahp = AH5416(ah);
1365         struct ar5416_eeprom *eep =
1366                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1367         u_int16_t spur_val = AR_NO_SPUR;
1368
1369         HDPRINTF(ah, HAL_DBG_ANI,
1370                  "Getting spur idx %d is2Ghz. %d val %x\n",
1371                  i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]);
1372
1373         switch (ah->ah_config.ath_hal_spurMode) {
1374         case SPUR_DISABLE:
1375                 break;
1376         case SPUR_ENABLE_IOCTL:
1377                 spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz];
1378                 HDPRINTF(ah, HAL_DBG_ANI,
1379                          "Getting spur val from new loc. %d\n", spur_val);
1380                 break;
1381         case SPUR_ENABLE_EEPROM:
1382                 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1383                 break;
1384
1385         }
1386         return spur_val;
1387 }
1388
1389 static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
1390 {
1391         enum hal_bool rfStatus = AH_FALSE;
1392         enum hal_status ecode = HAL_OK;
1393
1394         rfStatus = ath9k_hw_init_rf(ah, &ecode);
1395         if (!rfStatus) {
1396                 HDPRINTF(ah, HAL_DBG_RESET,
1397                          "%s: RF setup failed, status %u\n", __func__,
1398                          ecode);
1399                 return ecode;
1400         }
1401
1402         return HAL_OK;
1403 }
1404
1405 static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
1406 {
1407         u_int32_t val;
1408
1409         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1410
1411         val = ath9k_hw_get_radiorev(ah);
1412         switch (val & AR_RADIO_SREV_MAJOR) {
1413         case 0:
1414                 val = AR_RAD5133_SREV_MAJOR;
1415                 break;
1416         case AR_RAD5133_SREV_MAJOR:
1417         case AR_RAD5122_SREV_MAJOR:
1418         case AR_RAD2133_SREV_MAJOR:
1419         case AR_RAD2122_SREV_MAJOR:
1420                 break;
1421         default:
1422                 HDPRINTF(ah, HAL_DBG_CHANNEL,
1423                          "%s: 5G Radio Chip Rev 0x%02X is not "
1424                         "supported by this driver\n",
1425                          __func__, ah->ah_analog5GhzRev);
1426                 return HAL_ENOTSUPP;
1427         }
1428
1429         ah->ah_analog5GhzRev = val;
1430
1431         return HAL_OK;
1432 }
1433
1434 static inline void ath9k_hw_init_pll(struct ath_hal *ah,
1435                                      struct hal_channel *chan)
1436 {
1437         u_int32_t pll;
1438
1439         if (AR_SREV_9100(ah)) {
1440                 if (chan && IS_CHAN_5GHZ(chan))
1441                         pll = 0x1450;
1442                 else
1443                         pll = 0x1458;
1444         } else {
1445                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1446                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1447
1448                         if (chan && IS_CHAN_HALF_RATE(chan))
1449                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1450                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1451                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1452
1453                         if (chan && IS_CHAN_5GHZ(chan)) {
1454                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1455
1456
1457                                 if (AR_SREV_9280_20(ah)) {
1458                                         if (((chan->channel % 20) == 0)
1459                                             || ((chan->channel % 10) == 0))
1460                                                 pll = 0x2850;
1461                                         else
1462                                                 pll = 0x142c;
1463                                 }
1464                         } else {
1465                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1466                         }
1467
1468                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1469
1470                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1471
1472                         if (chan && IS_CHAN_HALF_RATE(chan))
1473                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1474                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1475                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1476
1477                         if (chan && IS_CHAN_5GHZ(chan))
1478                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1479                         else
1480                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1481                 } else {
1482                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1483
1484                         if (chan && IS_CHAN_HALF_RATE(chan))
1485                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1486                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1487                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1488
1489                         if (chan && IS_CHAN_5GHZ(chan))
1490                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1491                         else
1492                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1493                 }
1494         }
1495         REG_WRITE(ah, (u_int16_t) (AR_RTC_PLL_CONTROL), pll);
1496
1497         udelay(RTC_PLL_SETTLE_DELAY);
1498
1499         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1500 }
1501
1502 static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
1503                               enum hal_ht_macmode macmode)
1504 {
1505         u_int32_t phymode;
1506         struct ath_hal_5416 *ahp = AH5416(ah);
1507
1508         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1509                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1510
1511         if (IS_CHAN_HT40(chan)) {
1512                 phymode |= AR_PHY_FC_DYN2040_EN;
1513
1514                 if (chan->channelFlags & CHANNEL_HT40PLUS)
1515                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1516
1517                 if (ahp->ah_extprotspacing == HAL_HT_EXTPROTSPACING_25)
1518                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1519         }
1520         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1521
1522         ath9k_hw_set11nmac2040(ah, macmode);
1523
1524         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1525         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1526 }
1527
1528 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1529 {
1530         u_int32_t val;
1531
1532         val = REG_READ(ah, AR_STA_ID1);
1533         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1534         switch (opmode) {
1535         case HAL_M_HOSTAP:
1536                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1537                           | AR_STA_ID1_KSRCH_MODE);
1538                 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1539                 break;
1540         case HAL_M_IBSS:
1541                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1542                           | AR_STA_ID1_KSRCH_MODE);
1543                 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1544                 break;
1545         case HAL_M_STA:
1546         case HAL_M_MONITOR:
1547                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1548                 break;
1549         }
1550 }
1551
1552 static inline void
1553 ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
1554 {
1555         u_int32_t rfMode = 0;
1556
1557         if (chan == NULL)
1558                 return;
1559
1560         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1561                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1562
1563         if (!AR_SREV_9280_10_OR_LATER(ah))
1564                 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1565                         AR_PHY_MODE_RF2GHZ;
1566
1567         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1568                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1569
1570         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1571 }
1572
1573 static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1574 {
1575         u_int32_t rst_flags;
1576         u_int32_t tmpReg;
1577
1578         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1579                   AR_RTC_FORCE_WAKE_ON_INT);
1580
1581         if (AR_SREV_9100(ah)) {
1582                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1583                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1584         } else {
1585                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1586                 if (tmpReg &
1587                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1588                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1589                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1590                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1591                 } else {
1592                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1593                 }
1594
1595                 rst_flags = AR_RTC_RC_MAC_WARM;
1596                 if (type == HAL_RESET_COLD)
1597                         rst_flags |= AR_RTC_RC_MAC_COLD;
1598         }
1599
1600         REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), rst_flags);
1601         udelay(50);
1602
1603         REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
1604         if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1605                 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC stuck in MAC reset\n",
1606                          __func__);
1607                 return AH_FALSE;
1608         }
1609
1610         if (!AR_SREV_9100(ah))
1611                 REG_WRITE(ah, AR_RC, 0);
1612
1613         ath9k_hw_init_pll(ah, NULL);
1614
1615         if (AR_SREV_9100(ah))
1616                 udelay(50);
1617
1618         return AH_TRUE;
1619 }
1620
1621 static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1622 {
1623         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1624                   AR_RTC_FORCE_WAKE_ON_INT);
1625
1626         REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 0);
1627         REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 1);
1628
1629         if (!ath9k_hw_wait(ah,
1630                            AR_RTC_STATUS,
1631                            AR_RTC_STATUS_M,
1632                            AR_RTC_STATUS_ON)) {
1633                 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC not waking up\n",
1634                          __func__);
1635                 return AH_FALSE;
1636         }
1637
1638         ath9k_hw_read_revisions(ah);
1639
1640         return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
1641 }
1642
1643 static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1644                                             u_int32_t type)
1645 {
1646         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1647                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1648
1649         switch (type) {
1650         case HAL_RESET_POWER_ON:
1651                 return ath9k_hw_set_reset_power_on(ah);
1652                 break;
1653         case HAL_RESET_WARM:
1654         case HAL_RESET_COLD:
1655                 return ath9k_hw_set_reset(ah, type);
1656                 break;
1657         default:
1658                 return AH_FALSE;
1659         }
1660 }
1661
1662 static inline struct hal_channel_internal *ath9k_hw_check_chan(
1663                         struct ath_hal *ah, struct hal_channel *chan)
1664 {
1665         if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
1666                 HDPRINTF(ah, HAL_DBG_CHANNEL,
1667                          "%s: invalid channel %u/0x%x; not marked as "
1668                          "2GHz or 5GHz\n", __func__, chan->channel,
1669                          chan->channelFlags);
1670                 return NULL;
1671         }
1672
1673         if ((IS(chan, CHANNEL_OFDM)
1674              ^ IS(chan, CHANNEL_CCK)
1675              ^ IS(chan, CHANNEL_HT20)
1676              ^ IS(chan, CHANNEL_HT40PLUS)
1677              ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
1678                 HDPRINTF(ah, HAL_DBG_CHANNEL,
1679                          "%s: invalid channel %u/0x%x; not marked as "
1680                          "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1681                          __func__, chan->channel, chan->channelFlags);
1682                 return NULL;
1683         }
1684
1685         return ath9k_regd_check_channel(ah, chan);
1686 }
1687
1688 static inline enum hal_bool
1689 ath9k_hw_get_lower_upper_index(u_int8_t target,
1690                                u_int8_t *pList,
1691                                u_int16_t listSize,
1692                                u_int16_t *indexL,
1693                                u_int16_t *indexR)
1694 {
1695         u_int16_t i;
1696
1697         if (target <= pList[0]) {
1698                 *indexL = *indexR = 0;
1699                 return AH_TRUE;
1700         }
1701         if (target >= pList[listSize - 1]) {
1702                 *indexL = *indexR = (u_int16_t) (listSize - 1);
1703                 return AH_TRUE;
1704         }
1705
1706         for (i = 0; i < listSize - 1; i++) {
1707                 if (pList[i] == target) {
1708                         *indexL = *indexR = i;
1709                         return AH_TRUE;
1710                 }
1711                 if (target < pList[i + 1]) {
1712                         *indexL = i;
1713                         *indexR = (u_int16_t) (i + 1);
1714                         return AH_FALSE;
1715                 }
1716         }
1717         return AH_FALSE;
1718 }
1719
1720 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1721 {
1722         int16_t nfval;
1723         int16_t sort[HAL_NF_CAL_HIST_MAX];
1724         int i, j;
1725
1726         for (i = 0; i < HAL_NF_CAL_HIST_MAX; i++)
1727                 sort[i] = nfCalBuffer[i];
1728
1729         for (i = 0; i < HAL_NF_CAL_HIST_MAX - 1; i++) {
1730                 for (j = 1; j < HAL_NF_CAL_HIST_MAX - i; j++) {
1731                         if (sort[j] > sort[j - 1]) {
1732                                 nfval = sort[j];
1733                                 sort[j] = sort[j - 1];
1734                                 sort[j - 1] = nfval;
1735                         }
1736                 }
1737         }
1738         nfval = sort[(HAL_NF_CAL_HIST_MAX - 1) >> 1];
1739
1740         return nfval;
1741 }
1742
1743 static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
1744                                               int16_t *nfarray)
1745 {
1746         int i;
1747
1748         for (i = 0; i < NUM_NF_READINGS; i++) {
1749                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1750
1751                 if (++h[i].currIndex >= HAL_NF_CAL_HIST_MAX)
1752                         h[i].currIndex = 0;
1753
1754                 if (h[i].invalidNFcount > 0) {
1755                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1756                             || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1757                                 h[i].invalidNFcount = HAL_NF_CAL_HIST_MAX;
1758                         } else {
1759                                 h[i].invalidNFcount--;
1760                                 h[i].privNF = nfarray[i];
1761                         }
1762                 } else {
1763                         h[i].privNF =
1764                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1765                 }
1766         }
1767         return;
1768 }
1769
1770 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1771                                 int16_t nfarray[NUM_NF_READINGS])
1772 {
1773         int16_t nf;
1774
1775         if (AR_SREV_9280_10_OR_LATER(ah))
1776                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1777         else
1778                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1779
1780         if (nf & 0x100)
1781                 nf = 0 - ((nf ^ 0x1ff) + 1);
1782         HDPRINTF(ah, HAL_DBG_CALIBRATE,
1783                  "NF calibrated [ctl] [chain 0] is %d\n", nf);
1784         nfarray[0] = nf;
1785
1786         if (AR_SREV_9280_10_OR_LATER(ah))
1787                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1788                         AR9280_PHY_CH1_MINCCA_PWR);
1789         else
1790                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1791                         AR_PHY_CH1_MINCCA_PWR);
1792
1793         if (nf & 0x100)
1794                 nf = 0 - ((nf ^ 0x1ff) + 1);
1795         HDPRINTF(ah, HAL_DBG_NF_CAL,
1796                  "NF calibrated [ctl] [chain 1] is %d\n", nf);
1797         nfarray[1] = nf;
1798
1799         if (!AR_SREV_9280(ah)) {
1800                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1801                         AR_PHY_CH2_MINCCA_PWR);
1802                 if (nf & 0x100)
1803                         nf = 0 - ((nf ^ 0x1ff) + 1);
1804                 HDPRINTF(ah, HAL_DBG_NF_CAL,
1805                          "NF calibrated [ctl] [chain 2] is %d\n", nf);
1806                 nfarray[2] = nf;
1807         }
1808
1809         if (AR_SREV_9280_10_OR_LATER(ah))
1810                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1811                         AR9280_PHY_EXT_MINCCA_PWR);
1812         else
1813                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1814                         AR_PHY_EXT_MINCCA_PWR);
1815
1816         if (nf & 0x100)
1817                 nf = 0 - ((nf ^ 0x1ff) + 1);
1818         HDPRINTF(ah, HAL_DBG_NF_CAL,
1819                  "NF calibrated [ext] [chain 0] is %d\n", nf);
1820         nfarray[3] = nf;
1821
1822         if (AR_SREV_9280_10_OR_LATER(ah))
1823                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1824                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
1825         else
1826                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1827                         AR_PHY_CH1_EXT_MINCCA_PWR);
1828
1829         if (nf & 0x100)
1830                 nf = 0 - ((nf ^ 0x1ff) + 1);
1831         HDPRINTF(ah, HAL_DBG_CALIBRATE,
1832                  "NF calibrated [ext] [chain 1] is %d\n", nf);
1833         nfarray[4] = nf;
1834
1835         if (!AR_SREV_9280(ah)) {
1836                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1837                         AR_PHY_CH2_EXT_MINCCA_PWR);
1838                 if (nf & 0x100)
1839                         nf = 0 - ((nf ^ 0x1ff) + 1);
1840                 HDPRINTF(ah, HAL_DBG_NF_CAL,
1841                          "NF calibrated [ext] [chain 2] is %d\n", nf);
1842                 nfarray[5] = nf;
1843         }
1844 }
1845
1846 static enum hal_bool
1847 getNoiseFloorThresh(struct ath_hal *ah,
1848                     const struct hal_channel_internal *chan,
1849                     int16_t *nft)
1850 {
1851         struct ath_hal_5416 *ahp = AH5416(ah);
1852
1853         switch (chan->channelFlags & CHANNEL_ALL) {
1854         case CHANNEL_A:
1855         case CHANNEL_A_HT20:
1856         case CHANNEL_A_HT40PLUS:
1857         case CHANNEL_A_HT40MINUS:
1858                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1859                 break;
1860         case CHANNEL_B:
1861         case CHANNEL_G:
1862         case CHANNEL_G_HT20:
1863         case CHANNEL_G_HT40PLUS:
1864         case CHANNEL_G_HT40MINUS:
1865                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1866                 break;
1867         default:
1868                 HDPRINTF(ah, HAL_DBG_CHANNEL,
1869                          "%s: invalid channel flags 0x%x\n", __func__,
1870                          chan->channelFlags);
1871                 return AH_FALSE;
1872         }
1873         return AH_TRUE;
1874 }
1875
1876 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1877 {
1878         OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1879                        AR_PHY_AGC_CONTROL_ENABLE_NF);
1880         OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1881                        AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1882         OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1883 }
1884
1885 static void
1886 ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
1887 {
1888         struct hal_nfcal_hist *h;
1889         int i, j;
1890         int32_t val;
1891         const u_int32_t ar5416_cca_regs[6] = {
1892                 AR_PHY_CCA,
1893                 AR_PHY_CH1_CCA,
1894                 AR_PHY_CH2_CCA,
1895                 AR_PHY_EXT_CCA,
1896                 AR_PHY_CH1_EXT_CCA,
1897                 AR_PHY_CH2_EXT_CCA
1898         };
1899         u_int8_t chainmask;
1900
1901         if (AR_SREV_9280(ah))
1902                 chainmask = 0x1B;
1903         else
1904                 chainmask = 0x3F;
1905
1906 #ifdef ATH_NF_PER_CHAN
1907         h = chan->nfCalHist;
1908 #else
1909         h = ah->nfCalHist;
1910 #endif
1911
1912         for (i = 0; i < NUM_NF_READINGS; i++) {
1913                 if (chainmask & (1 << i)) {
1914                         val = REG_READ(ah, ar5416_cca_regs[i]);
1915                         val &= 0xFFFFFE00;
1916                         val |= (((u_int32_t) (h[i].privNF) << 1) & 0x1ff);
1917                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1918                 }
1919         }
1920
1921         OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1922                        AR_PHY_AGC_CONTROL_ENABLE_NF);
1923         OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1924                        AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1925         OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1926
1927         for (j = 0; j < 1000; j++) {
1928                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1929                      AR_PHY_AGC_CONTROL_NF) == 0)
1930                         break;
1931                 udelay(10);
1932         }
1933
1934         for (i = 0; i < NUM_NF_READINGS; i++) {
1935                 if (chainmask & (1 << i)) {
1936                         val = REG_READ(ah, ar5416_cca_regs[i]);
1937                         val &= 0xFFFFFE00;
1938                         val |= (((u_int32_t) (-50) << 1) & 0x1ff);
1939                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1940                 }
1941         }
1942 }
1943
1944 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1945                               struct hal_channel_internal *chan)
1946 {
1947         int16_t nf, nfThresh;
1948         int16_t nfarray[NUM_NF_READINGS] = { 0 };
1949         struct hal_nfcal_hist *h;
1950         u_int8_t chainmask;
1951
1952         if (AR_SREV_9280(ah))
1953                 chainmask = 0x1B;
1954         else
1955                 chainmask = 0x3F;
1956
1957         chan->channelFlags &= (~CHANNEL_CW_INT);
1958         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1959                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1960                          "%s: NF did not complete in calibration window\n",
1961                          __func__);
1962                 nf = 0;
1963                 chan->rawNoiseFloor = nf;
1964                 return chan->rawNoiseFloor;
1965         } else {
1966                 ar5416GetNoiseFloor(ah, nfarray);
1967                 nf = nfarray[0];
1968                 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1969                     && nf > nfThresh) {
1970                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
1971                                  "%s: noise floor failed detected; "
1972                                  "detected %d, threshold %d\n", __func__,
1973                                  nf, nfThresh);
1974                         chan->channelFlags |= CHANNEL_CW_INT;
1975                 }
1976         }
1977
1978 #ifdef ATH_NF_PER_CHAN
1979         h = chan->nfCalHist;
1980 #else
1981         h = ah->nfCalHist;
1982 #endif
1983
1984         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1985         chan->rawNoiseFloor = h[0].privNF;
1986
1987         return chan->rawNoiseFloor;
1988 }
1989
1990 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1991                               struct hal_mib_stats *stats)
1992 {
1993         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1994         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1995         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1996         stats->rts_good += REG_READ(ah, AR_RTS_OK);
1997         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1998 }
1999
2000 static void ath9k_enable_mib_counters(struct ath_hal *ah)
2001 {
2002         struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004         HDPRINTF(ah, HAL_DBG_ANI, "Enable mib counters\n");
2005
2006         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2007
2008         REG_WRITE(ah, AR_FILT_OFDM, 0);
2009         REG_WRITE(ah, AR_FILT_CCK, 0);
2010         REG_WRITE(ah, AR_MIBC,
2011                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
2012                   & 0x0f);
2013         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2014         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2015 }
2016
2017 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2018 {
2019         struct ath_hal_5416 *ahp = AH5416(ah);
2020
2021         HDPRINTF(ah, HAL_DBG_ANI, "Disabling MIB counters\n");
2022
2023         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2024
2025         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2026
2027         REG_WRITE(ah, AR_FILT_OFDM, 0);
2028         REG_WRITE(ah, AR_FILT_CCK, 0);
2029 }
2030
2031 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2032                                         struct hal_channel_internal *chan)
2033 {
2034         struct ath_hal_5416 *ahp = AH5416(ah);
2035         int i;
2036
2037         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2038                 if (ahp->ah_ani[i].c.channel == chan->channel)
2039                         return i;
2040                 if (ahp->ah_ani[i].c.channel == 0) {
2041                         ahp->ah_ani[i].c.channel = chan->channel;
2042                         ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2043                         return i;
2044                 }
2045         }
2046
2047         HDPRINTF(ah, HAL_DBG_ANI,
2048                  "No more channel states left. Using channel 0\n");
2049         return 0;
2050 }
2051
2052 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2053 {
2054         struct ath_hal_5416 *ahp = AH5416(ah);
2055         int i;
2056
2057         ahp->ah_hasHwPhyCounters = 1;
2058
2059         memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2060         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2061                 ahp->ah_ani[i].ofdmTrigHigh = HAL_ANI_OFDM_TRIG_HIGH;
2062                 ahp->ah_ani[i].ofdmTrigLow = HAL_ANI_OFDM_TRIG_LOW;
2063                 ahp->ah_ani[i].cckTrigHigh = HAL_ANI_CCK_TRIG_HIGH;
2064                 ahp->ah_ani[i].cckTrigLow = HAL_ANI_CCK_TRIG_LOW;
2065                 ahp->ah_ani[i].rssiThrHigh = HAL_ANI_RSSI_THR_HIGH;
2066                 ahp->ah_ani[i].rssiThrLow = HAL_ANI_RSSI_THR_LOW;
2067                 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2068                         !HAL_ANI_USE_OFDM_WEAK_SIG;
2069                 ahp->ah_ani[i].cckWeakSigThreshold =
2070                         HAL_ANI_CCK_WEAK_SIG_THR;
2071                 ahp->ah_ani[i].spurImmunityLevel = HAL_ANI_SPUR_IMMUNE_LVL;
2072                 ahp->ah_ani[i].firstepLevel = HAL_ANI_FIRSTEP_LVL;
2073                 if (ahp->ah_hasHwPhyCounters) {
2074                         ahp->ah_ani[i].ofdmPhyErrBase =
2075                                 AR_PHY_COUNTMAX - HAL_ANI_OFDM_TRIG_HIGH;
2076                         ahp->ah_ani[i].cckPhyErrBase =
2077                                 AR_PHY_COUNTMAX - HAL_ANI_CCK_TRIG_HIGH;
2078                 }
2079         }
2080         if (ahp->ah_hasHwPhyCounters) {
2081                 HDPRINTF(ah, HAL_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n",
2082                          ahp->ah_ani[0].ofdmPhyErrBase);
2083                 HDPRINTF(ah, HAL_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2084                          ahp->ah_ani[0].cckPhyErrBase);
2085
2086                 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2087                 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2088                 ath9k_enable_mib_counters(ah);
2089         }
2090         ahp->ah_aniPeriod = HAL_ANI_PERIOD;
2091         if (ah->ah_config.ath_hal_enableANI)
2092                 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2093 }
2094
2095 static inline void ath9k_hw_ani_setup(struct ath_hal *ah)
2096 {
2097         struct ath_hal_5416 *ahp = AH5416(ah);
2098         int i;
2099
2100         const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2101         const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2102         const int coarseLow[] = { -64, -64, -64, -64, -70 };
2103         const int firpwr[] = { -78, -78, -78, -78, -80 };
2104
2105         for (i = 0; i < 5; i++) {
2106                 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2107                 ahp->ah_coarseHigh[i] = coarseHigh[i];
2108                 ahp->ah_coarseLow[i] = coarseLow[i];
2109                 ahp->ah_firpwr[i] = firpwr[i];
2110         }
2111 }
2112
2113 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2114 {
2115         struct ath_hal_5416 *ahp = AH5416(ah);
2116
2117         HDPRINTF(ah, HAL_DBG_ANI, "Detaching Ani\n");
2118         if (ahp->ah_hasHwPhyCounters) {
2119                 ath9k_hw_disable_mib_counters(ah);
2120                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2121                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2122         }
2123 }
2124
2125
2126 static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
2127                                           enum hal_ani_cmd cmd, int param)
2128 {
2129         struct ath_hal_5416 *ahp = AH5416(ah);
2130         struct ar5416AniState *aniState = ahp->ah_curani;
2131
2132         switch (cmd & ahp->ah_ani_function) {
2133         case HAL_ANI_NOISE_IMMUNITY_LEVEL:{
2134                 u_int level = param;
2135
2136                 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2137                         HDPRINTF(ah, HAL_DBG_ANI,
2138                                  "%s: level out of range (%u > %u)\n",
2139                                  __func__, level,
2140                                  (unsigned) ARRAY_SIZE(ahp->
2141                                                        ah_totalSizeDesired));
2142                         return AH_FALSE;
2143                 }
2144
2145                 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2146                                  AR_PHY_DESIRED_SZ_TOT_DES,
2147                                  ahp->ah_totalSizeDesired[level]);
2148                 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2149                                  AR_PHY_AGC_CTL1_COARSE_LOW,
2150                                  ahp->ah_coarseLow[level]);
2151                 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2152                                  AR_PHY_AGC_CTL1_COARSE_HIGH,
2153                                  ahp->ah_coarseHigh[level]);
2154                 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2155                                  AR_PHY_FIND_SIG_FIRPWR,
2156                                  ahp->ah_firpwr[level]);
2157
2158                 if (level > aniState->noiseImmunityLevel)
2159                         ahp->ah_stats.ast_ani_niup++;
2160                 else if (level < aniState->noiseImmunityLevel)
2161                         ahp->ah_stats.ast_ani_nidown++;
2162                 aniState->noiseImmunityLevel = level;
2163                 break;
2164         }
2165         case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2166                 const int m1ThreshLow[] = { 127, 50 };
2167                 const int m2ThreshLow[] = { 127, 40 };
2168                 const int m1Thresh[] = { 127, 0x4d };
2169                 const int m2Thresh[] = { 127, 0x40 };
2170                 const int m2CountThr[] = { 31, 16 };
2171                 const int m2CountThrLow[] = { 63, 48 };
2172                 u_int on = param ? 1 : 0;
2173
2174                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2175                                  AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2176                                  m1ThreshLow[on]);
2177                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2178                                  AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2179                                  m2ThreshLow[on]);
2180                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2181                                  AR_PHY_SFCORR_M1_THRESH,
2182                                  m1Thresh[on]);
2183                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2184                                  AR_PHY_SFCORR_M2_THRESH,
2185                                  m2Thresh[on]);
2186                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2187                                  AR_PHY_SFCORR_M2COUNT_THR,
2188                                  m2CountThr[on]);
2189                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2190                                  AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2191                                  m2CountThrLow[on]);
2192
2193                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2194                                  AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2195                                  m1ThreshLow[on]);
2196                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2197                                  AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2198                                  m2ThreshLow[on]);
2199                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2200                                  AR_PHY_SFCORR_EXT_M1_THRESH,
2201                                  m1Thresh[on]);
2202                 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2203                                  AR_PHY_SFCORR_EXT_M2_THRESH,
2204                                  m2Thresh[on]);
2205
2206                 if (on)
2207                         OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2208                                        AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2209                 else
2210                         OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2211                                        AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2212
2213                 if (!on != aniState->ofdmWeakSigDetectOff) {
2214                         if (on)
2215                                 ahp->ah_stats.ast_ani_ofdmon++;
2216                         else
2217                                 ahp->ah_stats.ast_ani_ofdmoff++;
2218                         aniState->ofdmWeakSigDetectOff = !on;
2219                 }
2220                 break;
2221         }
2222         case HAL_ANI_CCK_WEAK_SIGNAL_THR:{
2223                 const int weakSigThrCck[] = { 8, 6 };
2224                 u_int high = param ? 1 : 0;
2225
2226                 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2227                                  AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2228                                  weakSigThrCck[high]);
2229                 if (high != aniState->cckWeakSigThreshold) {
2230                         if (high)
2231                                 ahp->ah_stats.ast_ani_cckhigh++;
2232                         else
2233                                 ahp->ah_stats.ast_ani_ccklow++;
2234                         aniState->cckWeakSigThreshold = high;
2235                 }
2236                 break;
2237         }
2238         case HAL_ANI_FIRSTEP_LEVEL:{
2239                 const int firstep[] = { 0, 4, 8 };
2240                 u_int level = param;
2241
2242                 if (level >= ARRAY_SIZE(firstep)) {
2243                         HDPRINTF(ah, HAL_DBG_ANI,
2244                                  "%s: level out of range (%u > %u)\n",
2245                                  __func__, level,
2246                                  (unsigned) ARRAY_SIZE(firstep));
2247                         return AH_FALSE;
2248                 }
2249                 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2250                                  AR_PHY_FIND_SIG_FIRSTEP,
2251                                  firstep[level]);
2252                 if (level > aniState->firstepLevel)
2253                         ahp->ah_stats.ast_ani_stepup++;
2254                 else if (level < aniState->firstepLevel)
2255                         ahp->ah_stats.ast_ani_stepdown++;
2256                 aniState->firstepLevel = level;
2257                 break;
2258         }
2259         case HAL_ANI_SPUR_IMMUNITY_LEVEL:{
2260                 const int cycpwrThr1[] =
2261                         { 2, 4, 6, 8, 10, 12, 14, 16 };
2262                 u_int level = param;
2263
2264                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2265                         HDPRINTF(ah, HAL_DBG_ANI,
2266                                  "%s: level out of range (%u > %u)\n",
2267                                  __func__, level,
2268                                  (unsigned)
2269                                  ARRAY_SIZE(cycpwrThr1));
2270                         return AH_FALSE;
2271                 }
2272                 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2273                                  AR_PHY_TIMING5_CYCPWR_THR1,
2274                                  cycpwrThr1[level]);
2275                 if (level > aniState->spurImmunityLevel)
2276                         ahp->ah_stats.ast_ani_spurup++;
2277                 else if (level < aniState->spurImmunityLevel)
2278                         ahp->ah_stats.ast_ani_spurdown++;
2279                 aniState->spurImmunityLevel = level;
2280                 break;
2281         }
2282         case HAL_ANI_PRESENT:
2283                 break;
2284         default:
2285                 HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__,
2286                          cmd);
2287                 return AH_FALSE;
2288         }
2289
2290         HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__);
2291         HDPRINTF(ah, HAL_DBG_ANI,
2292                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2293                 "ofdmWeakSigDetectOff=%d\n",
2294                  aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2295                  !aniState->ofdmWeakSigDetectOff);
2296         HDPRINTF(ah, HAL_DBG_ANI,
2297                 "cckWeakSigThreshold=%d, "
2298                 "firstepLevel=%d, listenTime=%d\n",
2299                  aniState->cckWeakSigThreshold, aniState->firstepLevel,
2300                  aniState->listenTime);
2301         HDPRINTF(ah, HAL_DBG_ANI,
2302                  "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2303                  aniState->cycleCount, aniState->ofdmPhyErrCount,
2304                  aniState->cckPhyErrCount);
2305         return AH_TRUE;
2306 }
2307
2308 static void ath9k_ani_restart(struct ath_hal *ah)
2309 {
2310         struct ath_hal_5416 *ahp = AH5416(ah);
2311         struct ar5416AniState *aniState;
2312
2313         if (!DO_ANI(ah))
2314                 return;
2315
2316         aniState = ahp->ah_curani;
2317
2318         aniState->listenTime = 0;
2319         if (ahp->ah_hasHwPhyCounters) {
2320                 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2321                         aniState->ofdmPhyErrBase = 0;
2322                         HDPRINTF(ah, HAL_DBG_ANI,
2323                                  "OFDM Trigger is too high for hw counters\n");
2324                 } else {
2325                         aniState->ofdmPhyErrBase =
2326                                 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2327                 }
2328                 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2329                         aniState->cckPhyErrBase = 0;
2330                         HDPRINTF(ah, HAL_DBG_ANI,
2331                                  "CCK Trigger is too high for hw counters\n");
2332                 } else {
2333                         aniState->cckPhyErrBase =
2334                                 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2335                 }
2336                 HDPRINTF(ah, HAL_DBG_ANI,
2337                          "%s: Writing ofdmbase=%u   cckbase=%u\n",
2338                          __func__, aniState->ofdmPhyErrBase,
2339                          aniState->cckPhyErrBase);
2340                 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2341                 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2342                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2343                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2344
2345                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2346         }
2347         aniState->ofdmPhyErrCount = 0;
2348         aniState->cckPhyErrCount = 0;
2349 }
2350
2351 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2352 {
2353         struct ath_hal_5416 *ahp = AH5416(ah);
2354         struct hal_channel_internal *chan = ah->ah_curchan;
2355         struct ar5416AniState *aniState;
2356         enum wireless_mode mode;
2357         int32_t rssi;
2358
2359         if (!DO_ANI(ah))
2360                 return;
2361
2362         aniState = ahp->ah_curani;
2363
2364         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2365                 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2366                                          aniState->noiseImmunityLevel +
2367                                          1) == AH_TRUE) {
2368                         return;
2369                 }
2370         }
2371
2372         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2373                 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2374                                          aniState->spurImmunityLevel +
2375                                          1) == AH_TRUE) {
2376                         return;
2377                 }
2378         }
2379
2380         if (ah->ah_opmode == HAL_M_HOSTAP) {
2381                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382                         ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2383                                              aniState->firstepLevel + 1);
2384                 }
2385                 return;
2386         }
2387         rssi = BEACON_RSSI(ahp);
2388         if (rssi > aniState->rssiThrHigh) {
2389                 if (!aniState->ofdmWeakSigDetectOff) {
2390                         if (ath9k_hw_ani_control(ah,
2391                                          HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2392                                          AH_FALSE) == AH_TRUE) {
2393                                 ath9k_hw_ani_control(ah,
2394                                         HAL_ANI_SPUR_IMMUNITY_LEVEL,
2395                                         0);
2396                                 return;
2397                         }
2398                 }
2399                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2400                         ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2401                                              aniState->firstepLevel + 1);
2402                         return;
2403                 }
2404         } else if (rssi > aniState->rssiThrLow) {
2405                 if (aniState->ofdmWeakSigDetectOff)
2406                         ath9k_hw_ani_control(ah,
2407                                              HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2408                                              AH_TRUE);
2409                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2410                         ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2411                                              aniState->firstepLevel + 1);
2412                 return;
2413         } else {
2414                 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2415                 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2416                         if (!aniState->ofdmWeakSigDetectOff)
2417                                 ath9k_hw_ani_control(ah,
2418                                              HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2419                                              AH_FALSE);
2420                         if (aniState->firstepLevel > 0)
2421                                 ath9k_hw_ani_control(ah,
2422                                                      HAL_ANI_FIRSTEP_LEVEL,
2423                                                      0);
2424                         return;
2425                 }
2426         }
2427 }
2428
2429 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2430 {
2431         struct ath_hal_5416 *ahp = AH5416(ah);
2432         struct hal_channel_internal *chan = ah->ah_curchan;
2433         struct ar5416AniState *aniState;
2434         enum wireless_mode mode;
2435         int32_t rssi;
2436
2437         if (!DO_ANI(ah))
2438                 return;
2439
2440         aniState = ahp->ah_curani;
2441         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2442                 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2443                                          aniState->noiseImmunityLevel +
2444                                          1) == AH_TRUE) {
2445                         return;
2446                 }
2447         }
2448         if (ah->ah_opmode == HAL_M_HOSTAP) {
2449                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2450                         ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2451                                              aniState->firstepLevel + 1);
2452                 }
2453                 return;
2454         }
2455         rssi = BEACON_RSSI(ahp);
2456         if (rssi > aniState->rssiThrLow) {
2457                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2458                         ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2459                                              aniState->firstepLevel + 1);
2460         } else {
2461                 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2462                 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2463                         if (aniState->firstepLevel > 0)
2464                                 ath9k_hw_ani_control(ah,
2465                                                      HAL_ANI_FIRSTEP_LEVEL,
2466                                                      0);
2467                 }
2468         }
2469 }
2470
2471 static void ath9k_ani_reset(struct ath_hal *ah)
2472 {
2473         struct ath_hal_5416 *ahp = AH5416(ah);
2474         struct ar5416AniState *aniState;
2475         struct hal_channel_internal *chan = ah->ah_curchan;
2476         int index;
2477
2478         if (!DO_ANI(ah))
2479                 return;
2480
2481         index = ath9k_hw_get_ani_channel_idx(ah, chan);
2482         aniState = &ahp->ah_ani[index];
2483         ahp->ah_curani = aniState;
2484
2485         if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
2486             && ah->ah_opmode != HAL_M_IBSS) {
2487                 HDPRINTF(ah, HAL_DBG_ANI,
2488                          "%s: Reset ANI state opmode %u\n", __func__,
2489                          ah->ah_opmode);
2490                 ahp->ah_stats.ast_ani_reset++;
2491                 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
2492                 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
2493                 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
2494                 ath9k_hw_ani_control(ah,
2495                                      HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2496                                      !HAL_ANI_USE_OFDM_WEAK_SIG);
2497                 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2498                                      HAL_ANI_CCK_WEAK_SIG_THR);
2499                 ath9k_hw_setrxfilter(ah,
2500                                      ath9k_hw_getrxfilter(ah) |
2501                                      HAL_RX_FILTER_PHYERR);
2502                 if (ah->ah_opmode == HAL_M_HOSTAP) {
2503                         ahp->ah_curani->ofdmTrigHigh =
2504                                 ah->ah_config.ath_hal_ofdmTrigHigh;
2505                         ahp->ah_curani->ofdmTrigLow =
2506                                 ah->ah_config.ath_hal_ofdmTrigLow;
2507                         ahp->ah_curani->cckTrigHigh =
2508                                 ah->ah_config.ath_hal_cckTrigHigh;
2509                         ahp->ah_curani->cckTrigLow =
2510                                 ah->ah_config.ath_hal_cckTrigLow;
2511                 }
2512                 ath9k_ani_restart(ah);
2513                 return;
2514         }
2515
2516         if (aniState->noiseImmunityLevel != 0)
2517                 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2518                                      aniState->noiseImmunityLevel);
2519         if (aniState->spurImmunityLevel != 0)
2520                 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2521                                      aniState->spurImmunityLevel);
2522         if (aniState->ofdmWeakSigDetectOff)
2523                 ath9k_hw_ani_control(ah,
2524                                      HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2525                                      !aniState->ofdmWeakSigDetectOff);
2526         if (aniState->cckWeakSigThreshold)
2527                 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2528                                      aniState->cckWeakSigThreshold);
2529         if (aniState->firstepLevel != 0)
2530                 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2531                                      aniState->firstepLevel);
2532         if (ahp->ah_hasHwPhyCounters) {
2533                 ath9k_hw_setrxfilter(ah,
2534                                      ath9k_hw_getrxfilter(ah) &
2535                                      ~HAL_RX_FILTER_PHYERR);
2536                 ath9k_ani_restart(ah);
2537                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2538                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2539
2540         } else {
2541                 ath9k_ani_restart(ah);
2542                 ath9k_hw_setrxfilter(ah,
2543                                      ath9k_hw_getrxfilter(ah) |
2544                                      HAL_RX_FILTER_PHYERR);
2545         }
2546 }
2547
2548 void ath9k_hw_procmibevent(struct ath_hal *ah,
2549                            const struct hal_node_stats *stats)
2550 {
2551         struct ath_hal_5416 *ahp = AH5416(ah);
2552         u_int32_t phyCnt1, phyCnt2;
2553
2554         HDPRINTF(ah, HAL_DBG_ANI, "Processing Mib Intr\n");
2555
2556         REG_WRITE(ah, AR_FILT_OFDM, 0);
2557         REG_WRITE(ah, AR_FILT_CCK, 0);
2558         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2559                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2560
2561         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2562         ahp->ah_stats.ast_nodestats = *stats;
2563
2564         if (!DO_ANI(ah))
2565                 return;
2566
2567         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2568         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2569         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2570             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2571                 struct ar5416AniState *aniState = ahp->ah_curani;
2572                 u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
2573
2574                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2575                 ahp->ah_stats.ast_ani_ofdmerrs +=
2576                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2577                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2578
2579                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2580                 ahp->ah_stats.ast_ani_cckerrs +=
2581                         cckPhyErrCnt - aniState->cckPhyErrCount;
2582                 aniState->cckPhyErrCount = cckPhyErrCnt;
2583
2584                 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2585                         ath9k_hw_ani_ofdm_err_trigger(ah);
2586                 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2587                         ath9k_hw_ani_cck_err_trigger(ah);
2588
2589                 ath9k_ani_restart(ah);
2590         }
2591 }
2592
2593 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2594 {
2595         struct ath_hal_5416 *ahp = AH5416(ah);
2596         struct ar5416AniState *aniState;
2597         int32_t rssi;
2598
2599         aniState = ahp->ah_curani;
2600
2601         if (ah->ah_opmode == HAL_M_HOSTAP) {
2602                 if (aniState->firstepLevel > 0) {
2603                         if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2604                                                  aniState->firstepLevel -
2605                                                  1) == AH_TRUE) {
2606                                 return;
2607                         }
2608                 }
2609         } else {
2610                 rssi = BEACON_RSSI(ahp);
2611                 if (rssi > aniState->rssiThrHigh) {
2612
2613                 } else if (rssi > aniState->rssiThrLow) {
2614                         if (aniState->ofdmWeakSigDetectOff) {
2615                                 if (ath9k_hw_ani_control(ah,
2616                                          HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2617                                          AH_TRUE) ==
2618                                     AH_TRUE) {
2619                                         return;
2620                                 }
2621                         }
2622                         if (aniState->firstepLevel > 0) {
2623                                 if (ath9k_hw_ani_control
2624                                     (ah, HAL_ANI_FIRSTEP_LEVEL,
2625                                      aniState->firstepLevel - 1) ==
2626                                     AH_TRUE) {
2627                                         return;
2628                                 }
2629                         }
2630                 } else {
2631                         if (aniState->firstepLevel > 0) {
2632                                 if (ath9k_hw_ani_control
2633                                     (ah, HAL_ANI_FIRSTEP_LEVEL,
2634                                      aniState->firstepLevel - 1) ==
2635                                     AH_TRUE) {
2636                                         return;
2637                                 }
2638                         }
2639                 }
2640         }
2641
2642         if (aniState->spurImmunityLevel > 0) {
2643                 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2644                                          aniState->spurImmunityLevel -
2645                                          1) == AH_TRUE) {
2646                         return;
2647                 }
2648         }
2649
2650         if (aniState->noiseImmunityLevel > 0) {
2651                 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2652                                      aniState->noiseImmunityLevel - 1);
2653                 return;
2654         }
2655 }
2656
2657 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2658 {
2659         struct ath_hal_5416 *ahp = AH5416(ah);
2660         struct ar5416AniState *aniState;
2661         u_int32_t txFrameCount, rxFrameCount, cycleCount;
2662         int32_t listenTime;
2663
2664         txFrameCount = REG_READ(ah, AR_TFCNT);
2665         rxFrameCount = REG_READ(ah, AR_RFCNT);
2666         cycleCount = REG_READ(ah, AR_CCCNT);
2667
2668         aniState = ahp->ah_curani;
2669         if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2670
2671                 listenTime = 0;
2672                 ahp->ah_stats.ast_ani_lzero++;
2673         } else {
2674                 int32_t ccdelta = cycleCount - aniState->cycleCount;
2675                 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2676                 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2677                 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2678         }
2679         aniState->cycleCount = cycleCount;
2680         aniState->txFrameCount = txFrameCount;
2681         aniState->rxFrameCount = rxFrameCount;
2682
2683         return listenTime;
2684 }
2685
2686 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2687                           const struct hal_node_stats *stats,
2688                           struct hal_channel *chan)
2689 {
2690         struct ath_hal_5416 *ahp = AH5416(ah);
2691         struct ar5416AniState *aniState;
2692         int32_t listenTime;
2693
2694         aniState = ahp->ah_curani;
2695         ahp->ah_stats.ast_nodestats = *stats;
2696
2697         listenTime = ath9k_hw_ani_get_listen_time(ah);
2698         if (listenTime < 0) {
2699                 ahp->ah_stats.ast_ani_lneg++;
2700                 ath9k_ani_restart(ah);
2701                 return;
2702         }
2703
2704         aniState->listenTime += listenTime;
2705
2706         if (ahp->ah_hasHwPhyCounters) {
2707                 u_int32_t phyCnt1, phyCnt2;
2708                 u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
2709
2710                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2711
2712                 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2713                 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2714
2715                 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2716                     phyCnt2 < aniState->cckPhyErrBase) {
2717                         if (phyCnt1 < aniState->ofdmPhyErrBase) {
2718                                 HDPRINTF(ah, HAL_DBG_ANI,
2719                                          "%s: phyCnt1 0x%x, resetting "
2720                                          "counter value to 0x%x\n",
2721                                          __func__, phyCnt1,
2722                                          aniState->ofdmPhyErrBase);
2723                                 REG_WRITE(ah, AR_PHY_ERR_1,
2724                                           aniState->ofdmPhyErrBase);
2725                                 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2726                                           AR_PHY_ERR_OFDM_TIMING);
2727                         }
2728                         if (phyCnt2 < aniState->cckPhyErrBase) {
2729                                 HDPRINTF(ah, HAL_DBG_ANI,
2730                                          "%s: phyCnt2 0x%x, resetting "
2731                                          "counter value to 0x%x\n",
2732                                          __func__, phyCnt2,
2733                                          aniState->cckPhyErrBase);
2734                                 REG_WRITE(ah, AR_PHY_ERR_2,
2735                                           aniState->cckPhyErrBase);
2736                                 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2737                                           AR_PHY_ERR_CCK_TIMING);
2738                         }
2739                         return;
2740                 }
2741
2742                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2743                 ahp->ah_stats.ast_ani_ofdmerrs +=
2744                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2745                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2746
2747                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2748                 ahp->ah_stats.ast_ani_cckerrs +=
2749                         cckPhyErrCnt - aniState->cckPhyErrCount;
2750                 aniState->cckPhyErrCount = cckPhyErrCnt;
2751         }
2752
2753         if (!DO_ANI(ah))
2754                 return;
2755
2756         if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2757                 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2758                     aniState->ofdmTrigLow / 1000 &&
2759                     aniState->cckPhyErrCount <= aniState->listenTime *
2760                     aniState->cckTrigLow / 1000)
2761                         ath9k_hw_ani_lower_immunity(ah);
2762                 ath9k_ani_restart(ah);
2763         } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2764                 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2765                     aniState->ofdmTrigHigh / 1000) {
2766                         ath9k_hw_ani_ofdm_err_trigger(ah);
2767                         ath9k_ani_restart(ah);
2768                 } else if (aniState->cckPhyErrCount >
2769                            aniState->listenTime * aniState->cckTrigHigh /
2770                            1000) {
2771                         ath9k_hw_ani_cck_err_trigger(ah);
2772                         ath9k_ani_restart(ah);
2773                 }
2774         }
2775 }
2776
2777 #ifndef ATH_NF_PER_CHAN
2778 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2779 {
2780         int i, j;
2781
2782         for (i = 0; i < NUM_NF_READINGS; i++) {
2783                 ah->nfCalHist[i].currIndex = 0;
2784                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2785                 ah->nfCalHist[i].invalidNFcount =
2786                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
2787                 for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
2788                         ah->nfCalHist[i].nfCalBuffer[j] =
2789                                 AR_PHY_CCA_MAX_GOOD_VALUE;
2790                 }
2791         }
2792         return;
2793 }
2794 #endif
2795
2796 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2797                                          u_int32_t gpio, u_int32_t type)
2798 {
2799         int addr;
2800         u_int32_t gpio_shift, tmp;
2801
2802         if (gpio > 11)
2803                 addr = AR_GPIO_OUTPUT_MUX3;
2804         else if (gpio > 5)
2805                 addr = AR_GPIO_OUTPUT_MUX2;
2806         else
2807                 addr = AR_GPIO_OUTPUT_MUX1;
2808
2809         gpio_shift = (gpio % 6) * 5;
2810
2811         if (AR_SREV_9280_20_OR_LATER(ah)
2812             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2813                 OS_REG_RMW(ah, addr, (type << gpio_shift),
2814                            (0x1f << gpio_shift));
2815         } else {
2816                 tmp = REG_READ(ah, addr);
2817                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2818                 tmp &= ~(0x1f << gpio_shift);
2819                 tmp |= (type << gpio_shift);
2820                 REG_WRITE(ah, addr, tmp);
2821         }
2822 }
2823
2824 static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
2825                                   enum hal_gpio_output_mux_type
2826                                   halSignalType)
2827 {
2828         u_int32_t ah_signal_type;
2829         u_int32_t gpio_shift;
2830
2831         static u_int32_t MuxSignalConversionTable[] = {
2832
2833                 AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
2834
2835                 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
2836
2837                 AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
2838
2839                 AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
2840
2841                 AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
2842         };
2843
2844         if ((halSignalType >= 0)
2845             && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))
2846                 ah_signal_type = MuxSignalConversionTable[halSignalType];
2847         else
2848                 return AH_FALSE;
2849
2850         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2851
2852         gpio_shift = 2 * gpio;
2853
2854         OS_REG_RMW(ah,
2855                    AR_GPIO_OE_OUT,
2856                    (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2857                    (AR_GPIO_OE_OUT_DRV << gpio_shift));
2858
2859         return AH_TRUE;
2860 }
2861
2862 static enum hal_bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
2863                                 u_int32_t val)
2864 {
2865         OS_REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2866                    AR_GPIO_BIT(gpio));
2867         return AH_TRUE;
2868 }
2869
2870 static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
2871 {
2872         if (gpio >= ah->ah_caps.halNumGpioPins)
2873                 return 0xffffffff;
2874
2875         if (AR_SREV_9280_10_OR_LATER(ah)) {
2876                 return (MS
2877                         (REG_READ(ah, AR_GPIO_IN_OUT),
2878                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2879         } else {
2880                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2881                         AR_GPIO_BIT(gpio)) != 0;
2882         }
2883 }
2884
2885 static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
2886 {
2887         enum hal_status ecode;
2888
2889         if (!ath9k_hw_chip_test(ah)) {
2890                 HDPRINTF(ah, HAL_DBG_REG_IO,
2891                          "%s: hardware self-test failed\n", __func__);
2892                 return HAL_ESELFTEST;
2893         }
2894
2895         ecode = ath9k_hw_rf_claim(ah);
2896         if (ecode != HAL_OK)
2897                 return ecode;
2898
2899         ecode = ath9k_hw_eeprom_attach(ah);
2900         if (ecode != HAL_OK)
2901                 return ecode;
2902         ecode = ath9k_hw_rfattach(ah);
2903         if (ecode != HAL_OK)
2904                 return ecode;
2905
2906         if (!AR_SREV_9100(ah)) {
2907                 ath9k_hw_ani_setup(ah);
2908                 ath9k_hw_ani_attach(ah);
2909         }
2910         return HAL_OK;
2911 }
2912
2913 static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
2914                                     struct ar5416_eeprom *pEepData,
2915                                     u_int32_t reg, u_int32_t value)
2916 {
2917         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2918
2919         switch (ah->ah_devid) {
2920         case AR9280_DEVID_PCI:
2921                 if (reg == 0x7894) {
2922                         HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2923                                  "ini VAL: %x  EEPROM: %x\n", value,
2924                                  (pBase->version & 0xff));
2925
2926                         if ((pBase->version & 0xff) > 0x0a) {
2927                                 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2928                                          "PWDCLKIND: %d\n",
2929                                          pBase->pwdclkind);
2930                                 value &= ~AR_AN_TOP2_PWDCLKIND;
2931                                 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2932                                          pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2933                         } else {
2934                                 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2935                                          "PWDCLKIND Earlier Rev\n");
2936                         }
2937
2938                         HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2939                                  "final ini VAL: %x\n", value);
2940                 }
2941                 break;
2942         }
2943         return value;
2944 }
2945
2946 static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2947 {
2948         struct ath_hal_5416 *ahp = AH5416(ah);
2949         struct hal_capabilities *pCap = &ah->ah_caps;
2950         u_int16_t capField = 0, eeval;
2951
2952         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2953
2954         ah->ah_currentRD = eeval;
2955
2956         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2957         ah->ah_currentRDExt = eeval;
2958
2959         capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2960
2961         if (ah->ah_opmode != HAL_M_HOSTAP &&
2962             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2963                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2964                         ah->ah_currentRD += 5;
2965                 else if (ah->ah_currentRD == 0x41)
2966                         ah->ah_currentRD = 0x43;
2967                 HDPRINTF(ah, HAL_DBG_REGULATORY,
2968                          "%s: regdomain mapped to 0x%x\n", __func__,
2969                          ah->ah_currentRD);
2970         }
2971
2972         pCap->halWirelessModes = 0;
2973         eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2974
2975         if (eeval & AR5416_OPFLAGS_11A) {
2976                 pCap->halWirelessModes |= ATH9K_MODE_SEL_11A |
2977                         ((!ah->ah_config.ath_hal_htEnable
2978                           || (eeval & AR5416_OPFLAGS_N_5G_HT20)) ? 0
2979                          : (ATH9K_MODE_SEL_11NA_HT20 |
2980                             ((eeval & AR5416_OPFLAGS_N_5G_HT40) ? 0
2981                              : (ATH9K_MODE_SEL_11NA_HT40PLUS |
2982                                 ATH9K_MODE_SEL_11NA_HT40MINUS))));
2983         }
2984         if (eeval & AR5416_OPFLAGS_11G) {
2985                 pCap->halWirelessModes |=
2986                         ATH9K_MODE_SEL_11B | ATH9K_MODE_SEL_11G |
2987                         ((!ah->ah_config.ath_hal_htEnable
2988                           || (eeval & AR5416_OPFLAGS_N_2G_HT20)) ? 0
2989                          : (ATH9K_MODE_SEL_11NG_HT20 |
2990                             ((eeval & AR5416_OPFLAGS_N_2G_HT40) ? 0
2991                              : (ATH9K_MODE_SEL_11NG_HT40PLUS |
2992                                 ATH9K_MODE_SEL_11NG_HT40MINUS))));
2993
2994         }
2995         pCap->halTxChainMask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2996         if ((ah->ah_isPciExpress)
2997             || (eeval & AR5416_OPFLAGS_11A)) {
2998                 pCap->halRxChainMask =
2999                         ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3000         } else {
3001                 pCap->halRxChainMask =
3002                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3003         }
3004
3005         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3006                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3007
3008         pCap->halLow2GhzChan = 2312;
3009         pCap->halHigh2GhzChan = 2732;
3010
3011         pCap->halLow5GhzChan = 4920;
3012         pCap->halHigh5GhzChan = 6100;
3013
3014         pCap->halCipherCkipSupport = AH_FALSE;
3015         pCap->halCipherTkipSupport = AH_TRUE;
3016         pCap->halCipherAesCcmSupport = AH_TRUE;
3017
3018         pCap->halMicCkipSupport = AH_FALSE;
3019         pCap->halMicTkipSupport = AH_TRUE;
3020         pCap->halMicAesCcmSupport = AH_TRUE;
3021
3022         pCap->halChanSpreadSupport = AH_TRUE;
3023
3024         pCap->halHTSupport =
3025                 ah->ah_config.ath_hal_htEnable ? AH_TRUE : AH_FALSE;
3026         pCap->halGTTSupport = AH_TRUE;
3027         pCap->halVEOLSupport = AH_TRUE;
3028         pCap->halBssIdMaskSupport = AH_TRUE;
3029         pCap->halMcastKeySrchSupport = AH_FALSE;
3030
3031         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3032                 pCap->halTotalQueues =
3033                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3034         else
3035                 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
3036
3037         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3038                 pCap->halKeyCacheSize =
3039                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3040         else
3041                 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
3042
3043         pCap->halFastCCSupport = AH_TRUE;
3044         pCap->halNumMRRetries = 4;
3045         pCap->halTxTrigLevelMax = MAX_TX_FIFO_THRESHOLD;
3046
3047         if (AR_SREV_9280_10_OR_LATER(ah))
3048                 pCap->halNumGpioPins = AR928X_NUM_GPIO;
3049         else
3050                 pCap->halNumGpioPins = AR_NUM_GPIO;
3051
3052         if (AR_SREV_9280_10_OR_LATER(ah)) {
3053                 pCap->halWowSupport = AH_TRUE;
3054                 pCap->halWowMatchPatternExact = AH_TRUE;
3055         } else {
3056                 pCap->halWowSupport = AH_FALSE;
3057                 pCap->halWowMatchPatternExact = AH_FALSE;
3058         }
3059
3060         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3061                 pCap->halCSTSupport = AH_TRUE;
3062                 pCap->halRtsAggrLimit = ATH_AMPDU_LIMIT_MAX;
3063         } else {
3064                 pCap->halRtsAggrLimit = (8 * 1024);
3065         }
3066
3067         pCap->halEnhancedPmSupport = AH_TRUE;
3068
3069         ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3070         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3071                 ahp->ah_gpioSelect =
3072                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3073                 ahp->ah_polarity =
3074                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3075
3076                 ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, AH_TRUE,
3077                                        NULL);
3078                 pCap->halRfSilentSupport = AH_TRUE;
3079         }
3080
3081         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3082             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3083             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3084             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3085             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3086                 pCap->halAutoSleepSupport = AH_FALSE;
3087         else
3088                 pCap->halAutoSleepSupport = AH_TRUE;
3089
3090         if (AR_SREV_9280(ah))
3091                 pCap->hal4kbSplitTransSupport = AH_FALSE;
3092         else
3093                 pCap->hal4kbSplitTransSupport = AH_TRUE;
3094
3095         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3096                 pCap->halRegCap =
3097                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3098                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3099                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3100                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3101         } else {
3102                 pCap->halRegCap =
3103                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3104                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3105         }
3106
3107         pCap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3108
3109         pCap->halNumAntCfg5GHz =
3110                 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ);
3111         pCap->halNumAntCfg2GHz =
3112                 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
3113
3114         return AH_TRUE;
3115 }
3116
3117 static void ar5416DisablePciePhy(struct ath_hal *ah)
3118 {
3119         if (!AR_SREV_9100(ah))
3120                 return;
3121
3122         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3123         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3124         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3125         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3126         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3127         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3128         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3129         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3130         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3131
3132         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3133 }
3134
3135 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3136 {
3137         OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3138         if (setChip) {
3139                 OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3140                                AR_RTC_FORCE_WAKE_EN);
3141                 if (!AR_SREV_9100(ah))
3142                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3143
3144                 OS_REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
3145                                AR_RTC_RESET_EN);
3146         }
3147 }
3148
3149 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3150 {
3151         OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3152         if (setChip) {
3153                 struct hal_capabilities *pCap = &ah->ah_caps;
3154
3155                 if (!pCap->halAutoSleepSupport) {
3156                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3157                                   AR_RTC_FORCE_WAKE_ON_INT);
3158                 } else {
3159                         OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3160                                        AR_RTC_FORCE_WAKE_EN);
3161                 }
3162         }
3163 }
3164
3165 static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3166                                               int setChip)
3167 {
3168         u_int32_t val;
3169         int i;
3170
3171         if (setChip) {
3172                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3173                     AR_RTC_STATUS_SHUTDOWN) {
3174                         if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
3175                             != AH_TRUE) {
3176                                 return AH_FALSE;
3177                         }
3178                 }
3179                 if (AR_SREV_9100(ah))
3180                         OS_REG_SET_BIT(ah, AR_RTC_RESET,
3181                                        AR_RTC_RESET_EN);
3182
3183                 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3184                                AR_RTC_FORCE_WAKE_EN);
3185                 udelay(50);
3186
3187                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3188                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3189                         if (val == AR_RTC_STATUS_ON)
3190                                 break;
3191                         udelay(50);
3192                         OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3193                                        AR_RTC_FORCE_WAKE_EN);
3194                 }
3195                 if (i == 0) {
3196                         HDPRINTF(ah, HAL_DBG_POWER_MGMT,
3197                                  "%s: Failed to wakeup in %uus\n",
3198                                  __func__, POWER_UP_TIME / 20);
3199                         return AH_FALSE;
3200                 }
3201         }
3202
3203         OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3204         return AH_TRUE;
3205 }
3206
3207 enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
3208                                 enum hal_power_mode mode)
3209 {
3210         struct ath_hal_5416 *ahp = AH5416(ah);
3211         static const char *modes[] = {
3212                 "AWAKE",
3213                 "FULL-SLEEP",
3214                 "NETWORK SLEEP",
3215                 "UNDEFINED"
3216         };
3217         int status = AH_TRUE, setChip = AH_TRUE;
3218
3219         HDPRINTF(ah, HAL_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3220                  modes[ahp->ah_powerMode], modes[mode],
3221                  setChip ? "set chip " : "");
3222
3223         switch (mode) {
3224         case HAL_PM_AWAKE:
3225                 status = ath9k_hw_set_power_awake(ah, setChip);
3226                 break;
3227         case HAL_PM_FULL_SLEEP:
3228                 ath9k_set_power_sleep(ah, setChip);
3229                 ahp->ah_chipFullSleep = AH_TRUE;
3230                 break;
3231         case HAL_PM_NETWORK_SLEEP:
3232                 ath9k_set_power_network_sleep(ah, setChip);
3233                 break;
3234         default:
3235                 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
3236                          "%s: unknown power mode %u\n", __func__, mode);
3237                 return AH_FALSE;
3238         }
3239         ahp->ah_powerMode = mode;
3240         return status;
3241 }
3242
3243 static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
3244                                           void __iomem *mem,
3245                                           enum hal_status *status)
3246 {
3247         struct ath_hal_5416 *ahp;
3248         struct ath_hal *ah;
3249         enum hal_status ecode;
3250 #ifndef CONFIG_SLOW_ANT_DIV
3251         u_int32_t i;
3252         u_int32_t j;
3253 #endif
3254
3255         ahp = ath9k_hw_newstate(devid, sc, mem, status);
3256         if (ahp == NULL)
3257                 return NULL;
3258
3259         ah = &ahp->ah;
3260
3261         ath9k_hw_set_defaults(ah);
3262
3263         if (ah->ah_config.ath_hal_intrMitigation != 0)
3264                 ahp->ah_intrMitigation = AH_TRUE;
3265
3266         if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
3267                 HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't reset chip\n",
3268                          __func__);
3269                 ecode = HAL_EIO;
3270                 goto bad;
3271         }
3272
3273         if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
3274                 HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't wakeup chip\n",
3275                          __func__);
3276                 ecode = HAL_EIO;
3277                 goto bad;
3278         }
3279
3280         if (ah->ah_config.ath_hal_serializeRegMode == SER_REG_MODE_AUTO) {
3281                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3282                         ah->ah_config.ath_hal_serializeRegMode =
3283                                 SER_REG_MODE_ON;
3284                 } else {
3285                         ah->ah_config.ath_hal_serializeRegMode =
3286                                 SER_REG_MODE_OFF;
3287                 }
3288         }
3289         HDPRINTF(ah, HAL_DBG_RESET, "%s: ath_hal_serializeRegMode is %d\n",
3290                  __func__, ah->ah_config.ath_hal_serializeRegMode);
3291
3292         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3293             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3294             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3295             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3296                 HDPRINTF(ah, HAL_DBG_RESET,
3297                          "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3298                          "this driver\n", __func__,
3299                          ah->ah_macVersion, ah->ah_macRev);
3300                 ecode = HAL_ENOTSUPP;
3301                 goto bad;
3302         }
3303
3304         if (AR_SREV_9100(ah)) {
3305                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3306                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3307                 ah->ah_isPciExpress = AH_FALSE;
3308         }
3309         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3310
3311         if (AR_SREV_9160_10_OR_LATER(ah)) {
3312                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3313                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3314                         ahp->ah_adcGainCalData.calData =
3315                                 &adc_gain_cal_single_sample;
3316                         ahp->ah_adcDcCalData.calData =
3317                                 &adc_dc_cal_single_sample;
3318                         ahp->ah_adcDcCalInitData.calData =
3319                                 &adc_init_dc_cal;
3320                 } else {
3321                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3322                         ahp->ah_adcGainCalData.calData =
3323                                 &adc_gain_cal_multi_sample;
3324                         ahp->ah_adcDcCalData.calData =
3325                                 &adc_dc_cal_multi_sample;
3326                         ahp->ah_adcDcCalInitData.calData =
3327                                 &adc_init_dc_cal;
3328                 }
3329                 ahp->ah_suppCals =
3330                         ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3331         }
3332
3333         if (AR_SREV_9160(ah)) {
3334                 ah->ah_config.ath_hal_enableANI = 1;
3335                 ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
3336                                         HAL_ANI_FIRSTEP_LEVEL);
3337         } else {
3338                 ahp->ah_ani_function = HAL_ANI_ALL;
3339                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3340                         ahp->ah_ani_function &=
3341                                 ~HAL_ANI_NOISE_IMMUNITY_LEVEL;
3342                 }
3343         }
3344
3345         HDPRINTF(ah, HAL_DBG_RESET,
3346                  "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3347                  ah->ah_macVersion, ah->ah_macRev);
3348
3349         if (AR_SREV_9280_20_OR_LATER(ah)) {
3350                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3351                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
3352                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3353                                ARRAY_SIZE(ar9280Common_9280_2), 2);
3354
3355                 if (ah->ah_config.ath_hal_pcieClockReq) {
3356                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3357                                        ar9280PciePhy_clkreq_off_L1_9280,
3358                                        ARRAY_SIZE
3359                                        (ar9280PciePhy_clkreq_off_L1_9280),
3360                                        2);
3361                 } else {
3362                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3363                                        ar9280PciePhy_clkreq_always_on_L1_9280,
3364                                        ARRAY_SIZE
3365                                        (ar9280PciePhy_clkreq_always_on_L1_9280),
3366                                        2);
3367                 }
3368                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3369                                ar9280Modes_fast_clock_9280_2,
3370                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3371                                3);
3372         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3373                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3374                                ARRAY_SIZE(ar9280Modes_9280), 6);
3375                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3376                                ARRAY_SIZE(ar9280Common_9280), 2);
3377         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3378                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3379                                ARRAY_SIZE(ar5416Modes_9160), 6);
3380                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3381                                ARRAY_SIZE(ar5416Common_9160), 2);
3382                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3383                                ARRAY_SIZE(ar5416Bank0_9160), 2);
3384                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3385                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3386                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3387                                ARRAY_SIZE(ar5416Bank1_9160), 2);
3388                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3389                                ARRAY_SIZE(ar5416Bank2_9160), 2);
3390                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3391                                ARRAY_SIZE(ar5416Bank3_9160), 3);
3392                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3393                                ARRAY_SIZE(ar5416Bank6_9160), 3);
3394                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3395                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3396                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3397                                ARRAY_SIZE(ar5416Bank7_9160), 2);
3398                 if (AR_SREV_9160_11(ah)) {
3399                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
3400                                        ar5416Addac_91601_1,
3401                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
3402                 } else {
3403                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3404                                        ARRAY_SIZE(ar5416Addac_9160), 2);
3405                 }
3406         } else if (AR_SREV_9100_OR_LATER(ah)) {
3407                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3408                                ARRAY_SIZE(ar5416Modes_9100), 6);
3409                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3410                                ARRAY_SIZE(ar5416Common_9100), 2);
3411                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3412                                ARRAY_SIZE(ar5416Bank0_9100), 2);
3413                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3414                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3415                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3416                                ARRAY_SIZE(ar5416Bank1_9100), 2);
3417                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3418                                ARRAY_SIZE(ar5416Bank2_9100), 2);
3419                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3420                                ARRAY_SIZE(ar5416Bank3_9100), 3);
3421                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3422                                ARRAY_SIZE(ar5416Bank6_9100), 3);
3423                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3424                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3425                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3426                                ARRAY_SIZE(ar5416Bank7_9100), 2);
3427                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3428                                ARRAY_SIZE(ar5416Addac_9100), 2);
3429         } else {
3430                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3431                                ARRAY_SIZE(ar5416Modes), 6);
3432                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3433                                ARRAY_SIZE(ar5416Common), 2);
3434                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3435                                ARRAY_SIZE(ar5416Bank0), 2);
3436                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3437                                ARRAY_SIZE(ar5416BB_RfGain), 3);
3438                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3439                                ARRAY_SIZE(ar5416Bank1), 2);
3440                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3441                                ARRAY_SIZE(ar5416Bank2), 2);
3442                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3443                                ARRAY_SIZE(ar5416Bank3), 3);
3444                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3445                                ARRAY_SIZE(ar5416Bank6), 3);
3446                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3447                                ARRAY_SIZE(ar5416Bank6TPC), 3);
3448                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3449                                ARRAY_SIZE(ar5416Bank7), 2);
3450                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3451                                ARRAY_SIZE(ar5416Addac), 2);
3452         }
3453
3454         if (ah->ah_isPciExpress)
3455                 ath9k_hw_configpcipowersave(ah, 0);
3456         else
3457                 ar5416DisablePciePhy(ah);
3458
3459         ecode = ath9k_hw_post_attach(ah);
3460         if (ecode != HAL_OK)
3461                 goto bad;
3462
3463 #ifndef CONFIG_SLOW_ANT_DIV
3464         if (ah->ah_devid == AR9280_DEVID_PCI) {
3465                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3466                         u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
3467
3468                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3469                                 u_int32_t val = INI_RA(&ahp->ah_iniModes, i, j);
3470
3471                                 INI_RA(&ahp->ah_iniModes, i, j) =
3472                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3473                                                            reg, val);
3474                         }
3475                 }
3476         }
3477 #endif
3478
3479         if (!ath9k_hw_fill_cap_info(ah)) {
3480                 HDPRINTF(ah, HAL_DBG_RESET,
3481                          "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3482                 ecode = HAL_EEREAD;
3483                 goto bad;
3484         }
3485
3486         ecode = ath9k_hw_init_macaddr(ah);
3487         if (ecode != HAL_OK) {
3488                 HDPRINTF(ah, HAL_DBG_RESET,
3489                          "%s: failed initializing mac address\n",
3490                          __func__);
3491                 goto bad;
3492         }
3493
3494         if (AR_SREV_9285(ah))
3495                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3496         else
3497                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3498
3499 #ifndef ATH_NF_PER_CHAN
3500
3501         ath9k_init_nfcal_hist_buffer(ah);
3502 #endif
3503
3504         return ah;
3505
3506 bad:
3507         if (ahp)
3508                 ath9k_hw_detach((struct ath_hal *) ahp);
3509         if (status)
3510                 *status = ecode;
3511         return NULL;
3512 }
3513
3514 void ath9k_hw_detach(struct ath_hal *ah)
3515 {
3516         if (!AR_SREV_9100(ah))
3517                 ath9k_hw_ani_detach(ah);
3518         ath9k_hw_rfdetach(ah);
3519
3520         ath9k_hw_setpower(ah, HAL_PM_FULL_SLEEP);
3521         kfree(ah);
3522 }
3523
3524 enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
3525                                       u_int16_t flags, u_int16_t *low,
3526                                       u_int16_t *high)
3527 {
3528         struct hal_capabilities *pCap = &ah->ah_caps;
3529
3530         if (flags & CHANNEL_5GHZ) {
3531                 *low = pCap->halLow5GhzChan;
3532                 *high = pCap->halHigh5GhzChan;
3533                 return AH_TRUE;
3534         }
3535         if ((flags & CHANNEL_2GHZ)) {
3536                 *low = pCap->halLow2GhzChan;
3537                 *high = pCap->halHigh2GhzChan;
3538
3539                 return AH_TRUE;
3540         }
3541         return AH_FALSE;
3542 }
3543
3544 static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
3545                                                     u_int8_t pwrMax,
3546                                                     u_int8_t *pPwrList,
3547                                                     u_int8_t *pVpdList,
3548                                                     u_int16_t
3549                                                     numIntercepts,
3550                                                     u_int8_t *pRetVpdList)
3551 {
3552         u_int16_t i, k;
3553         u_int8_t currPwr = pwrMin;
3554         u_int16_t idxL = 0, idxR = 0;
3555
3556         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3557                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3558                                                numIntercepts, &(idxL),
3559                                                &(idxR));
3560                 if (idxR < 1)
3561                         idxR = 1;
3562                 if (idxL == numIntercepts - 1)
3563                         idxL = (u_int16_t) (numIntercepts - 2);
3564                 if (pPwrList[idxL] == pPwrList[idxR])
3565                         k = pVpdList[idxL];
3566                 else
3567                         k = (u_int16_t) (((currPwr -
3568                                            pPwrList[idxL]) *
3569                                           pVpdList[idxR] +
3570                                           (pPwrList[idxR] -
3571                                            currPwr) * pVpdList[idxL]) /
3572                                          (pPwrList[idxR] -
3573                                           pPwrList[idxL]));
3574                 pRetVpdList[i] = (u_int8_t) k;
3575                 currPwr += 2;
3576         }
3577
3578         return AH_TRUE;
3579 }
3580
3581 static inline void
3582 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3583                                     struct hal_channel_internal *chan,
3584                                     struct cal_data_per_freq *pRawDataSet,
3585                                     u_int8_t *bChans,
3586                                     u_int16_t availPiers,
3587                                     u_int16_t tPdGainOverlap,
3588                                     int16_t *pMinCalPower,
3589                                     u_int16_t *pPdGainBoundaries,
3590                                     u_int8_t *pPDADCValues,
3591                                     u_int16_t numXpdGains)
3592 {
3593         int i, j, k;
3594         int16_t ss;
3595         u_int16_t idxL = 0, idxR = 0, numPiers;
3596         static u_int8_t vpdTableL[AR5416_NUM_PD_GAINS]
3597                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3598         static u_int8_t vpdTableR[AR5416_NUM_PD_GAINS]
3599                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3600         static u_int8_t vpdTableI[AR5416_NUM_PD_GAINS]
3601                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3602
3603         u_int8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3604         u_int8_t minPwrT4[AR5416_NUM_PD_GAINS];
3605         u_int8_t maxPwrT4[AR5416_NUM_PD_GAINS];
3606         int16_t vpdStep;
3607         int16_t tmpVal;
3608         u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
3609         enum hal_bool match;
3610         int16_t minDelta = 0;
3611         struct chan_centers centers;
3612
3613         ath9k_hw_get_channel_centers(ah, chan, &centers);
3614
3615         for (numPiers = 0; numPiers < availPiers; numPiers++) {
3616                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3617                         break;
3618         }
3619
3620         match = ath9k_hw_get_lower_upper_index((u_int8_t)
3621                                                FREQ2FBIN(centers.
3622                                                          synth_center,
3623                                                          IS_CHAN_2GHZ
3624                                                          (chan)), bChans,
3625                                                numPiers, &idxL, &idxR);
3626
3627         if (match) {
3628                 for (i = 0; i < numXpdGains; i++) {
3629                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3630                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3631                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3632                                                 pRawDataSet[idxL].
3633                                                 pwrPdg[i],
3634                                                 pRawDataSet[idxL].
3635                                                 vpdPdg[i],
3636                                                 AR5416_PD_GAIN_ICEPTS,
3637                                                 vpdTableI[i]);
3638                 }
3639         } else {
3640                 for (i = 0; i < numXpdGains; i++) {
3641                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
3642                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
3643                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
3644                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
3645
3646                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3647
3648                         maxPwrT4[i] =
3649                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3650                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3651
3652
3653                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3654                                                 pPwrL, pVpdL,
3655                                                 AR5416_PD_GAIN_ICEPTS,
3656                                                 vpdTableL[i]);
3657                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3658                                                 pPwrR, pVpdR,
3659                                                 AR5416_PD_GAIN_ICEPTS,
3660                                                 vpdTableR[i]);
3661
3662                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3663                                 vpdTableI[i][j] =
3664                                         (u_int8_t) (ath9k_hw_interpolate
3665                                                     ((u_int16_t)
3666                                                      FREQ2FBIN(centers.
3667                                                                synth_center,
3668                                                                IS_CHAN_2GHZ
3669                                                                (chan)),
3670                                                      bChans[idxL],
3671                                                      bChans[idxR], vpdTableL[i]
3672                                                      [j], vpdTableR[i]
3673                                                      [j]));
3674                         }
3675                 }
3676         }
3677
3678         *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3679
3680         k = 0;
3681         for (i = 0; i < numXpdGains; i++) {
3682                 if (i == (numXpdGains - 1))
3683                         pPdGainBoundaries[i] =
3684                                 (u_int16_t) (maxPwrT4[i] / 2);
3685                 else
3686                         pPdGainBoundaries[i] =
3687                                 (u_int16_t) ((maxPwrT4[i] +
3688                                               minPwrT4[i + 1]) / 4);
3689
3690                 pPdGainBoundaries[i] =
3691                         min((u_int16_t) AR5416_MAX_RATE_POWER,
3692                             pPdGainBoundaries[i]);
3693
3694                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3695                         minDelta = pPdGainBoundaries[0] - 23;
3696                         pPdGainBoundaries[0] = 23;
3697                 } else {
3698                         minDelta = 0;
3699                 }
3700
3701                 if (i == 0) {
3702                         if (AR_SREV_9280_10_OR_LATER(ah))
3703                                 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3704                         else
3705                                 ss = 0;
3706                 } else {
3707                         ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3708                                          (minPwrT4[i] / 2)) -
3709                                         tPdGainOverlap + 1 + minDelta);
3710                 }
3711                 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3712                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3713
3714                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3715                         tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3716                         pPDADCValues[k++] =
3717                                 (u_int8_t) ((tmpVal < 0) ? 0 : tmpVal);
3718                         ss++;
3719                 }
3720
3721                 sizeCurrVpdTable =
3722                         (u_int8_t) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3723                 tgtIndex = (u_int8_t) (pPdGainBoundaries[i] + tPdGainOverlap -
3724                                        (minPwrT4[i] / 2));
3725                 maxIndex = (tgtIndex <
3726                             sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3727
3728                 while ((ss < maxIndex)
3729                        && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3730                         pPDADCValues[k++] = vpdTableI[i][ss++];
3731                 }
3732
3733                 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3734                                      vpdTableI[i][sizeCurrVpdTable - 2]);
3735                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3736
3737                 if (tgtIndex > maxIndex) {
3738                         while ((ss <= tgtIndex)
3739                                && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3740                                 tmpVal = (int16_t) ((vpdTableI[i]
3741                                                      [sizeCurrVpdTable -
3742                                                       1] + (ss - maxIndex +
3743                                                             1) * vpdStep));
3744                                 pPDADCValues[k++] = (u_int8_t) ((tmpVal >
3745                                                  255) ? 255 : tmpVal);
3746                                 ss++;
3747                         }
3748                 }
3749         }
3750
3751         while (i < AR5416_PD_GAINS_IN_MASK) {
3752                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3753                 i++;
3754         }
3755
3756         while (k < AR5416_NUM_PDADC_VALUES) {
3757                 pPDADCValues[k] = pPDADCValues[k - 1];
3758                 k++;
3759         }
3760         return;
3761 }
3762
3763 static inline enum hal_bool
3764 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3765                              struct ar5416_eeprom *pEepData,
3766                              struct hal_channel_internal *chan,
3767                              int16_t *pTxPowerIndexOffset)
3768 {
3769         struct cal_data_per_freq *pRawDataset;
3770         u_int8_t *pCalBChans = NULL;
3771         u_int16_t pdGainOverlap_t2;
3772         static u_int8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
3773         u_int16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3774         u_int16_t numPiers, i, j;
3775         int16_t tMinCalPower;
3776         u_int16_t numXpdGain, xpdMask;
3777         u_int16_t xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3778         u_int32_t reg32, regOffset, regChainOffset;
3779         int16_t modalIdx;
3780         struct ath_hal_5416 *ahp = AH5416(ah);
3781
3782         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3783         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3784
3785         if ((pEepData->baseEepHeader.
3786              version & AR5416_EEP_VER_MINOR_MASK) >=
3787             AR5416_EEP_MINOR_VER_2) {
3788                 pdGainOverlap_t2 =
3789                         pEepData->modalHeader[modalIdx].pdGainOverlap;
3790         } else {
3791                 pdGainOverlap_t2 =
3792                         (u_int16_t) (MS
3793                                      (REG_READ(ah, AR_PHY_TPCRG5),
3794                                       AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3795         }
3796
3797         if (IS_CHAN_2GHZ(chan)) {
3798                 pCalBChans = pEepData->calFreqPier2G;
3799                 numPiers = AR5416_NUM_2G_CAL_PIERS;
3800         } else {
3801                 pCalBChans = pEepData->calFreqPier5G;
3802                 numPiers = AR5416_NUM_5G_CAL_PIERS;
3803         }
3804
3805         numXpdGain = 0;
3806
3807         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3808                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3809                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
3810                                 break;
3811                         xpdGainValues[numXpdGain] =
3812                                 (u_int16_t) (AR5416_PD_GAINS_IN_MASK - i);
3813                         numXpdGain++;
3814                 }
3815         }
3816
3817         OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3818                          (numXpdGain - 1) & 0x3);
3819         OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3820                          xpdGainValues[0]);
3821         OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3822                          xpdGainValues[1]);
3823         OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3824                          xpdGainValues[2]);
3825
3826         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3827                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3828                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3829                     && (i != 0)) {
3830                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3831                 } else
3832                         regChainOffset = i * 0x1000;
3833                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3834                         if (IS_CHAN_2GHZ(chan))
3835                                 pRawDataset = pEepData->calPierData2G[i];
3836                         else
3837                                 pRawDataset = pEepData->calPierData5G[i];
3838
3839                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3840                                                             pRawDataset,
3841                                                             pCalBChans,
3842                                                             numPiers,
3843                                                             pdGainOverlap_t2,
3844                                                             &tMinCalPower,
3845                                                             gainBoundaries,
3846                                                             pdadcValues,
3847                                                             numXpdGain);
3848
3849                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3850
3851                                 REG_WRITE(ah,
3852                                           AR_PHY_TPCRG5 + regChainOffset,
3853                                           SM(pdGainOverlap_t2,
3854                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3855                                           | SM(gainBoundaries[0],
3856                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3857                                           | SM(gainBoundaries[1],
3858                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3859                                           | SM(gainBoundaries[2],
3860                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3861                                           | SM(gainBoundaries[3],
3862                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3863                         }
3864
3865                         regOffset =
3866                                 AR_PHY_BASE + (672 << 2) + regChainOffset;
3867                         for (j = 0; j < 32; j++) {
3868                                 reg32 =
3869                                         ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3870                                         | ((pdadcValues[4 * j + 1] & 0xFF) <<
3871                                            8) | ((pdadcValues[4 * j + 2] &
3872                                                   0xFF) << 16) |
3873                                         ((pdadcValues[4 * j + 3] & 0xFF) <<
3874                                          24);
3875                                 REG_WRITE(ah, regOffset, reg32);
3876
3877                                 HDPRINTF(ah, HAL_DBG_PHY_IO,
3878                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
3879                                          i, regChainOffset, regOffset,
3880                                          reg32);
3881                                 HDPRINTF(ah, HAL_DBG_PHY_IO,
3882                                 "PDADC: Chain %d | PDADC %3d Value %3d | "
3883                                 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3884                                 "PDADC %3d Value %3d |\n",
3885                                          i, 4 * j, pdadcValues[4 * j],
3886                                          4 * j + 1, pdadcValues[4 * j + 1],
3887                                          4 * j + 2, pdadcValues[4 * j + 2],
3888                                          4 * j + 3,
3889                                          pdadcValues[4 * j + 3]);
3890
3891                                 regOffset += 4;
3892                         }
3893                 }
3894         }
3895         *pTxPowerIndexOffset = 0;
3896
3897         return AH_TRUE;
3898 }
3899
3900 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3901 {
3902         struct ath_hal_5416 *ahp = AH5416(ah);
3903         u_int8_t i;
3904
3905         if (ah->ah_isPciExpress != AH_TRUE)
3906                 return;
3907
3908         if (ah->ah_config.ath_hal_pciePowerSaveEnable == 2)
3909                 return;
3910
3911         if (restore)
3912                 return;
3913
3914         if (AR_SREV_9280_20_OR_LATER(ah)) {
3915                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3916                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3917                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3918                 }
3919                 udelay(1000);
3920         } else if (AR_SREV_9280(ah)
3921                    && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3922                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3923                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3924
3925                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3926                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3927                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3928
3929                 if (ah->ah_config.ath_hal_pcieClockReq)
3930                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3931                 else
3932                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3933
3934                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3935                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3936                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3937
3938                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3939
3940                 udelay(1000);
3941         } else {
3942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3943                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3944                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3945                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3946                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3947                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3949                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3950                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3951                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3952         }
3953
3954         OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3955
3956         if (ah->ah_config.ath_hal_pcieWaen) {
3957                 REG_WRITE(ah, AR_WA, ah->ah_config.ath_hal_pcieWaen);
3958         } else {
3959                 if (AR_SREV_9280(ah))
3960                         REG_WRITE(ah, AR_WA, 0x0040073f);
3961                 else
3962                         REG_WRITE(ah, AR_WA, 0x0000073f);
3963         }
3964 }
3965
3966 static inline void
3967 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3968                                   struct hal_channel_internal *chan,
3969                                   struct cal_target_power_leg *powInfo,
3970                                   u_int16_t numChannels,
3971                                   struct cal_target_power_leg *pNewPower,
3972                                   u_int16_t numRates,
3973                                   enum hal_bool isExtTarget)
3974 {
3975         u_int16_t clo, chi;
3976         int i;
3977         int matchIndex = -1, lowIndex = -1;
3978         u_int16_t freq;
3979         struct chan_centers centers;
3980
3981         ath9k_hw_get_channel_centers(ah, chan, &centers);
3982         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3983
3984         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3985                 IS_CHAN_2GHZ(chan))) {
3986                 matchIndex = 0;
3987         } else {
3988                 for (i = 0; (i < numChannels)
3989                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
3990                         if (freq ==
3991                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
3992                                                IS_CHAN_2GHZ(chan))) {
3993                                 matchIndex = i;
3994                                 break;
3995                         } else if ((freq <
3996                                     ath9k_hw_fbin2freq(powInfo[i].bChannel,
3997                                                        IS_CHAN_2GHZ(chan)))
3998                                    && (freq >
3999                                        ath9k_hw_fbin2freq(powInfo[i - 1].
4000                                                           bChannel,
4001                                                           IS_CHAN_2GHZ
4002                                                           (chan)))) {
4003                                 lowIndex = i - 1;
4004                                 break;
4005                         }
4006                 }
4007                 if ((matchIndex == -1) && (lowIndex == -1))
4008                         matchIndex = i - 1;
4009         }
4010
4011         if (matchIndex != -1) {
4012                 *pNewPower = powInfo[matchIndex];
4013         } else {
4014                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4015                                          IS_CHAN_2GHZ(chan));
4016                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4017                                          IS_CHAN_2GHZ(chan));
4018
4019                 for (i = 0; i < numRates; i++) {
4020                         pNewPower->tPow2x[i] =
4021                                 (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
4022                                                                 powInfo
4023                                                                 [lowIndex].
4024                                                                 tPow2x[i],
4025                                                                 powInfo
4026                                                                 [lowIndex +
4027                                                                  1].tPow2x[i]);
4028                 }
4029         }
4030 }
4031
4032 static inline void
4033 ath9k_hw_get_target_powers(struct ath_hal *ah,
4034                            struct hal_channel_internal *chan,
4035                            struct cal_target_power_ht *powInfo,
4036                            u_int16_t numChannels,
4037                            struct cal_target_power_ht *pNewPower,
4038                            u_int16_t numRates,
4039                            enum hal_bool isHt40Target)
4040 {
4041         u_int16_t clo, chi;
4042         int i;
4043         int matchIndex = -1, lowIndex = -1;
4044         u_int16_t freq;
4045         struct chan_centers centers;
4046
4047         ath9k_hw_get_channel_centers(ah, chan, &centers);
4048         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4049
4050         if (freq <=
4051                 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4052                 matchIndex = 0;
4053         } else {
4054                 for (i = 0; (i < numChannels)
4055                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4056                         if (freq ==
4057                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4058                                                IS_CHAN_2GHZ(chan))) {
4059                                 matchIndex = i;
4060                                 break;
4061                         } else
4062                                 if ((freq <
4063                                      ath9k_hw_fbin2freq(powInfo[i].bChannel,
4064                                                         IS_CHAN_2GHZ(chan)))
4065                                     && (freq >
4066                                         ath9k_hw_fbin2freq(powInfo[i - 1].
4067                                                            bChannel,
4068                                                            IS_CHAN_2GHZ
4069                                                            (chan)))) {
4070                                         lowIndex = i - 1;
4071                                         break;
4072                                 }
4073                 }
4074                 if ((matchIndex == -1) && (lowIndex == -1))
4075                         matchIndex = i - 1;
4076         }
4077
4078         if (matchIndex != -1) {
4079                 *pNewPower = powInfo[matchIndex];
4080         } else {
4081                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4082                                          IS_CHAN_2GHZ(chan));
4083                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4084                                          IS_CHAN_2GHZ(chan));
4085
4086                 for (i = 0; i < numRates; i++) {
4087                         pNewPower->tPow2x[i] =
4088                                 (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
4089                                                                 powInfo
4090                                                                 [lowIndex].
4091                                                                 tPow2x[i],
4092                                                                 powInfo
4093                                                                 [lowIndex +
4094                                                                  1].tPow2x[i]);
4095                 }
4096         }
4097 }
4098
4099 static inline u_int16_t
4100 ath9k_hw_get_max_edge_power(u_int16_t freq,
4101                             struct cal_ctl_edges *pRdEdgesPower,
4102                             enum hal_bool is2GHz)
4103 {
4104         u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4105         int i;
4106
4107         for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4108              && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4109                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4110                                                is2GHz)) {
4111                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4112                         break;
4113                 } else if ((i > 0)
4114                            && (freq <
4115                                ath9k_hw_fbin2freq(pRdEdgesPower[i].
4116                                                   bChannel, is2GHz))) {
4117                         if (ath9k_hw_fbin2freq
4118                             (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4119                             && pRdEdgesPower[i - 1].flag) {
4120                                 twiceMaxEdgePower =
4121                                         pRdEdgesPower[i - 1].tPower;
4122                         }
4123                         break;
4124                 }
4125         }
4126         return twiceMaxEdgePower;
4127 }
4128
4129 static inline enum hal_bool
4130 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4131                                   struct ar5416_eeprom *pEepData,
4132                                   struct hal_channel_internal *chan,
4133                                   int16_t *ratesArray,
4134                                   u_int16_t cfgCtl,
4135                                   u_int8_t AntennaReduction,
4136                                   u_int8_t twiceMaxRegulatoryPower,
4137                                   u_int8_t powerLimit)
4138 {
4139         u_int8_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4140         static const u_int16_t tpScaleReductionTable[5] =
4141                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4142
4143         int i;
4144         int8_t twiceLargestAntenna;
4145         struct cal_ctl_data *rep;
4146         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4147                 0, { 0, 0, 0, 0}
4148         };
4149         struct cal_target_power_leg targetPowerOfdmExt = {
4150                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4151                 0, { 0, 0, 0, 0 }
4152         };
4153         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4154                 0, {0, 0, 0, 0}
4155         };
4156         u_int8_t scaledPower = 0, minCtlPower, maxRegAllowedPower;
4157         u_int16_t ctlModesFor11a[] =
4158                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4159         u_int16_t ctlModesFor11g[] =
4160                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4161                   CTL_2GHT40
4162                 };
4163         u_int16_t numCtlModes, *pCtlMode, ctlMode, freq;
4164         struct chan_centers centers;
4165         int tx_chainmask;
4166         u_int8_t twiceMinEdgePower;
4167         struct ath_hal_5416 *ahp = AH5416(ah);
4168
4169         tx_chainmask = ahp->ah_txchainmask;
4170
4171         ath9k_hw_get_channel_centers(ah, chan, &centers);
4172
4173         twiceLargestAntenna = max(
4174                 pEepData->modalHeader
4175                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4176                 pEepData->modalHeader
4177                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4178
4179         twiceLargestAntenna = max((u_int8_t) twiceLargestAntenna,
4180                 pEepData->modalHeader
4181                         [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4182
4183         twiceLargestAntenna =
4184                 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4185
4186         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4187
4188         if (ah->ah_tpScale != HAL_TP_SCALE_MAX) {
4189                 maxRegAllowedPower -=
4190                         (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4191         }
4192
4193         scaledPower = min(powerLimit, maxRegAllowedPower);
4194
4195         switch (ar5416_get_ntxchains(tx_chainmask)) {
4196         case 1:
4197                 break;
4198         case 2:
4199                 scaledPower -=
4200                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4201                         pwrDecreaseFor2Chain;
4202                 break;
4203         case 3:
4204                 scaledPower -=
4205                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4206                         pwrDecreaseFor3Chain;
4207                 break;
4208         }
4209
4210         scaledPower = max(0, (int32_t) scaledPower);
4211
4212         if (IS_CHAN_2GHZ(chan)) {
4213                 numCtlModes =
4214                         ARRAY_SIZE(ctlModesFor11g) -
4215                         SUB_NUM_CTL_MODES_AT_2G_40;
4216                 pCtlMode = ctlModesFor11g;
4217
4218                 ath9k_hw_get_legacy_target_powers(ah, chan,
4219                         pEepData->
4220                         calTargetPowerCck,
4221                         AR5416_NUM_2G_CCK_TARGET_POWERS,
4222                         &targetPowerCck, 4,
4223                         AH_FALSE);
4224                 ath9k_hw_get_legacy_target_powers(ah, chan,
4225                         pEepData->
4226                         calTargetPower2G,
4227                         AR5416_NUM_2G_20_TARGET_POWERS,
4228                         &targetPowerOfdm, 4,
4229                         AH_FALSE);
4230                 ath9k_hw_get_target_powers(ah, chan,
4231                         pEepData->calTargetPower2GHT20,
4232                         AR5416_NUM_2G_20_TARGET_POWERS,
4233                         &targetPowerHt20, 8, AH_FALSE);
4234
4235                 if (IS_CHAN_HT40(chan)) {
4236                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4237                         ath9k_hw_get_target_powers(ah, chan,
4238                                 pEepData->
4239                                 calTargetPower2GHT40,
4240                                 AR5416_NUM_2G_40_TARGET_POWERS,
4241                                 &targetPowerHt40, 8,
4242                                 AH_TRUE);
4243                         ath9k_hw_get_legacy_target_powers(ah, chan,
4244                                 pEepData->
4245                                 calTargetPowerCck,
4246                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
4247                                 &targetPowerCckExt,
4248                                 4, AH_TRUE);
4249                         ath9k_hw_get_legacy_target_powers(ah, chan,
4250                                 pEepData->
4251                                 calTargetPower2G,
4252                                 AR5416_NUM_2G_20_TARGET_POWERS,
4253                                 &targetPowerOfdmExt,
4254                                 4, AH_TRUE);
4255                 }
4256         } else {
4257
4258                 numCtlModes =
4259                         ARRAY_SIZE(ctlModesFor11a) -
4260                         SUB_NUM_CTL_MODES_AT_5G_40;
4261                 pCtlMode = ctlModesFor11a;
4262
4263                 ath9k_hw_get_legacy_target_powers(ah, chan,
4264                         pEepData->
4265                         calTargetPower5G,
4266                         AR5416_NUM_5G_20_TARGET_POWERS,
4267                         &targetPowerOfdm, 4,
4268                         AH_FALSE);
4269                 ath9k_hw_get_target_powers(ah, chan,
4270                         pEepData->calTargetPower5GHT20,
4271                         AR5416_NUM_5G_20_TARGET_POWERS,
4272                         &targetPowerHt20, 8, AH_FALSE);
4273
4274                 if (IS_CHAN_HT40(chan)) {
4275                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4276                         ath9k_hw_get_target_powers(ah, chan,
4277                                 pEepData->
4278                                 calTargetPower5GHT40,
4279                                 AR5416_NUM_5G_40_TARGET_POWERS,
4280                                 &targetPowerHt40, 8,
4281                                 AH_TRUE);
4282                         ath9k_hw_get_legacy_target_powers(ah, chan,
4283                                 pEepData->
4284                                 calTargetPower5G,
4285                                 AR5416_NUM_5G_20_TARGET_POWERS,
4286                                 &targetPowerOfdmExt,
4287                                 4, AH_TRUE);
4288                 }
4289         }
4290
4291         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4292                 enum hal_bool isHt40CtlMode =
4293                         (pCtlMode[ctlMode] == CTL_5GHT40)
4294                         || (pCtlMode[ctlMode] == CTL_2GHT40);
4295                 if (isHt40CtlMode)
4296                         freq = centers.synth_center;
4297                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4298                         freq = centers.ext_center;
4299                 else
4300                         freq = centers.ctl_center;
4301
4302                 if (ar5416_get_eep_ver(ahp) == 14
4303                     && ar5416_get_eep_rev(ahp) <= 2)
4304                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4305
4306                 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4307                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4308                         "EXT_ADDITIVE %d\n",
4309                          ctlMode, numCtlModes, isHt40CtlMode,
4310                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
4311
4312                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4313                      i++) {
4314                         HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4315                                  "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4316                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4317                                 "chan %d chanctl 0x%x\n",
4318                                  i, cfgCtl, pCtlMode[ctlMode],
4319                                  pEepData->ctlIndex[i], chan->channel,
4320                                  chan->conformanceTestLimit);
4321
4322                         if ((((cfgCtl & ~CTL_MODE_M) |
4323                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4324                              pEepData->ctlIndex[i])
4325                             ||
4326                             (((cfgCtl & ~CTL_MODE_M) |
4327                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4328                              ((pEepData->
4329                                ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4330                                 rep = &(pEepData->ctlData[i]);
4331
4332                                 twiceMinEdgePower =
4333                                         ath9k_hw_get_max_edge_power(freq,
4334                                                 rep->
4335                                                 ctlEdges
4336                                                 [ar5416_get_ntxchains
4337                                                 (tx_chainmask)
4338                                                 - 1],
4339                                                 IS_CHAN_2GHZ
4340                                                 (chan));
4341
4342                                 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4343                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
4344                                         "2xMinEdge %d chainmask %d chains %d\n",
4345                                          i, freq, IS_CHAN_2GHZ(chan),
4346                                          twiceMinEdgePower, tx_chainmask,
4347                                          ar5416_get_ntxchains
4348                                          (tx_chainmask));
4349                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4350                                         twiceMaxEdgePower =
4351                                                 min(twiceMaxEdgePower,
4352                                                     twiceMinEdgePower);
4353                                 } else {
4354                                         twiceMaxEdgePower =
4355                                                 twiceMinEdgePower;
4356                                         break;
4357                                 }
4358                         }
4359                 }
4360
4361                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4362
4363                 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4364                                 "    SEL-Min ctlMode %d pCtlMode %d "
4365                                 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4366                          ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4367                          scaledPower, minCtlPower);
4368
4369                 switch (pCtlMode[ctlMode]) {
4370                 case CTL_11B:
4371                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4372                              i++) {
4373                                 targetPowerCck.tPow2x[i] =
4374                                         min(targetPowerCck.tPow2x[i],
4375                                             minCtlPower);
4376                         }
4377                         break;
4378                 case CTL_11A:
4379                 case CTL_11G:
4380                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4381                              i++) {
4382                                 targetPowerOfdm.tPow2x[i] =
4383                                         min(targetPowerOfdm.tPow2x[i],
4384                                             minCtlPower);
4385                         }
4386                         break;
4387                 case CTL_5GHT20:
4388                 case CTL_2GHT20:
4389                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4390                              i++) {
4391                                 targetPowerHt20.tPow2x[i] =
4392                                         min(targetPowerHt20.tPow2x[i],
4393                                             minCtlPower);
4394                         }
4395                         break;
4396                 case CTL_11B_EXT:
4397                         targetPowerCckExt.tPow2x[0] =
4398                                 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4399                         break;
4400                 case CTL_11A_EXT:
4401                 case CTL_11G_EXT:
4402                         targetPowerOfdmExt.tPow2x[0] =
4403                                 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4404                         break;
4405                 case CTL_5GHT40:
4406                 case CTL_2GHT40:
4407                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4408                              i++) {
4409                                 targetPowerHt40.tPow2x[i] =
4410                                         min(targetPowerHt40.tPow2x[i],
4411                                             minCtlPower);
4412                         }
4413                         break;
4414                 default:
4415                         break;
4416                 }
4417         }
4418
4419         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4420                 ratesArray[rate18mb] = ratesArray[rate24mb] =
4421                 targetPowerOfdm.tPow2x[0];
4422         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4423         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4424         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4425         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4426
4427         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4428                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4429
4430         if (IS_CHAN_2GHZ(chan)) {
4431                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4432                 ratesArray[rate2s] = ratesArray[rate2l] =
4433                         targetPowerCck.tPow2x[1];
4434                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4435                         targetPowerCck.tPow2x[2];
4436                 ;
4437                 ratesArray[rate11s] = ratesArray[rate11l] =
4438                         targetPowerCck.tPow2x[3];
4439                 ;
4440         }
4441         if (IS_CHAN_HT40(chan)) {
4442                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4443                         ratesArray[rateHt40_0 + i] =
4444                                 targetPowerHt40.tPow2x[i];
4445                 }
4446                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4447                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4448                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4449                 if (IS_CHAN_2GHZ(chan)) {
4450                         ratesArray[rateExtCck] =
4451                                 targetPowerCckExt.tPow2x[0];
4452                 }
4453         }
4454         return AH_TRUE;
4455 }
4456
4457 static enum hal_status
4458 ath9k_hw_set_txpower(struct ath_hal *ah,
4459                      struct ar5416_eeprom *pEepData,
4460                      struct hal_channel_internal *chan,
4461                      u_int16_t cfgCtl,
4462                      u_int8_t twiceAntennaReduction,
4463                      u_int8_t twiceMaxRegulatoryPower,
4464                      u_int8_t powerLimit)
4465 {
4466         struct modal_eep_header *pModal =
4467                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4468         int16_t ratesArray[Ar5416RateSize];
4469         int16_t txPowerIndexOffset = 0;
4470         u_int8_t ht40PowerIncForPdadc = 2;
4471         int i;
4472
4473         memset(ratesArray, 0, sizeof(ratesArray));
4474
4475         if ((pEepData->baseEepHeader.
4476              version & AR5416_EEP_VER_MINOR_MASK) >=
4477             AR5416_EEP_MINOR_VER_2) {
4478                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4479         }
4480
4481         if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4482                                                &ratesArray[0], cfgCtl,
4483                                                twiceAntennaReduction,
4484                                                twiceMaxRegulatoryPower,
4485                                                powerLimit)) {
4486                 HDPRINTF(ah, HAL_DBG_EEPROM,
4487                         "ath9k_hw_set_txpower: unable to set "
4488                         "tx power per rate table\n");
4489                 return HAL_EIO;
4490         }
4491
4492         if (!ath9k_hw_set_power_cal_table
4493             (ah, pEepData, chan, &txPowerIndexOffset)) {
4494                 HDPRINTF(ah, HAL_DBG_EEPROM,
4495                          "ath9k_hw_set_txpower: unable to set power table\n");
4496                 return HAL_EIO;
4497         }
4498
4499         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4500                 ratesArray[i] =
4501                         (int16_t) (txPowerIndexOffset + ratesArray[i]);
4502                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4503                         ratesArray[i] = AR5416_MAX_RATE_POWER;
4504         }
4505
4506         if (AR_SREV_9280_10_OR_LATER(ah)) {
4507                 for (i = 0; i < Ar5416RateSize; i++)
4508                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4509         }
4510
4511         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4512                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
4513                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4514                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4515                   | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4516                 );
4517         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4518                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
4519                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4520                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4521                   | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4522                 );
4523
4524         if (IS_CHAN_2GHZ(chan)) {
4525                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4526                           ATH9K_POW_SM(ratesArray[rate2s], 24)
4527                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
4528                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
4529                           | ATH9K_POW_SM(ratesArray[rate1l], 0)
4530                         );
4531                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4532                           ATH9K_POW_SM(ratesArray[rate11s], 24)
4533                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
4534                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4535                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4536                         );
4537         }
4538
4539         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4540                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4541                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4542                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4543                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4544                 );
4545         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4546                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4547                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4548                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4549                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4550                 );
4551
4552         if (IS_CHAN_HT40(chan)) {
4553                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4554                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
4555                                        ht40PowerIncForPdadc, 24)
4556                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4557                                          ht40PowerIncForPdadc, 16)
4558                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4559                                          ht40PowerIncForPdadc, 8)
4560                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4561                                          ht40PowerIncForPdadc, 0)
4562                         );
4563                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4564                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
4565                                        ht40PowerIncForPdadc, 24)
4566                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4567                                          ht40PowerIncForPdadc, 16)
4568                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4569                                          ht40PowerIncForPdadc, 8)
4570                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4571                                          ht40PowerIncForPdadc, 0)
4572                         );
4573
4574                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4575                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4576                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4577                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4578                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4579                         );
4580         }
4581
4582         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4583                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4584                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4585                 );
4586
4587         i = rate6mb;
4588         if (IS_CHAN_HT40(chan))
4589                 i = rateHt40_0;
4590         else if (IS_CHAN_HT20(chan))
4591                 i = rateHt20_0;
4592
4593         if (AR_SREV_9280_10_OR_LATER(ah))
4594                 ah->ah_maxPowerLevel =
4595                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4596         else
4597                 ah->ah_maxPowerLevel = ratesArray[i];
4598
4599         return HAL_OK;
4600 }
4601
4602 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4603                                                  u_int32_t coef_scaled,
4604                                                  u_int32_t *coef_mantissa,
4605                                                  u_int32_t *coef_exponent)
4606 {
4607         u_int32_t coef_exp, coef_man;
4608
4609         for (coef_exp = 31; coef_exp > 0; coef_exp--)
4610                 if ((coef_scaled >> coef_exp) & 0x1)
4611                         break;
4612
4613         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4614
4615         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4616
4617         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4618         *coef_exponent = coef_exp - 16;
4619 }
4620
4621 static void
4622 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4623                          struct hal_channel_internal *chan)
4624 {
4625         u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
4626         u_int32_t clockMhzScaled = 0x64000000;
4627         struct chan_centers centers;
4628
4629         if (IS_CHAN_HALF_RATE(chan))
4630                 clockMhzScaled = clockMhzScaled >> 1;
4631         else if (IS_CHAN_QUARTER_RATE(chan))
4632                 clockMhzScaled = clockMhzScaled >> 2;
4633
4634         ath9k_hw_get_channel_centers(ah, chan, &centers);
4635         coef_scaled = clockMhzScaled / centers.synth_center;
4636
4637         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4638                                       &ds_coef_exp);
4639
4640         OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4641                          AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4642         OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4643                          AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4644
4645         coef_scaled = (9 * coef_scaled) / 10;
4646
4647         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4648                                       &ds_coef_exp);
4649
4650         OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4651                          AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4652         OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4653                          AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4654 }
4655
4656 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4657                                         struct hal_channel *chan,
4658                                         struct hal_channel_internal *ichan)
4659 {
4660         int bb_spur = AR_NO_SPUR;
4661         int freq;
4662         int bin, cur_bin;
4663         int bb_spur_off, spur_subchannel_sd;
4664         int spur_freq_sd;
4665         int spur_delta_phase;
4666         int denominator;
4667         int upper, lower, cur_vit_mask;
4668         int tmp, newVal;
4669         int i;
4670         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4671                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4672         };
4673         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4674                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4675         };
4676         int inc[4] = { 0, 100, 0, 0 };
4677         struct chan_centers centers;
4678
4679         int8_t mask_m[123];
4680         int8_t mask_p[123];
4681         int8_t mask_amt;
4682         int tmp_mask;
4683         int cur_bb_spur;
4684         enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
4685
4686         memset(&mask_m, 0, sizeof(int8_t) * 123);
4687         memset(&mask_p, 0, sizeof(int8_t) * 123);
4688
4689         ath9k_hw_get_channel_centers(ah, ichan, &centers);
4690         freq = centers.synth_center;
4691
4692         ah->ah_config.ath_hal_spurMode = SPUR_ENABLE_EEPROM;
4693         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4694                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4695
4696                 if (is2GHz)
4697                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4698                 else
4699                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4700
4701                 if (AR_NO_SPUR == cur_bb_spur)
4702                         break;
4703                 cur_bb_spur = cur_bb_spur - freq;
4704
4705                 if (IS_CHAN_HT40(chan)) {
4706                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4707                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4708                                 bb_spur = cur_bb_spur;
4709                                 break;
4710                         }
4711                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4712                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4713                         bb_spur = cur_bb_spur;
4714                         break;
4715                 }
4716         }
4717
4718         if (AR_NO_SPUR == bb_spur) {
4719                 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4720                                AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4721                 return;
4722         } else {
4723                 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4724                                AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4725         }
4726
4727         bin = bb_spur * 320;
4728
4729         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4730
4731         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4732                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4733                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4734                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4735         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4736
4737         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4738                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4739                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4740                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4741                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4742         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4743
4744         if (IS_CHAN_HT40(chan)) {
4745                 if (bb_spur < 0) {
4746                         spur_subchannel_sd = 1;
4747                         bb_spur_off = bb_spur + 10;
4748                 } else {
4749                         spur_subchannel_sd = 0;
4750                         bb_spur_off = bb_spur - 10;
4751                 }
4752         } else {
4753                 spur_subchannel_sd = 0;
4754                 bb_spur_off = bb_spur;
4755         }
4756
4757         if (IS_CHAN_HT40(chan))
4758                 spur_delta_phase =
4759                         ((bb_spur * 262144) /
4760                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4761         else
4762                 spur_delta_phase =
4763                         ((bb_spur * 524288) /
4764                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4765
4766         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4767         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4768
4769         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4770                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4771                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4772         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4773
4774         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4775         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4776
4777         cur_bin = -6000;
4778         upper = bin + 100;
4779         lower = bin - 100;
4780
4781         for (i = 0; i < 4; i++) {
4782                 int pilot_mask = 0;
4783                 int chan_mask = 0;
4784                 int bp = 0;
4785                 for (bp = 0; bp < 30; bp++) {
4786                         if ((cur_bin > lower) && (cur_bin < upper)) {
4787                                 pilot_mask = pilot_mask | 0x1 << bp;
4788                                 chan_mask = chan_mask | 0x1 << bp;
4789                         }
4790                         cur_bin += 100;
4791                 }
4792                 cur_bin += inc[i];
4793                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4794                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4795         }
4796
4797         cur_vit_mask = 6100;
4798         upper = bin + 120;
4799         lower = bin - 120;
4800
4801         for (i = 0; i < 123; i++) {
4802                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4803                         if ((abs(cur_vit_mask - bin)) < 75)
4804                                 mask_amt = 1;
4805                         else
4806                                 mask_amt = 0;
4807                         if (cur_vit_mask < 0)
4808                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4809                         else
4810                                 mask_p[cur_vit_mask / 100] = mask_amt;
4811                 }
4812                 cur_vit_mask -= 100;
4813         }
4814
4815         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4816                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4817                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4818                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4819                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4820                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4821                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4822                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4823         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4824         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4825
4826         tmp_mask = (mask_m[31] << 28)
4827                 | (mask_m[32] << 26) | (mask_m[33] << 24)
4828                 | (mask_m[34] << 22) | (mask_m[35] << 20)
4829                 | (mask_m[36] << 18) | (mask_m[37] << 16)
4830                 | (mask_m[48] << 14) | (mask_m[39] << 12)
4831                 | (mask_m[40] << 10) | (mask_m[41] << 8)
4832                 | (mask_m[42] << 6) | (mask_m[43] << 4)
4833                 | (mask_m[44] << 2) | (mask_m[45] << 0);
4834         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4835         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4836
4837         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4838                 | (mask_m[18] << 26) | (mask_m[18] << 24)
4839                 | (mask_m[20] << 22) | (mask_m[20] << 20)
4840                 | (mask_m[22] << 18) | (mask_m[22] << 16)
4841                 | (mask_m[24] << 14) | (mask_m[24] << 12)
4842                 | (mask_m[25] << 10) | (mask_m[26] << 8)
4843                 | (mask_m[27] << 6) | (mask_m[28] << 4)
4844                 | (mask_m[29] << 2) | (mask_m[30] << 0);
4845         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4846         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4847
4848         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4849                 | (mask_m[2] << 26) | (mask_m[3] << 24)
4850                 | (mask_m[4] << 22) | (mask_m[5] << 20)
4851                 | (mask_m[6] << 18) | (mask_m[7] << 16)
4852                 | (mask_m[8] << 14) | (mask_m[9] << 12)
4853                 | (mask_m[10] << 10) | (mask_m[11] << 8)
4854                 | (mask_m[12] << 6) | (mask_m[13] << 4)
4855                 | (mask_m[14] << 2) | (mask_m[15] << 0);
4856         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4857         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4858
4859         tmp_mask = (mask_p[15] << 28)
4860                 | (mask_p[14] << 26) | (mask_p[13] << 24)
4861                 | (mask_p[12] << 22) | (mask_p[11] << 20)
4862                 | (mask_p[10] << 18) | (mask_p[9] << 16)
4863                 | (mask_p[8] << 14) | (mask_p[7] << 12)
4864                 | (mask_p[6] << 10) | (mask_p[5] << 8)
4865                 | (mask_p[4] << 6) | (mask_p[3] << 4)
4866                 | (mask_p[2] << 2) | (mask_p[1] << 0);
4867         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4868         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4869
4870         tmp_mask = (mask_p[30] << 28)
4871                 | (mask_p[29] << 26) | (mask_p[28] << 24)
4872                 | (mask_p[27] << 22) | (mask_p[26] << 20)
4873                 | (mask_p[25] << 18) | (mask_p[24] << 16)
4874                 | (mask_p[23] << 14) | (mask_p[22] << 12)
4875                 | (mask_p[21] << 10) | (mask_p[20] << 8)
4876                 | (mask_p[19] << 6) | (mask_p[18] << 4)
4877                 | (mask_p[17] << 2) | (mask_p[16] << 0);
4878         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4879         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4880
4881         tmp_mask = (mask_p[45] << 28)
4882                 | (mask_p[44] << 26) | (mask_p[43] << 24)
4883                 | (mask_p[42] << 22) | (mask_p[41] << 20)
4884                 | (mask_p[40] << 18) | (mask_p[39] << 16)
4885                 | (mask_p[38] << 14) | (mask_p[37] << 12)
4886                 | (mask_p[36] << 10) | (mask_p[35] << 8)
4887                 | (mask_p[34] << 6) | (mask_p[33] << 4)
4888                 | (mask_p[32] << 2) | (mask_p[31] << 0);
4889         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4890         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4891
4892         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4893                 | (mask_p[59] << 26) | (mask_p[58] << 24)
4894                 | (mask_p[57] << 22) | (mask_p[56] << 20)
4895                 | (mask_p[55] << 18) | (mask_p[54] << 16)
4896                 | (mask_p[53] << 14) | (mask_p[52] << 12)
4897                 | (mask_p[51] << 10) | (mask_p[50] << 8)
4898                 | (mask_p[49] << 6) | (mask_p[48] << 4)
4899                 | (mask_p[47] << 2) | (mask_p[46] << 0);
4900         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4901         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4902 }
4903
4904 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4905                                    struct hal_channel *chan)
4906 {
4907         int bb_spur = AR_NO_SPUR;
4908         int bin, cur_bin;
4909         int spur_freq_sd;
4910         int spur_delta_phase;
4911         int denominator;
4912         int upper, lower, cur_vit_mask;
4913         int tmp, new;
4914         int i;
4915         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4916                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4917         };
4918         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4919                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4920         };
4921         int inc[4] = { 0, 100, 0, 0 };
4922
4923         int8_t mask_m[123];
4924         int8_t mask_p[123];
4925         int8_t mask_amt;
4926         int tmp_mask;
4927         int cur_bb_spur;
4928         enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
4929
4930         memset(&mask_m, 0, sizeof(int8_t) * 123);
4931         memset(&mask_p, 0, sizeof(int8_t) * 123);
4932
4933         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4934                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4935                 if (AR_NO_SPUR == cur_bb_spur)
4936                         break;
4937                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4938                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4939                         bb_spur = cur_bb_spur;
4940                         break;
4941                 }
4942         }
4943
4944         if (AR_NO_SPUR == bb_spur)
4945                 return;
4946
4947         bin = bb_spur * 32;
4948
4949         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4950         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4951                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4952                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4953                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4954
4955         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4956
4957         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4958                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4959                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4960                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4961                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4962         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4963
4964         spur_delta_phase = ((bb_spur * 524288) / 100) &
4965                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4966
4967         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4968         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4969
4970         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4971                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4972                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4973         REG_WRITE(ah, AR_PHY_TIMING11, new);
4974
4975         cur_bin = -6000;
4976         upper = bin + 100;
4977         lower = bin - 100;
4978
4979         for (i = 0; i < 4; i++) {
4980                 int pilot_mask = 0;
4981                 int chan_mask = 0;
4982                 int bp = 0;
4983                 for (bp = 0; bp < 30; bp++) {
4984                         if ((cur_bin > lower) && (cur_bin < upper)) {
4985                                 pilot_mask = pilot_mask | 0x1 << bp;
4986                                 chan_mask = chan_mask | 0x1 << bp;
4987                         }
4988                         cur_bin += 100;
4989                 }
4990                 cur_bin += inc[i];
4991                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4992                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4993         }
4994
4995         cur_vit_mask = 6100;
4996         upper = bin + 120;
4997         lower = bin - 120;
4998
4999         for (i = 0; i < 123; i++) {
5000                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
5001                         if ((abs(cur_vit_mask - bin)) < 75)
5002                                 mask_amt = 1;
5003                         else
5004                                 mask_amt = 0;
5005                         if (cur_vit_mask < 0)
5006                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5007                         else
5008                                 mask_p[cur_vit_mask / 100] = mask_amt;
5009                 }
5010                 cur_vit_mask -= 100;
5011         }
5012
5013         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5014                 | (mask_m[48] << 26) | (mask_m[49] << 24)
5015                 | (mask_m[50] << 22) | (mask_m[51] << 20)
5016                 | (mask_m[52] << 18) | (mask_m[53] << 16)
5017                 | (mask_m[54] << 14) | (mask_m[55] << 12)
5018                 | (mask_m[56] << 10) | (mask_m[57] << 8)
5019                 | (mask_m[58] << 6) | (mask_m[59] << 4)
5020                 | (mask_m[60] << 2) | (mask_m[61] << 0);
5021         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5022         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5023
5024         tmp_mask = (mask_m[31] << 28)
5025                 | (mask_m[32] << 26) | (mask_m[33] << 24)
5026                 | (mask_m[34] << 22) | (mask_m[35] << 20)
5027                 | (mask_m[36] << 18) | (mask_m[37] << 16)
5028                 | (mask_m[48] << 14) | (mask_m[39] << 12)
5029                 | (mask_m[40] << 10) | (mask_m[41] << 8)
5030                 | (mask_m[42] << 6) | (mask_m[43] << 4)
5031                 | (mask_m[44] << 2) | (mask_m[45] << 0);
5032         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5033         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5034
5035         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5036                 | (mask_m[18] << 26) | (mask_m[18] << 24)
5037                 | (mask_m[20] << 22) | (mask_m[20] << 20)
5038                 | (mask_m[22] << 18) | (mask_m[22] << 16)
5039                 | (mask_m[24] << 14) | (mask_m[24] << 12)
5040                 | (mask_m[25] << 10) | (mask_m[26] << 8)
5041                 | (mask_m[27] << 6) | (mask_m[28] << 4)
5042                 | (mask_m[29] << 2) | (mask_m[30] << 0);
5043         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5044         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5045
5046         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5047                 | (mask_m[2] << 26) | (mask_m[3] << 24)
5048                 | (mask_m[4] << 22) | (mask_m[5] << 20)
5049                 | (mask_m[6] << 18) | (mask_m[7] << 16)
5050                 | (mask_m[8] << 14) | (mask_m[9] << 12)
5051                 | (mask_m[10] << 10) | (mask_m[11] << 8)
5052                 | (mask_m[12] << 6) | (mask_m[13] << 4)
5053                 | (mask_m[14] << 2) | (mask_m[15] << 0);
5054         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5055         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5056
5057         tmp_mask = (mask_p[15] << 28)
5058                 | (mask_p[14] << 26) | (mask_p[13] << 24)
5059                 | (mask_p[12] << 22) | (mask_p[11] << 20)
5060                 | (mask_p[10] << 18) | (mask_p[9] << 16)
5061                 | (mask_p[8] << 14) | (mask_p[7] << 12)
5062                 | (mask_p[6] << 10) | (mask_p[5] << 8)
5063                 | (mask_p[4] << 6) | (mask_p[3] << 4)
5064                 | (mask_p[2] << 2) | (mask_p[1] << 0);
5065         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5066         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5067
5068         tmp_mask = (mask_p[30] << 28)
5069                 | (mask_p[29] << 26) | (mask_p[28] << 24)
5070                 | (mask_p[27] << 22) | (mask_p[26] << 20)
5071                 | (mask_p[25] << 18) | (mask_p[24] << 16)
5072                 | (mask_p[23] << 14) | (mask_p[22] << 12)
5073                 | (mask_p[21] << 10) | (mask_p[20] << 8)
5074                 | (mask_p[19] << 6) | (mask_p[18] << 4)
5075                 | (mask_p[17] << 2) | (mask_p[16] << 0);
5076         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5077         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5078
5079         tmp_mask = (mask_p[45] << 28)
5080                 | (mask_p[44] << 26) | (mask_p[43] << 24)
5081                 | (mask_p[42] << 22) | (mask_p[41] << 20)
5082                 | (mask_p[40] << 18) | (mask_p[39] << 16)
5083                 | (mask_p[38] << 14) | (mask_p[37] << 12)
5084                 | (mask_p[36] << 10) | (mask_p[35] << 8)
5085                 | (mask_p[34] << 6) | (mask_p[33] << 4)
5086                 | (mask_p[32] << 2) | (mask_p[31] << 0);
5087         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5088         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5089
5090         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5091                 | (mask_p[59] << 26) | (mask_p[58] << 24)
5092                 | (mask_p[57] << 22) | (mask_p[56] << 20)
5093                 | (mask_p[55] << 18) | (mask_p[54] << 16)
5094                 | (mask_p[53] << 14) | (mask_p[52] << 12)
5095                 | (mask_p[51] << 10) | (mask_p[50] << 8)
5096                 | (mask_p[49] << 6) | (mask_p[48] << 4)
5097                 | (mask_p[47] << 2) | (mask_p[46] << 0);
5098         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5099         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5100 }
5101
5102 static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5103 {
5104         struct ath_hal_5416 *ahp = AH5416(ah);
5105         int rx_chainmask, tx_chainmask;
5106
5107         rx_chainmask = ahp->ah_rxchainmask;
5108         tx_chainmask = ahp->ah_txchainmask;
5109
5110         switch (rx_chainmask) {
5111         case 0x5:
5112                 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5113                                AR_PHY_SWAP_ALT_CHAIN);
5114         case 0x3:
5115                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5116                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5117                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5118                         break;
5119                 }
5120         case 0x1:
5121         case 0x2:
5122                 if (!AR_SREV_9280(ah))
5123                         break;
5124         case 0x7:
5125                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5126                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5127                 break;
5128         default:
5129                 break;
5130         }
5131
5132         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5133         if (tx_chainmask == 0x5) {
5134                 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5135                                AR_PHY_SWAP_ALT_CHAIN);
5136         }
5137         if (AR_SREV_9100(ah))
5138                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5139                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5140 }
5141
5142 static void ath9k_hw_set_addac(struct ath_hal *ah,
5143                                struct hal_channel_internal *chan)
5144 {
5145         struct modal_eep_header *pModal;
5146         struct ath_hal_5416 *ahp = AH5416(ah);
5147         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5148         u_int8_t biaslevel;
5149
5150         if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5151                 return;
5152
5153         if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5154                 return;
5155
5156         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5157
5158         if (pModal->xpaBiasLvl != 0xff) {
5159                 biaslevel = pModal->xpaBiasLvl;
5160         } else {
5161
5162                 u_int16_t resetFreqBin, freqBin, freqCount = 0;
5163                 struct chan_centers centers;
5164
5165                 ath9k_hw_get_channel_centers(ah, chan, &centers);
5166
5167                 resetFreqBin =
5168                         FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5169                 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5170                 biaslevel = (u_int8_t) (pModal->xpaBiasLvlFreq[0] >> 14);
5171
5172                 freqCount++;
5173
5174                 while (freqCount < 3) {
5175                         if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5176                                 break;
5177
5178                         freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5179                         if (resetFreqBin >= freqBin) {
5180                                 biaslevel =
5181                                         (u_int8_t) (pModal->
5182                                                     xpaBiasLvlFreq[freqCount]
5183                                                     >> 14);
5184                         } else {
5185                                 break;
5186                         }
5187                         freqCount++;
5188                 }
5189         }
5190
5191         if (IS_CHAN_2GHZ(chan)) {
5192                 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5193                         (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5194                         << 3;
5195         } else {
5196                 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5197                         (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5198                         << 6;
5199         }
5200 }
5201
5202 static u_int ath9k_hw_mac_usec(struct ath_hal *ah, u_int clks)
5203 {
5204         const struct hal_channel *c =
5205                 (const struct hal_channel *) ah->ah_curchan;
5206
5207         if (c != NULL)
5208                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
5209         else
5210                 return clks / CLOCK_RATE[WIRELESS_MODE_11b];
5211 }
5212
5213 static u_int ath9k_hw_mac_to_usec(struct ath_hal *ah, u_int clks)
5214 {
5215         struct hal_channel_internal *chan = ah->ah_curchan;
5216
5217         if (chan && IS_CHAN_HT40(chan))
5218                 return ath9k_hw_mac_usec(ah, clks) / 2;
5219         else
5220                 return ath9k_hw_mac_usec(ah, clks);
5221 }
5222
5223 static u_int ath9k_hw_mac_clks(struct ath_hal *ah, u_int usecs)
5224 {
5225         const struct hal_channel *c =
5226                 (const struct hal_channel *) ah->ah_curchan;
5227
5228         if (c != NULL)
5229                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
5230         else
5231                 return usecs * CLOCK_RATE[WIRELESS_MODE_11b];
5232 }
5233
5234 static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
5235 {
5236         struct hal_channel_internal *chan = ah->ah_curchan;
5237
5238         if (chan && IS_CHAN_HT40(chan))
5239                 return ath9k_hw_mac_clks(ah, usecs) * 2;
5240         else
5241                 return ath9k_hw_mac_clks(ah, usecs);
5242 }
5243
5244 static enum hal_bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
5245 {
5246         struct ath_hal_5416 *ahp = AH5416(ah);
5247
5248         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5249                 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad ack timeout %u\n",
5250                          __func__, us);
5251                 ahp->ah_acktimeout = (u_int) -1;
5252                 return AH_FALSE;
5253         } else {
5254                 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
5255                                  AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5256                 ahp->ah_acktimeout = us;
5257                 return AH_TRUE;
5258         }
5259 }
5260
5261 static enum hal_bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
5262 {
5263         struct ath_hal_5416 *ahp = AH5416(ah);
5264
5265         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5266                 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad cts timeout %u\n",
5267                          __func__, us);
5268                 ahp->ah_ctstimeout = (u_int) -1;
5269                 return AH_FALSE;
5270         } else {
5271                 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
5272                                  AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5273                 ahp->ah_ctstimeout = us;
5274                 return AH_TRUE;
5275         }
5276 }
5277 static enum hal_bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5278                                                    u_int tu)
5279 {
5280         struct ath_hal_5416 *ahp = AH5416(ah);
5281
5282         if (tu > 0xFFFF) {
5283                 HDPRINTF(ah, HAL_DBG_TX, "%s: bad global tx timeout %u\n",
5284                          __func__, tu);
5285                 ahp->ah_globaltxtimeout = (u_int) -1;
5286                 return AH_FALSE;
5287         } else {
5288                 OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5289                 ahp->ah_globaltxtimeout = tu;
5290                 return AH_TRUE;
5291         }
5292 }
5293
5294 enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
5295 {
5296         struct ath_hal_5416 *ahp = AH5416(ah);
5297
5298         if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5299                 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad slot time %u\n",
5300                          __func__, us);
5301                 ahp->ah_slottime = (u_int) -1;
5302                 return AH_FALSE;
5303         } else {
5304                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5305                 ahp->ah_slottime = us;
5306                 return AH_TRUE;
5307         }
5308 }
5309
5310 static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
5311 {
5312         struct ath_hal_5416 *ahp = AH5416(ah);
5313
5314         HDPRINTF(ah, HAL_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5315                  __func__, ahp->ah_miscMode);
5316         if (ahp->ah_miscMode != 0)
5317                 REG_WRITE(ah, AR_PCU_MISC,
5318                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5319         if (ahp->ah_slottime != (u_int) -1)
5320                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5321         if (ahp->ah_acktimeout != (u_int) -1)
5322                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5323         if (ahp->ah_ctstimeout != (u_int) -1)
5324                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5325         if (ahp->ah_globaltxtimeout != (u_int) -1)
5326                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5327 }
5328
5329 static inline enum hal_status
5330 ath9k_hw_process_ini(struct ath_hal *ah,
5331                      struct hal_channel *chan,
5332                      struct hal_channel_internal *ichan,
5333                      enum hal_ht_macmode macmode)
5334 {
5335         int i, regWrites = 0;
5336         struct ath_hal_5416 *ahp = AH5416(ah);
5337         u_int modesIndex, freqIndex;
5338         enum hal_status status;
5339
5340         switch (chan->channelFlags & CHANNEL_ALL) {
5341         case CHANNEL_A:
5342         case CHANNEL_A_HT20:
5343                 modesIndex = 1;
5344                 freqIndex = 1;
5345                 break;
5346         case CHANNEL_A_HT40PLUS:
5347         case CHANNEL_A_HT40MINUS:
5348                 modesIndex = 2;
5349                 freqIndex = 1;
5350                 break;
5351         case CHANNEL_PUREG:
5352         case CHANNEL_G_HT20:
5353         case CHANNEL_B:
5354                 modesIndex = 4;
5355                 freqIndex = 2;
5356                 break;
5357         case CHANNEL_G_HT40PLUS:
5358         case CHANNEL_G_HT40MINUS:
5359                 modesIndex = 3;
5360                 freqIndex = 2;
5361                 break;
5362
5363         default:
5364                 return HAL_EINVAL;
5365         }
5366
5367         REG_WRITE(ah, AR_PHY(0), 0x00000007);
5368
5369         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5370
5371         ath9k_hw_set_addac(ah, ichan);
5372
5373         if (AR_SREV_5416_V22_OR_LATER(ah)) {
5374                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5375         } else {
5376                 struct ar5416IniArray temp;
5377                 u_int32_t addacSize =
5378                         sizeof(u_int32_t) * ahp->ah_iniAddac.ia_rows *
5379                         ahp->ah_iniAddac.ia_columns;
5380
5381                 memcpy(ahp->ah_addac5416_21,
5382                        ahp->ah_iniAddac.ia_array, addacSize);
5383
5384                 (ahp->ah_addac5416_21)[31 *
5385                                        ahp->ah_iniAddac.ia_columns + 1] = 0;
5386
5387                 temp.ia_array = ahp->ah_addac5416_21;
5388                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5389                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5390                 REG_WRITE_ARRAY(&temp, 1, regWrites);
5391         }
5392         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5393
5394         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5395                 u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
5396                 u_int32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5397
5398 #ifdef CONFIG_SLOW_ANT_DIV
5399                 if (ah->ah_devid == AR9280_DEVID_PCI)
5400                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5401                                                  val);
5402 #endif
5403
5404                 REG_WRITE(ah, reg, val);
5405
5406                 if (reg >= 0x7800 && reg < 0x78a0
5407                     && ah->ah_config.ath_hal_analogShiftReg) {
5408                         udelay(100);
5409                 }
5410
5411                 DO_DELAY(regWrites);
5412         }
5413
5414         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5415                 u_int32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5416                 u_int32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
5417
5418                 REG_WRITE(ah, reg, val);
5419
5420                 if (reg >= 0x7800 && reg < 0x78a0
5421                     && ah->ah_config.ath_hal_analogShiftReg) {
5422                         udelay(100);
5423                 }
5424
5425                 DO_DELAY(regWrites);
5426         }
5427
5428         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5429
5430         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5431                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5432                                 regWrites);
5433         }
5434
5435         ath9k_hw_override_ini(ah, chan);
5436         ath9k_hw_set_regs(ah, chan, macmode);
5437         ath9k_hw_init_chain_masks(ah);
5438
5439         status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
5440                                       ath9k_regd_get_ctl(ah, chan),
5441                                       ath9k_regd_get_antenna_allowed(ah,
5442                                                                      chan),
5443                                       ichan->maxRegTxPower * 2,
5444                                       min((u_int32_t) MAX_RATE_POWER,
5445                                           (u_int32_t) ah->ah_powerLimit));
5446         if (status != HAL_OK) {
5447                 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
5448                          "%s: error init'ing transmit power\n", __func__);
5449                 return HAL_EIO;
5450         }
5451
5452         if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
5453                 HDPRINTF(ah, HAL_DBG_REG_IO,
5454                          "%s: ar5416SetRfRegs failed\n", __func__);
5455                 return HAL_EIO;
5456         }
5457
5458         return HAL_OK;
5459 }
5460
5461 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
5462                                               struct hal_cal_list *currCal)
5463 {
5464         OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5465                          AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5466                          currCal->calData->calCountMax);
5467
5468         switch (currCal->calData->calType) {
5469         case IQ_MISMATCH_CAL:
5470                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5471                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5472                          "%s: starting IQ Mismatch Calibration\n",
5473                          __func__);
5474                 break;
5475         case ADC_GAIN_CAL:
5476                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5477                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5478                          "%s: starting ADC Gain Calibration\n", __func__);
5479                 break;
5480         case ADC_DC_CAL:
5481                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5482                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5483                          "%s: starting ADC DC Calibration\n", __func__);
5484                 break;
5485         case ADC_DC_INIT_CAL:
5486                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5487                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5488                          "%s: starting Init ADC DC Calibration\n",
5489                          __func__);
5490                 break;
5491         }
5492
5493         OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5494                        AR_PHY_TIMING_CTRL4_DO_CAL);
5495 }
5496
5497 static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
5498                                               struct hal_cal_list *currCal)
5499 {
5500         struct ath_hal_5416 *ahp = AH5416(ah);
5501         int i;
5502
5503         ath9k_hw_setup_calibration(ah, currCal);
5504
5505         currCal->calState = CAL_RUNNING;
5506
5507         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5508                 ahp->ah_Meas0.sign[i] = 0;
5509                 ahp->ah_Meas1.sign[i] = 0;
5510                 ahp->ah_Meas2.sign[i] = 0;
5511                 ahp->ah_Meas3.sign[i] = 0;
5512         }
5513
5514         ahp->ah_CalSamples = 0;
5515 }
5516
5517 static inline void
5518 ath9k_hw_per_calibration(struct ath_hal *ah,
5519                          struct hal_channel_internal *ichan,
5520                          u_int8_t rxchainmask,
5521                          struct hal_cal_list *currCal,
5522                          enum hal_bool *isCalDone)
5523 {
5524         struct ath_hal_5416 *ahp = AH5416(ah);
5525
5526         *isCalDone = AH_FALSE;
5527
5528         if (currCal->calState == CAL_RUNNING) {
5529                 if (!(REG_READ(ah,
5530                                AR_PHY_TIMING_CTRL4(0)) &
5531                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
5532
5533                         currCal->calData->calCollect(ah);
5534
5535                         ahp->ah_CalSamples++;
5536
5537                         if (ahp->ah_CalSamples >=
5538                             currCal->calData->calNumSamples) {
5539                                 int i, numChains = 0;
5540                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5541                                         if (rxchainmask & (1 << i))
5542                                                 numChains++;
5543                                 }
5544
5545                                 currCal->calData->calPostProc(ah,
5546                                                               numChains);
5547
5548                                 ichan->CalValid |=
5549                                         currCal->calData->calType;
5550                                 currCal->calState = CAL_DONE;
5551                                 *isCalDone = AH_TRUE;
5552                         } else {
5553                                 ath9k_hw_setup_calibration(ah, currCal);
5554                         }
5555                 }
5556         } else if (!(ichan->CalValid & currCal->calData->calType)) {
5557                 ath9k_hw_reset_calibration(ah, currCal);
5558         }
5559 }
5560
5561 static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5562                                                    int init_cal_count)
5563 {
5564         struct ath_hal_5416 *ahp = AH5416(ah);
5565         struct hal_channel_internal ichan;
5566         enum hal_bool isCalDone;
5567         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5568         const struct hal_percal_data *calData = currCal->calData;
5569         int i;
5570
5571         if (currCal == NULL)
5572                 return AH_FALSE;
5573
5574         ichan.CalValid = 0;
5575
5576         for (i = 0; i < init_cal_count; i++) {
5577                 ath9k_hw_reset_calibration(ah, currCal);
5578
5579                 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5580                                    AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5581                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
5582                                  "%s: Cal %d failed to complete in 100ms.\n",
5583                                  __func__, calData->calType);
5584
5585                         ahp->ah_cal_list = ahp->ah_cal_list_last =
5586                                 ahp->ah_cal_list_curr = NULL;
5587                         return AH_FALSE;
5588                 }
5589
5590                 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5591                                          currCal, &isCalDone);
5592                 if (isCalDone == AH_FALSE) {
5593                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
5594                                  "%s: Not able to run Init Cal %d.\n",
5595                                  __func__, calData->calType);
5596                 }
5597                 if (currCal->calNext) {
5598                         currCal = currCal->calNext;
5599                         calData = currCal->calData;
5600                 }
5601         }
5602
5603         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5604         return AH_TRUE;
5605 }
5606
5607 static inline enum hal_bool
5608 ath9k_hw_channel_change(struct ath_hal *ah,
5609                         struct hal_channel *chan,
5610                         struct hal_channel_internal *ichan,
5611                         enum hal_ht_macmode macmode)
5612 {
5613         u_int32_t synthDelay, qnum;
5614         struct ath_hal_5416 *ahp = AH5416(ah);
5615
5616         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5617                 if (ath9k_hw_numtxpending(ah, qnum)) {
5618                         HDPRINTF(ah, HAL_DBG_QUEUE,
5619                                  "%s: Transmit frames pending on queue %d\n",
5620                                  __func__, qnum);
5621                         return AH_FALSE;
5622                 }
5623         }
5624
5625         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5626         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5627                            AR_PHY_RFBUS_GRANT_EN)) {
5628                 HDPRINTF(ah, HAL_DBG_PHY_IO,
5629                          "%s: Could not kill baseband RX\n", __func__);
5630                 return AH_FALSE;
5631         }
5632
5633         ath9k_hw_set_regs(ah, chan, macmode);
5634
5635         if (AR_SREV_9280_10_OR_LATER(ah)) {
5636                 if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
5637                         HDPRINTF(ah, HAL_DBG_CHANNEL,
5638                                  "%s: failed to set channel\n", __func__);
5639                         return AH_FALSE;
5640                 }
5641         } else {
5642                 if (!(ath9k_hw_set_channel(ah, ichan))) {
5643                         HDPRINTF(ah, HAL_DBG_CHANNEL,
5644                                  "%s: failed to set channel\n", __func__);
5645                         return AH_FALSE;
5646                 }
5647         }
5648
5649         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
5650                                  ath9k_regd_get_ctl(ah, chan),
5651                                  ath9k_regd_get_antenna_allowed(ah, chan),
5652                                  ichan->maxRegTxPower * 2,
5653                                  min((u_int32_t) MAX_RATE_POWER,
5654                                      (u_int32_t) ah->ah_powerLimit))
5655             != HAL_OK) {
5656                 HDPRINTF(ah, HAL_DBG_EEPROM,
5657                          "%s: error init'ing transmit power\n", __func__);
5658                 return AH_FALSE;
5659         }
5660
5661         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5662         if (IS_CHAN_CCK(chan))
5663                 synthDelay = (4 * synthDelay) / 22;
5664         else
5665                 synthDelay /= 10;
5666
5667         udelay(synthDelay + BASE_ACTIVATE_DELAY);
5668
5669         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5670
5671         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5672                 ath9k_hw_set_delta_slope(ah, ichan);
5673
5674         if (AR_SREV_9280_10_OR_LATER(ah))
5675                 ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
5676         else
5677                 ath9k_hw_spur_mitigate(ah, chan);
5678
5679         if (!ichan->oneTimeCalsDone)
5680                 ichan->oneTimeCalsDone = AH_TRUE;
5681
5682         return AH_TRUE;
5683 }
5684
5685 static enum hal_bool ath9k_hw_chip_reset(struct ath_hal *ah,
5686                                          struct hal_channel *chan)
5687 {
5688         struct ath_hal_5416 *ahp = AH5416(ah);
5689
5690         if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
5691                 return AH_FALSE;
5692
5693         if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
5694                 return AH_FALSE;
5695
5696         ahp->ah_chipFullSleep = AH_FALSE;
5697
5698         ath9k_hw_init_pll(ah, chan);
5699
5700         ath9k_hw_set_rfmode(ah, chan);
5701
5702         return AH_TRUE;
5703 }
5704
5705 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5706 {
5707         u_int32_t regval;
5708
5709         regval = REG_READ(ah, AR_AHB_MODE);
5710         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5711
5712         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5713         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5714
5715         OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5716
5717         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5718         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5719
5720         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5721
5722         if (AR_SREV_9285(ah)) {
5723                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5724                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5725         } else {
5726                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5727                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5728         }
5729 }
5730
5731 enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5732 {
5733         REG_WRITE(ah, AR_CR, AR_CR_RXD);
5734         if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5735                 HDPRINTF(ah, HAL_DBG_RX, "%s: dma failed to stop in 10ms\n"
5736                          "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5737                          __func__,
5738                          REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5739                 return AH_FALSE;
5740         } else {
5741                 return AH_TRUE;
5742         }
5743 }
5744
5745 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5746 {
5747         OS_REG_CLR_BIT(ah, AR_DIAG_SW,
5748                        (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5749
5750         ath9k_enable_mib_counters(ah);
5751
5752         ath9k_ani_reset(ah);
5753 }
5754
5755 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5756 {
5757         OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5758
5759         ath9k_hw_disable_mib_counters(ah);
5760 }
5761
5762 static enum hal_bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5763                                               struct hal_channel *chan,
5764                                               enum hal_cal_types calType)
5765 {
5766         struct ath_hal_5416 *ahp = AH5416(ah);
5767         enum hal_bool retval = AH_FALSE;
5768
5769         switch (calType & ahp->ah_suppCals) {
5770         case IQ_MISMATCH_CAL:
5771                 if (!IS_CHAN_B(chan))
5772                         retval = AH_TRUE;
5773                 break;
5774         case ADC_GAIN_CAL:
5775         case ADC_DC_CAL:
5776                 if (!IS_CHAN_B(chan)
5777                     && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5778                         retval = AH_TRUE;
5779                 break;
5780         }
5781
5782         return retval;
5783 }
5784
5785 static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
5786                                               struct hal_channel *chan)
5787 {
5788         struct ath_hal_5416 *ahp = AH5416(ah);
5789         struct hal_channel_internal *ichan =
5790                 ath9k_regd_check_channel(ah, chan);
5791
5792         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5793                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5794                   AR_PHY_AGC_CONTROL_CAL);
5795
5796         if (!ath9k_hw_wait
5797             (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5798                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5799                          "%s: offset calibration failed to complete in 1ms; "
5800                          "noisy environment?\n", __func__);
5801                 return AH_FALSE;
5802         }
5803
5804         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5805                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5806                   AR_PHY_AGC_CONTROL_NF);
5807
5808         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5809                 NULL;
5810
5811         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5812                 if (AH_TRUE ==
5813                     ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5814                         INIT_CAL(&ahp->ah_adcGainCalData);
5815                         INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5816                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
5817                                  "%s: enabling ADC Gain Calibration.\n",
5818                                  __func__);
5819                 }
5820                 if (AH_TRUE ==
5821                     ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5822                         INIT_CAL(&ahp->ah_adcDcCalData);
5823                         INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5824                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
5825                                  "%s: enabling ADC DC Calibration.\n",
5826                                  __func__);
5827                 }
5828                 if (AH_TRUE ==
5829                     ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5830                         INIT_CAL(&ahp->ah_iqCalData);
5831                         INSERT_CAL(ahp, &ahp->ah_iqCalData);
5832                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
5833                                  "%s: enabling IQ Calibration.\n",
5834                                  __func__);
5835                 }
5836
5837                 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5838
5839                 if (ahp->ah_cal_list_curr)
5840                         ath9k_hw_reset_calibration(ah,
5841                                                    ahp->ah_cal_list_curr);
5842         }
5843
5844         ichan->CalValid = 0;
5845
5846         return AH_TRUE;
5847 }
5848
5849
5850 enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
5851                              struct hal_channel *chan,
5852                              enum hal_ht_macmode macmode,
5853                              u_int8_t txchainmask, u_int8_t rxchainmask,
5854                              enum hal_ht_extprotspacing extprotspacing,
5855                              enum hal_bool bChannelChange,
5856                              enum hal_status *status)
5857 {
5858 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
5859         u_int32_t saveLedState;
5860         struct ath_hal_5416 *ahp = AH5416(ah);
5861         struct hal_channel_internal *ichan;
5862         struct hal_channel_internal *curchan = ah->ah_curchan;
5863         u_int32_t saveDefAntenna;
5864         u_int32_t macStaId1;
5865         enum hal_status ecode;
5866         int i, rx_chainmask;
5867
5868         ahp->ah_extprotspacing = extprotspacing;
5869         ahp->ah_txchainmask = txchainmask;
5870         ahp->ah_rxchainmask = rxchainmask;
5871
5872         if (AR_SREV_9280(ah)) {
5873                 ahp->ah_txchainmask &= 0x3;
5874                 ahp->ah_rxchainmask &= 0x3;
5875         }
5876
5877         ichan = ath9k_hw_check_chan(ah, chan);
5878         if (ichan == NULL) {
5879                 HDPRINTF(ah, HAL_DBG_CHANNEL,
5880                          "%s: invalid channel %u/0x%x; no mapping\n",
5881                          __func__, chan->channel, chan->channelFlags);
5882                 FAIL(HAL_EINVAL);
5883         }
5884
5885         if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
5886                 return AH_FALSE;
5887
5888         if (curchan)
5889                 ath9k_hw_getnf(ah, curchan);
5890
5891         if (bChannelChange &&
5892             (ahp->ah_chipFullSleep != AH_TRUE) &&
5893             (ah->ah_curchan != NULL) &&
5894             (chan->channel != ah->ah_curchan->channel) &&
5895             ((chan->channelFlags & CHANNEL_ALL) ==
5896              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5897             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5898                                    !IS_CHAN_A_5MHZ_SPACED(ah->
5899                                                           ah_curchan)))) {
5900
5901                 if (ath9k_hw_channel_change(ah, chan, ichan, macmode)) {
5902                         chan->channelFlags = ichan->channelFlags;
5903                         chan->privFlags = ichan->privFlags;
5904
5905                         ath9k_hw_loadnf(ah, ah->ah_curchan);
5906
5907                         ath9k_hw_start_nfcal(ah);
5908
5909                         return AH_TRUE;
5910                 }
5911         }
5912
5913         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5914         if (saveDefAntenna == 0)
5915                 saveDefAntenna = 1;
5916
5917         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5918
5919         saveLedState = REG_READ(ah, AR_CFG_LED) &
5920                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5921                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5922
5923         ath9k_hw_mark_phy_inactive(ah);
5924
5925         if (!ath9k_hw_chip_reset(ah, chan)) {
5926                 HDPRINTF(ah, HAL_DBG_RESET, "%s: chip reset failed\n",
5927                          __func__);
5928                 FAIL(HAL_EIO);
5929         }
5930
5931         if (AR_SREV_9280(ah)) {
5932                 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5933                                AR_GPIO_JTAG_DISABLE);
5934
5935                 if (ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) {
5936                         if (IS_CHAN_5GHZ(chan))
5937                                 ath9k_hw_set_gpio(ah, 9, 0);
5938                         else
5939                                 ath9k_hw_set_gpio(ah, 9, 1);
5940                 }
5941                 ath9k_hw_cfg_output(ah, 9, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
5942         }
5943
5944         ecode = ath9k_hw_process_ini(ah, chan, ichan, macmode);
5945         if (ecode != HAL_OK)
5946                 goto bad;
5947
5948         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5949                 ath9k_hw_set_delta_slope(ah, ichan);
5950
5951         if (AR_SREV_9280_10_OR_LATER(ah))
5952                 ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
5953         else
5954                 ath9k_hw_spur_mitigate(ah, chan);
5955
5956         if (!ath9k_hw_eeprom_set_board_values(ah, ichan)) {
5957                 HDPRINTF(ah, HAL_DBG_EEPROM,
5958                          "%s: error setting board options\n", __func__);
5959                 FAIL(HAL_EIO);
5960         }
5961
5962         ath9k_hw_decrease_chain_power(ah, chan);
5963
5964         REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
5965         REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
5966                   | macStaId1
5967                   | AR_STA_ID1_RTS_USE_DEF
5968                   | (ah->ah_config.
5969                      ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0)
5970                   | ahp->ah_staId1Defaults);
5971         ath9k_hw_set_operating_mode(ah, opmode);
5972
5973         REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
5974         REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
5975
5976         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5977
5978         REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
5979         REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
5980                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5981
5982         REG_WRITE(ah, AR_ISR, ~0);
5983
5984         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5985
5986         if (AR_SREV_9280_10_OR_LATER(ah)) {
5987                 if (!(ath9k_hw_ar9280_set_channel(ah, ichan)))
5988                         FAIL(HAL_EIO);
5989         } else {
5990                 if (!(ath9k_hw_set_channel(ah, ichan)))
5991                         FAIL(HAL_EIO);
5992         }
5993
5994         for (i = 0; i < AR_NUM_DCU; i++)
5995                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5996
5997         ahp->ah_intrTxqs = 0;
5998         for (i = 0; i < ah->ah_caps.halTotalQueues; i++)
5999                 ath9k_hw_resettxqueue(ah, i);
6000
6001         ath9k_hw_init_interrupt_masks(ah, opmode);
6002         ath9k_hw_init_qos(ah);
6003
6004         ath9k_hw_init_user_settings(ah);
6005
6006         ah->ah_opmode = opmode;
6007
6008         REG_WRITE(ah, AR_STA_ID1,
6009                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
6010
6011         ath9k_hw_set_dma(ah);
6012
6013         REG_WRITE(ah, AR_OBS, 8);
6014
6015         if (ahp->ah_intrMitigation) {
6016
6017                 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
6018                 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
6019         }
6020
6021         ath9k_hw_init_bb(ah, chan);
6022
6023         if (!ath9k_hw_init_cal(ah, chan))
6024                 FAIL(HAL_ESELFTEST);
6025
6026         rx_chainmask = ahp->ah_rxchainmask;
6027         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
6028                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
6029                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
6030         }
6031
6032         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
6033
6034         if (AR_SREV_9100(ah)) {
6035                 u_int32_t mask;
6036                 mask = REG_READ(ah, AR_CFG);
6037                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6038                         HDPRINTF(ah, HAL_DBG_RESET,
6039                                  "%s CFG Byte Swap Set 0x%x\n", __func__,
6040                                  mask);
6041                 } else {
6042                         mask =
6043                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6044                         REG_WRITE(ah, AR_CFG, mask);
6045                         HDPRINTF(ah, HAL_DBG_RESET,
6046                                  "%s Setting CFG 0x%x\n", __func__,
6047                                  REG_READ(ah, AR_CFG));
6048                 }
6049         } else {
6050 #ifdef __BIG_ENDIAN
6051                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6052 #endif
6053         }
6054         chan->channelFlags = ichan->channelFlags;
6055         chan->privFlags = ichan->privFlags;
6056         return AH_TRUE;
6057 bad:
6058         if (status)
6059                 *status = ecode;
6060         return AH_FALSE;
6061 #undef FAIL
6062 }
6063
6064 enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah)
6065 {
6066         return ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM);
6067 }
6068
6069 enum hal_bool ath9k_hw_disable(struct ath_hal *ah)
6070 {
6071         if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
6072                 return AH_FALSE;
6073
6074         return ath9k_hw_set_reset_reg(ah, HAL_RESET_COLD);
6075 }
6076
6077 enum hal_bool
6078 ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
6079                    u_int8_t rxchainmask, enum hal_bool longcal,
6080                    enum hal_bool *isCalDone)
6081 {
6082         struct ath_hal_5416 *ahp = AH5416(ah);
6083         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6084         struct hal_channel_internal *ichan =
6085                 ath9k_regd_check_channel(ah, chan);
6086
6087         *isCalDone = AH_TRUE;
6088
6089         if (ichan == NULL) {
6090                 HDPRINTF(ah, HAL_DBG_CHANNEL,
6091                          "%s: invalid channel %u/0x%x; no mapping\n",
6092                          __func__, chan->channel, chan->channelFlags);
6093                 return AH_FALSE;
6094         }
6095
6096         if (currCal &&
6097             (currCal->calState == CAL_RUNNING ||
6098              currCal->calState == CAL_WAITING)) {
6099                 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6100                                          isCalDone);
6101                 if (*isCalDone == AH_TRUE) {
6102                         ahp->ah_cal_list_curr = currCal = currCal->calNext;
6103
6104                         if (currCal->calState == CAL_WAITING) {
6105                                 *isCalDone = AH_FALSE;
6106                                 ath9k_hw_reset_calibration(ah, currCal);
6107                         }
6108                 }
6109         }
6110
6111         if (longcal) {
6112                 ath9k_hw_getnf(ah, ichan);
6113                 ath9k_hw_loadnf(ah, ah->ah_curchan);
6114                 ath9k_hw_start_nfcal(ah);
6115
6116                 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6117
6118                         chan->channelFlags |= CHANNEL_CW_INT;
6119                         ichan->channelFlags &= ~CHANNEL_CW_INT;
6120                 }
6121         }
6122
6123         return AH_TRUE;
6124 }
6125
6126 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6127 {
6128         struct ath_hal_5416 *ahp = AH5416(ah);
6129         int i;
6130
6131         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6132                 ahp->ah_totalPowerMeasI[i] +=
6133                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6134                 ahp->ah_totalPowerMeasQ[i] +=
6135                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6136                 ahp->ah_totalIqCorrMeas[i] +=
6137                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6138                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6139                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6140                          ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6141                          ahp->ah_totalPowerMeasQ[i],
6142                          ahp->ah_totalIqCorrMeas[i]);
6143         }
6144 }
6145
6146 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6147 {
6148         struct ath_hal_5416 *ahp = AH5416(ah);
6149         int i;
6150
6151         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6152                 ahp->ah_totalAdcIOddPhase[i] +=
6153                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6154                 ahp->ah_totalAdcIEvenPhase[i] +=
6155                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6156                 ahp->ah_totalAdcQOddPhase[i] +=
6157                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6158                 ahp->ah_totalAdcQEvenPhase[i] +=
6159                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6160
6161                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6162                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6163                         "oddq=0x%08x; evenq=0x%08x;\n",
6164                          ahp->ah_CalSamples, i,
6165                          ahp->ah_totalAdcIOddPhase[i],
6166                          ahp->ah_totalAdcIEvenPhase[i],
6167                          ahp->ah_totalAdcQOddPhase[i],
6168                          ahp->ah_totalAdcQEvenPhase[i]);
6169         }
6170 }
6171
6172 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6173 {
6174         struct ath_hal_5416 *ahp = AH5416(ah);
6175         int i;
6176
6177         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6178                 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6179                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6180                 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6181                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6182                 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6183                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6184                 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6185                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6186
6187                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6188                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6189                         "oddq=0x%08x; evenq=0x%08x;\n",
6190                          ahp->ah_CalSamples, i,
6191                          ahp->ah_totalAdcDcOffsetIOddPhase[i],
6192                          ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6193                          ahp->ah_totalAdcDcOffsetQOddPhase[i],
6194                          ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6195         }
6196 }
6197
6198 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
6199 {
6200         struct ath_hal_5416 *ahp = AH5416(ah);
6201         u_int32_t powerMeasQ, powerMeasI, iqCorrMeas;
6202         u_int32_t qCoffDenom, iCoffDenom;
6203         int32_t qCoff, iCoff;
6204         int iqCorrNeg, i;
6205
6206         for (i = 0; i < numChains; i++) {
6207                 powerMeasI = ahp->ah_totalPowerMeasI[i];
6208                 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6209                 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6210
6211                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6212                          "Starting IQ Cal and Correction for Chain %d\n",
6213                          i);
6214
6215                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6216                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6217                          i, ahp->ah_totalIqCorrMeas[i]);
6218
6219                 iqCorrNeg = 0;
6220
6221
6222                 if (iqCorrMeas > 0x80000000) {
6223                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6224                         iqCorrNeg = 1;
6225                 }
6226
6227                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6228                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6229                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6230                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6231                 HDPRINTF(ah, HAL_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6232                          iqCorrNeg);
6233
6234                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6235                 qCoffDenom = powerMeasQ / 64;
6236
6237                 if (powerMeasQ != 0) {
6238
6239                         iCoff = iqCorrMeas / iCoffDenom;
6240                         qCoff = powerMeasI / qCoffDenom - 64;
6241                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6242                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
6243                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6244                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
6245
6246
6247                         iCoff = iCoff & 0x3f;
6248                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6249                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6250                         if (iqCorrNeg == 0x0)
6251                                 iCoff = 0x40 - iCoff;
6252
6253                         if (qCoff > 15)
6254                                 qCoff = 15;
6255                         else if (qCoff <= -16)
6256                                 qCoff = 16;
6257
6258                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6259                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
6260                                  i, iCoff, qCoff);
6261
6262                         OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6263                                          AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6264                                          iCoff);
6265                         OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6266                                          AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6267                                          qCoff);
6268                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6269                                  "IQ Cal and Correction done for Chain %d\n",
6270                                  i);
6271                 }
6272         }
6273
6274         OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6275                        AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6276 }
6277
6278 static void
6279 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
6280 {
6281         struct ath_hal_5416 *ahp = AH5416(ah);
6282         u_int32_t iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6283                 qEvenMeasOffset;
6284         u_int32_t qGainMismatch, iGainMismatch, val, i;
6285
6286         for (i = 0; i < numChains; i++) {
6287                 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6288                 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6289                 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6290                 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6291
6292                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6293                          "Starting ADC Gain Cal for Chain %d\n", i);
6294
6295                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6296                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6297                          iOddMeasOffset);
6298                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6299                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6300                          iEvenMeasOffset);
6301                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6302                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6303                          qOddMeasOffset);
6304                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6305                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6306                          qEvenMeasOffset);
6307
6308                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6309                         iGainMismatch =
6310                                 ((iEvenMeasOffset * 32) /
6311                                  iOddMeasOffset) & 0x3f;
6312                         qGainMismatch =
6313                                 ((qOddMeasOffset * 32) /
6314                                  qEvenMeasOffset) & 0x3f;
6315
6316                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6317                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
6318                                  iGainMismatch);
6319                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6320                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
6321                                  qGainMismatch);
6322
6323                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6324                         val &= 0xfffff000;
6325                         val |= (qGainMismatch) | (iGainMismatch << 6);
6326                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6327
6328                         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6329                                  "ADC Gain Cal done for Chain %d\n", i);
6330                 }
6331         }
6332
6333         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6334                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6335                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6336 }
6337
6338 static void
6339 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
6340 {
6341         struct ath_hal_5416 *ahp = AH5416(ah);
6342         u_int32_t iOddMeasOffset, iEvenMeasOffset, val, i;
6343         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6344         const struct hal_percal_data *calData =
6345                 ahp->ah_cal_list_curr->calData;
6346         u_int32_t numSamples =
6347                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6348
6349         for (i = 0; i < numChains; i++) {
6350                 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6351                 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6352                 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6353                 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6354
6355                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6356                          "Starting ADC DC Offset Cal for Chain %d\n", i);
6357
6358                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6359                          "Chn %d pwr_meas_odd_i = %d\n", i,
6360                          iOddMeasOffset);
6361                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6362                          "Chn %d pwr_meas_even_i = %d\n", i,
6363                          iEvenMeasOffset);
6364                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6365                          "Chn %d pwr_meas_odd_q = %d\n", i,
6366                          qOddMeasOffset);
6367                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6368                          "Chn %d pwr_meas_even_q = %d\n", i,
6369                          qEvenMeasOffset);
6370
6371                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6372                                numSamples) & 0x1ff;
6373                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6374                                numSamples) & 0x1ff;
6375
6376                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6377                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6378                          iDcMismatch);
6379                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6380                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6381                          qDcMismatch);
6382
6383                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6384                 val &= 0xc0000fff;
6385                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6386                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6387
6388                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6389                          "ADC DC Offset Cal done for Chain %d\n", i);
6390         }
6391
6392         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6393                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6394                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6395 }
6396
6397 enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
6398 {
6399         struct ath_hal_5416 *ahp = AH5416(ah);
6400         struct hal_channel_internal *ichan = ah->ah_curchan;
6401         struct hal_channel *chan = (struct hal_channel *) ichan;
6402
6403         ah->ah_powerLimit = min(limit, (u_int32_t) MAX_RATE_POWER);
6404
6405         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
6406                                  ath9k_regd_get_ctl(ah, chan),
6407                                  ath9k_regd_get_antenna_allowed(ah,
6408                                                                 chan),
6409                                  chan->maxRegTxPower * 2,
6410                                  min((u_int32_t) MAX_RATE_POWER,
6411                                      (u_int32_t) ah->ah_powerLimit))
6412             != HAL_OK)
6413                 return AH_FALSE;
6414
6415         return AH_TRUE;
6416 }
6417
6418 void
6419 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6420                              struct hal_channel_internal *chan,
6421                              struct chan_centers *centers)
6422 {
6423         int8_t extoff;
6424         struct ath_hal_5416 *ahp = AH5416(ah);
6425
6426         if (!IS_CHAN_HT40(chan)) {
6427                 centers->ctl_center = centers->ext_center =
6428                         centers->synth_center = chan->channel;
6429                 return;
6430         }
6431
6432         if (chan->channelFlags & CHANNEL_HT40PLUS) {
6433                 centers->synth_center =
6434                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6435                 extoff = 1;
6436         } else {
6437                 centers->synth_center =
6438                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6439                 extoff = -1;
6440         }
6441
6442         centers->ctl_center = centers->synth_center - (extoff *
6443                 HT40_CHANNEL_CENTER_SHIFT);
6444         centers->ext_center = centers->synth_center + (extoff *
6445                 ((ahp->
6446                 ah_extprotspacing
6447                 ==
6448                 HAL_HT_EXTPROTSPACING_20)
6449                 ?
6450                 HT40_CHANNEL_CENTER_SHIFT
6451                 : 15));
6452
6453 }
6454
6455 void
6456 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
6457                         enum hal_bool *isCalDone)
6458 {
6459         struct ath_hal_5416 *ahp = AH5416(ah);
6460         struct hal_channel_internal *ichan =
6461                 ath9k_regd_check_channel(ah, chan);
6462         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6463
6464         *isCalDone = AH_TRUE;
6465
6466         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6467                 return;
6468
6469         if (currCal == NULL)
6470                 return;
6471
6472         if (ichan == NULL) {
6473                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6474                          "%s: invalid channel %u/0x%x; no mapping\n",
6475                          __func__, chan->channel, chan->channelFlags);
6476                 return;
6477         }
6478
6479
6480         if (currCal->calState != CAL_DONE) {
6481                 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6482                          "%s: Calibration state incorrect, %d\n",
6483                          __func__, currCal->calState);
6484                 return;
6485         }
6486
6487
6488         if (ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType)
6489             == AH_FALSE) {
6490                 return;
6491         }
6492
6493         HDPRINTF(ah, HAL_DBG_CALIBRATE,
6494                  "%s: Resetting Cal %d state for channel %u/0x%x\n",
6495                  __func__, currCal->calData->calType, chan->channel,
6496                  chan->channelFlags);
6497
6498         ichan->CalValid &= ~currCal->calData->calType;
6499         currCal->calState = CAL_WAITING;
6500
6501         *isCalDone = AH_FALSE;
6502 }
6503
6504 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac)
6505 {
6506         struct ath_hal_5416 *ahp = AH5416(ah);
6507
6508         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6509 }
6510
6511 enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
6512 {
6513         struct ath_hal_5416 *ahp = AH5416(ah);
6514
6515         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6516         return AH_TRUE;
6517 }
6518
6519 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
6520 {
6521         struct ath_hal_5416 *ahp = AH5416(ah);
6522
6523         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6524 }
6525
6526 enum hal_bool
6527 ath9k_hw_setbssidmask(struct ath_hal *ah, const u_int8_t *mask)
6528 {
6529         struct ath_hal_5416 *ahp = AH5416(ah);
6530
6531         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6532
6533         REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
6534         REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
6535
6536         return AH_TRUE;
6537 }
6538
6539 #ifdef CONFIG_ATH9K_RFKILL
6540 static void ath9k_enable_rfkill(struct ath_hal *ah)
6541 {
6542         struct ath_hal_5416 *ahp = AH5416(ah);
6543
6544         OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
6545                        AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
6546
6547         OS_REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
6548                        AR_GPIO_INPUT_MUX2_RFSILENT);
6549
6550         ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect);
6551         OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
6552
6553         if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) {
6554
6555                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6556                                        !ahp->ah_gpioBit);
6557         } else {
6558                 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6559                                        ahp->ah_gpioBit);
6560         }
6561 }
6562 #endif
6563
6564 void
6565 ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
6566                        u_int16_t assocId)
6567 {
6568         struct ath_hal_5416 *ahp = AH5416(ah);
6569
6570         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6571         ahp->ah_assocId = assocId;
6572
6573         REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
6574         REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
6575                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6576 }
6577
6578 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah)
6579 {
6580         u_int64_t tsf;
6581
6582         tsf = REG_READ(ah, AR_TSF_U32);
6583         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6584         return tsf;
6585 }
6586
6587 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6588 {
6589         int count;
6590
6591         count = 0;
6592         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6593                 count++;
6594                 if (count > 10) {
6595                         HDPRINTF(ah, HAL_DBG_RESET,
6596                          "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6597                                  __func__);
6598                         break;
6599                 }
6600                 udelay(10);
6601         }
6602         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6603 }
6604
6605 u_int ath9k_hw_getdefantenna(struct ath_hal *ah)
6606 {
6607         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6608 }
6609
6610 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna)
6611 {
6612         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6613 }
6614
6615 enum hal_bool
6616 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6617                           enum hal_ant_setting settings,
6618                           struct hal_channel *chan,
6619                           u_int8_t *tx_chainmask,
6620                           u_int8_t *rx_chainmask,
6621                           u_int8_t *antenna_cfgd)
6622 {
6623         struct ath_hal_5416 *ahp = AH5416(ah);
6624         static u_int8_t tx_chainmask_cfg, rx_chainmask_cfg;
6625
6626         if (AR_SREV_9280(ah)) {
6627                 if (!tx_chainmask_cfg) {
6628
6629                         tx_chainmask_cfg = *tx_chainmask;
6630                         rx_chainmask_cfg = *rx_chainmask;
6631                 }
6632
6633                 switch (settings) {
6634                 case HAL_ANT_FIXED_A:
6635                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6636                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6637                         *antenna_cfgd = AH_TRUE;
6638                         break;
6639                 case HAL_ANT_FIXED_B:
6640                         if (ah->ah_caps.halTxChainMask >
6641                             ATH9K_ANTENNA1_CHAINMASK) {
6642                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6643                         }
6644                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6645                         *antenna_cfgd = AH_TRUE;
6646                         break;
6647                 case HAL_ANT_VARIABLE:
6648                         *tx_chainmask = tx_chainmask_cfg;
6649                         *rx_chainmask = rx_chainmask_cfg;
6650                         *antenna_cfgd = AH_TRUE;
6651                         break;
6652                 default:
6653                         break;
6654                 }
6655         } else {
6656                 ahp->ah_diversityControl = settings;
6657         }
6658
6659         return AH_TRUE;
6660 }
6661
6662 void ath9k_hw_setopmode(struct ath_hal *ah)
6663 {
6664         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6665 }
6666
6667 enum hal_bool
6668 ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
6669                        u_int32_t capability, u_int32_t *result)
6670 {
6671         struct ath_hal_5416 *ahp = AH5416(ah);
6672         const struct hal_capabilities *pCap = &ah->ah_caps;
6673
6674         switch (type) {
6675         case HAL_CAP_CIPHER:
6676                 switch (capability) {
6677                 case HAL_CIPHER_AES_CCM:
6678                 case HAL_CIPHER_AES_OCB:
6679                 case HAL_CIPHER_TKIP:
6680                 case HAL_CIPHER_WEP:
6681                 case HAL_CIPHER_MIC:
6682                 case HAL_CIPHER_CLR:
6683                         return AH_TRUE;
6684                 default:
6685                         return AH_FALSE;
6686                 }
6687         case HAL_CAP_TKIP_MIC:
6688                 switch (capability) {
6689                 case 0:
6690                         return AH_TRUE;
6691                 case 1:
6692                         return (ahp->ah_staId1Defaults &
6693                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? AH_TRUE :
6694                         AH_FALSE;
6695                 }
6696         case HAL_CAP_TKIP_SPLIT:
6697                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6698                         AH_FALSE : AH_TRUE;
6699         case HAL_CAP_WME_TKIPMIC:
6700                 return HAL_OK;
6701         case HAL_CAP_PHYCOUNTERS:
6702                 return ahp->ah_hasHwPhyCounters ? HAL_OK : HAL_ENXIO;
6703         case HAL_CAP_DIVERSITY:
6704                 switch (capability) {
6705                 case 0:
6706                         return AH_TRUE;
6707                 case 1:
6708                         return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6709                                 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6710                                 AH_TRUE : AH_FALSE;
6711                 }
6712                 return AH_FALSE;
6713         case HAL_CAP_PHYDIAG:
6714                 return AH_TRUE;
6715         case HAL_CAP_MCAST_KEYSRCH:
6716                 switch (capability) {
6717                 case 0:
6718                         return AH_TRUE;
6719                 case 1:
6720                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6721                                 return AH_FALSE;
6722                         } else {
6723                                 return (ahp->ah_staId1Defaults &
6724                                         AR_STA_ID1_MCAST_KSRCH) ? AH_TRUE :
6725                                         AH_FALSE;
6726                         }
6727                 }
6728                 return AH_FALSE;
6729         case HAL_CAP_TSF_ADJUST:
6730                 switch (capability) {
6731                 case 0:
6732                         return AH_TRUE;
6733                 case 1:
6734                         return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6735                                 AH_TRUE : AH_FALSE;
6736                 }
6737                 return AH_FALSE;
6738         case HAL_CAP_RFSILENT:
6739                 if (capability == 3)
6740                         return AH_FALSE;
6741         case HAL_CAP_ANT_CFG_2GHZ:
6742                 *result = pCap->halNumAntCfg2GHz;
6743                 return AH_TRUE;
6744         case HAL_CAP_ANT_CFG_5GHZ:
6745                 *result = pCap->halNumAntCfg5GHz;
6746                 return AH_TRUE;
6747         case HAL_CAP_TXPOW:
6748                 switch (capability) {
6749                 case 0:
6750                         return HAL_OK;
6751                 case 1:
6752                         *result = ah->ah_powerLimit;
6753                         return HAL_OK;
6754                 case 2:
6755                         *result = ah->ah_maxPowerLevel;
6756                         return HAL_OK;
6757                 case 3:
6758                         *result = ah->ah_tpScale;
6759                         return HAL_OK;
6760                 }
6761                 return AH_FALSE;
6762         default:
6763                 return AH_FALSE;
6764         }
6765 }
6766
6767 enum hal_status
6768 ath9k_hw_select_antconfig(struct ath_hal *ah, u_int32_t cfg)
6769 {
6770         struct ath_hal_5416 *ahp = AH5416(ah);
6771         struct hal_channel_internal *chan = ah->ah_curchan;
6772         const struct hal_capabilities *pCap = &ah->ah_caps;
6773         u_int16_t ant_config;
6774         u_int32_t halNumAntConfig;
6775
6776         halNumAntConfig =
6777                 IS_CHAN_2GHZ(chan) ? pCap->halNumAntCfg2GHz : pCap->
6778                 halNumAntCfg5GHz;
6779
6780         if (cfg < halNumAntConfig) {
6781                 if (HAL_OK ==
6782                     ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, cfg,
6783                                                     &ant_config)) {
6784                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6785                         return HAL_OK;
6786                 }
6787         }
6788
6789         return HAL_EINVAL;
6790 }
6791
6792 enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah)
6793 {
6794         u_int32_t host_isr;
6795
6796         if (AR_SREV_9100(ah))
6797                 return AH_TRUE;
6798
6799         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6800         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6801                 return AH_TRUE;
6802
6803         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6804         if ((host_isr & AR_INTR_SYNC_DEFAULT)
6805             && (host_isr != AR_INTR_SPURIOUS))
6806                 return AH_TRUE;
6807
6808         return AH_FALSE;
6809 }
6810
6811 enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
6812 {
6813         u_int32_t isr = 0;
6814         u_int32_t mask2 = 0;
6815         struct hal_capabilities *pCap = &ah->ah_caps;
6816         u_int32_t sync_cause = 0;
6817         enum hal_bool fatal_int = AH_FALSE;
6818
6819         if (!AR_SREV_9100(ah)) {
6820                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6821                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6822                             == AR_RTC_STATUS_ON) {
6823                                 isr = REG_READ(ah, AR_ISR);
6824                         }
6825                 }
6826
6827                 sync_cause =
6828                         REG_READ(ah,
6829                                  AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6830
6831                 *masked = 0;
6832
6833                 if (!isr && !sync_cause)
6834                         return AH_FALSE;
6835         } else {
6836                 *masked = 0;
6837                 isr = REG_READ(ah, AR_ISR);
6838         }
6839
6840         if (isr) {
6841                 struct ath_hal_5416 *ahp = AH5416(ah);
6842
6843                 if (isr & AR_ISR_BCNMISC) {
6844                         u_int32_t isr2;
6845                         isr2 = REG_READ(ah, AR_ISR_S2);
6846                         if (isr2 & AR_ISR_S2_TIM)
6847                                 mask2 |= HAL_INT_TIM;
6848                         if (isr2 & AR_ISR_S2_DTIM)
6849                                 mask2 |= HAL_INT_DTIM;
6850                         if (isr2 & AR_ISR_S2_DTIMSYNC)
6851                                 mask2 |= HAL_INT_DTIMSYNC;
6852                         if (isr2 & (AR_ISR_S2_CABEND))
6853                                 mask2 |= HAL_INT_CABEND;
6854                         if (isr2 & AR_ISR_S2_GTT)
6855                                 mask2 |= HAL_INT_GTT;
6856                         if (isr2 & AR_ISR_S2_CST)
6857                                 mask2 |= HAL_INT_CST;
6858                 }
6859
6860                 isr = REG_READ(ah, AR_ISR_RAC);
6861                 if (isr == 0xffffffff) {
6862                         *masked = 0;
6863                         return AH_FALSE;
6864                 }
6865
6866                 *masked = isr & HAL_INT_COMMON;
6867
6868                 if (ahp->ah_intrMitigation) {
6869
6870                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6871                                 *masked |= HAL_INT_RX;
6872                 }
6873
6874                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6875                         *masked |= HAL_INT_RX;
6876                 if (isr &
6877                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6878                      AR_ISR_TXEOL)) {
6879                         u_int32_t s0_s, s1_s;
6880
6881                         *masked |= HAL_INT_TX;
6882
6883                         s0_s = REG_READ(ah, AR_ISR_S0_S);
6884                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6885                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6886
6887                         s1_s = REG_READ(ah, AR_ISR_S1_S);
6888                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6889                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6890                 }
6891
6892                 if (isr & AR_ISR_RXORN) {
6893                         HDPRINTF(ah, HAL_DBG_INTERRUPT,
6894                                  "%s: receive FIFO overrun interrupt\n",
6895                                  __func__);
6896                 }
6897
6898                 if (!AR_SREV_9100(ah)) {
6899                         if (!pCap->halAutoSleepSupport) {
6900                                 u_int32_t isr5 = REG_READ(ah, AR_ISR_S5_S);
6901                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
6902                                         *masked |= HAL_INT_TIM_TIMER;
6903                         }
6904                 }
6905
6906                 *masked |= mask2;
6907         }
6908         if (AR_SREV_9100(ah))
6909                 return AH_TRUE;
6910         if (sync_cause) {
6911                 fatal_int =
6912                         (sync_cause &
6913                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6914                         ? AH_TRUE : AH_FALSE;
6915
6916                 if (AH_TRUE == fatal_int) {
6917                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6918                                 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
6919                                          "%s: received PCI FATAL interrupt\n",
6920                                          __func__);
6921                         }
6922                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6923                                 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
6924                                          "%s: received PCI PERR interrupt\n",
6925                                          __func__);
6926                         }
6927                 }
6928                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6929                         HDPRINTF(ah, HAL_DBG_INTERRUPT,
6930                                  "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6931                                  __func__);
6932                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6933                         REG_WRITE(ah, AR_RC, 0);
6934                         *masked |= HAL_INT_FATAL;
6935                 }
6936                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6937                         HDPRINTF(ah, HAL_DBG_INTERRUPT,
6938                                  "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6939                                  __func__);
6940                 }
6941
6942                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6943                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6944         }
6945         return AH_TRUE;
6946 }
6947
6948 enum hal_int ath9k_hw_intrget(struct ath_hal *ah)
6949 {
6950         return AH5416(ah)->ah_maskReg;
6951 }
6952
6953 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
6954 {
6955         struct ath_hal_5416 *ahp = AH5416(ah);
6956         u_int32_t omask = ahp->ah_maskReg;
6957         u_int32_t mask, mask2;
6958         struct hal_capabilities *pCap = &ah->ah_caps;
6959
6960         HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6961                  omask, ints);
6962
6963         if (omask & HAL_INT_GLOBAL) {
6964                 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: disable IER\n",
6965                          __func__);
6966                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6967                 (void) REG_READ(ah, AR_IER);
6968                 if (!AR_SREV_9100(ah)) {
6969                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6970                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6971
6972                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6973                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6974                 }
6975         }
6976
6977         mask = ints & HAL_INT_COMMON;
6978         mask2 = 0;
6979
6980         if (ints & HAL_INT_TX) {
6981                 if (ahp->ah_txOkInterruptMask)
6982                         mask |= AR_IMR_TXOK;
6983                 if (ahp->ah_txDescInterruptMask)
6984                         mask |= AR_IMR_TXDESC;
6985                 if (ahp->ah_txErrInterruptMask)
6986                         mask |= AR_IMR_TXERR;
6987                 if (ahp->ah_txEolInterruptMask)
6988                         mask |= AR_IMR_TXEOL;
6989         }
6990         if (ints & HAL_INT_RX) {
6991                 mask |= AR_IMR_RXERR;
6992                 if (ahp->ah_intrMitigation)
6993                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6994                 else
6995                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6996                 if (!pCap->halAutoSleepSupport)
6997                         mask |= AR_IMR_GENTMR;
6998         }
6999
7000         if (ints & (HAL_INT_BMISC)) {
7001                 mask |= AR_IMR_BCNMISC;
7002                 if (ints & HAL_INT_TIM)
7003                         mask2 |= AR_IMR_S2_TIM;
7004                 if (ints & HAL_INT_DTIM)
7005                         mask2 |= AR_IMR_S2_DTIM;
7006                 if (ints & HAL_INT_DTIMSYNC)
7007                         mask2 |= AR_IMR_S2_DTIMSYNC;
7008                 if (ints & HAL_INT_CABEND)
7009                         mask2 |= (AR_IMR_S2_CABEND);
7010         }
7011
7012         if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
7013                 mask |= AR_IMR_BCNMISC;
7014                 if (ints & HAL_INT_GTT)
7015                         mask2 |= AR_IMR_S2_GTT;
7016                 if (ints & HAL_INT_CST)
7017                         mask2 |= AR_IMR_S2_CST;
7018         }
7019
7020         HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
7021                  mask);
7022         REG_WRITE(ah, AR_IMR, mask);
7023         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
7024                                            AR_IMR_S2_DTIM |
7025                                            AR_IMR_S2_DTIMSYNC |
7026                                            AR_IMR_S2_CABEND |
7027                                            AR_IMR_S2_CABTO |
7028                                            AR_IMR_S2_TSFOOR |
7029                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
7030         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
7031         ahp->ah_maskReg = ints;
7032
7033         if (!pCap->halAutoSleepSupport) {
7034                 if (ints & HAL_INT_TIM_TIMER)
7035                         OS_REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7036                 else
7037                         OS_REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7038         }
7039
7040         if (ints & HAL_INT_GLOBAL) {
7041                 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: enable IER\n",
7042                          __func__);
7043                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
7044                 if (!AR_SREV_9100(ah)) {
7045                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
7046                                   AR_INTR_MAC_IRQ);
7047                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
7048
7049
7050                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
7051                                   AR_INTR_SYNC_DEFAULT);
7052                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
7053                                   AR_INTR_SYNC_DEFAULT);
7054                 }
7055                 HDPRINTF(ah, HAL_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
7056                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
7057         }
7058
7059         return omask;
7060 }
7061
7062 void
7063 ath9k_hw_beaconinit(struct ath_hal *ah,
7064                     u_int32_t next_beacon, u_int32_t beacon_period)
7065 {
7066         struct ath_hal_5416 *ahp = AH5416(ah);
7067         int flags = 0;
7068
7069         ahp->ah_beaconInterval = beacon_period;
7070
7071         switch (ah->ah_opmode) {
7072         case HAL_M_STA:
7073         case HAL_M_MONITOR:
7074                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7075                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7076                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7077                 flags |= AR_TBTT_TIMER_EN;
7078                 break;
7079         case HAL_M_IBSS:
7080                 OS_REG_SET_BIT(ah, AR_TXCFG,
7081                                AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7082                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7083                           TU_TO_USEC(next_beacon +
7084                                      (ahp->ah_atimWindow ? ahp->
7085                                       ah_atimWindow : 1)));
7086                 flags |= AR_NDP_TIMER_EN;
7087         case HAL_M_HOSTAP:
7088                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7089                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7090                           TU_TO_USEC(next_beacon -
7091                                      ah->ah_config.
7092                                      ath_hal_dma_beacon_response_time));
7093                 REG_WRITE(ah, AR_NEXT_SWBA,
7094                           TU_TO_USEC(next_beacon -
7095                                      ah->ah_config.
7096                                      ath_hal_sw_beacon_response_time));
7097                 flags |=
7098                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7099                 break;
7100         }
7101
7102         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7103         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7104         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7105         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7106
7107         beacon_period &= ~HAL_BEACON_ENA;
7108         if (beacon_period & HAL_BEACON_RESET_TSF) {
7109                 beacon_period &= ~HAL_BEACON_RESET_TSF;
7110                 ath9k_hw_reset_tsf(ah);
7111         }
7112
7113         OS_REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7114 }
7115
7116 void
7117 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7118                                const struct hal_beacon_state *bs)
7119 {
7120         u_int32_t nextTbtt, beaconintval, dtimperiod, beacontimeout;
7121         struct hal_capabilities *pCap = &ah->ah_caps;
7122
7123         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7124
7125         REG_WRITE(ah, AR_BEACON_PERIOD,
7126                   TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
7127         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7128                   TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
7129
7130         OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
7131                          AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7132
7133         beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
7134
7135         if (bs->bs_sleepduration > beaconintval)
7136                 beaconintval = bs->bs_sleepduration;
7137
7138         dtimperiod = bs->bs_dtimperiod;
7139         if (bs->bs_sleepduration > dtimperiod)
7140                 dtimperiod = bs->bs_sleepduration;
7141
7142         if (beaconintval == dtimperiod)
7143                 nextTbtt = bs->bs_nextdtim;
7144         else
7145                 nextTbtt = bs->bs_nexttbtt;
7146
7147         HDPRINTF(ah, HAL_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7148                  bs->bs_nextdtim);
7149         HDPRINTF(ah, HAL_DBG_BEACON, "%s: next beacon %d\n", __func__,
7150                  nextTbtt);
7151         HDPRINTF(ah, HAL_DBG_BEACON, "%s: beacon period %d\n", __func__,
7152                  beaconintval);
7153         HDPRINTF(ah, HAL_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7154                  dtimperiod);
7155
7156         REG_WRITE(ah, AR_NEXT_DTIM,
7157                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7158         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7159
7160         REG_WRITE(ah, AR_SLEEP1,
7161                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7162                   | AR_SLEEP1_ASSUME_DTIM);
7163
7164         if (pCap->halAutoSleepSupport)
7165                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7166         else
7167                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7168
7169         REG_WRITE(ah, AR_SLEEP2,
7170                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7171
7172         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7173         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7174
7175         OS_REG_SET_BIT(ah, AR_TIMER_MODE,
7176                        AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7177                        AR_DTIM_TIMER_EN);
7178
7179 }
7180
7181 enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry)
7182 {
7183         if (entry < ah->ah_caps.halKeyCacheSize) {
7184                 u_int32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7185                 if (val & AR_KEYTABLE_VALID)
7186                         return AH_TRUE;
7187         }
7188         return AH_FALSE;
7189 }
7190
7191 enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
7192 {
7193         u_int32_t keyType;
7194
7195         if (entry >= ah->ah_caps.halKeyCacheSize) {
7196                 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7197                          "%s: entry %u out of range\n", __func__, entry);
7198                 return AH_FALSE;
7199         }
7200         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7201
7202         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7203         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7204         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7205         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7206         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7207         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7208         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7209         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7210
7211         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7212                 u_int16_t micentry = entry + 64;
7213
7214                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7215                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7216                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7217                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7218
7219         }
7220
7221         if (ah->ah_curchan == NULL)
7222                 return AH_TRUE;
7223
7224         return AH_TRUE;
7225 }
7226
7227 enum hal_bool
7228 ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
7229                    const u_int8_t *mac)
7230 {
7231         u_int32_t macHi, macLo;
7232
7233         if (entry >= ah->ah_caps.halKeyCacheSize) {
7234                 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7235                          "%s: entry %u out of range\n", __func__, entry);
7236                 return AH_FALSE;
7237         }
7238
7239         if (mac != NULL) {
7240                 macHi = (mac[5] << 8) | mac[4];
7241                 macLo = (mac[3] << 24) | (mac[2] << 16)
7242                         | (mac[1] << 8) | mac[0];
7243                 macLo >>= 1;
7244                 macLo |= (macHi & 1) << 31;
7245                 macHi >>= 1;
7246         } else {
7247                 macLo = macHi = 0;
7248         }
7249         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7250         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7251
7252         return AH_TRUE;
7253 }
7254
7255 enum hal_bool
7256 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
7257                             const struct hal_keyval *k,
7258                             const u_int8_t *mac, int xorKey)
7259 {
7260         const struct hal_capabilities *pCap = &ah->ah_caps;
7261         u_int32_t key0, key1, key2, key3, key4;
7262         u_int32_t keyType;
7263         u_int32_t xorMask = xorKey ?
7264                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7265                  | ATH9K_KEY_XOR) : 0;
7266         struct ath_hal_5416 *ahp = AH5416(ah);
7267
7268         if (entry >= pCap->halKeyCacheSize) {
7269                 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7270                          "%s: entry %u out of range\n", __func__, entry);
7271                 return AH_FALSE;
7272         }
7273         switch (k->kv_type) {
7274         case HAL_CIPHER_AES_OCB:
7275                 keyType = AR_KEYTABLE_TYPE_AES;
7276                 break;
7277         case HAL_CIPHER_AES_CCM:
7278                 if (!pCap->halCipherAesCcmSupport) {
7279                         HDPRINTF(ah, HAL_DBG_KEYCACHE,
7280                                  "%s: AES-CCM not supported by "
7281                                  "mac rev 0x%x\n", __func__,
7282                                  ah->ah_macRev);
7283                         return AH_FALSE;
7284                 }
7285                 keyType = AR_KEYTABLE_TYPE_CCM;
7286                 break;
7287         case HAL_CIPHER_TKIP:
7288                 keyType = AR_KEYTABLE_TYPE_TKIP;
7289                 if (ATH9K_IS_MIC_ENABLED(ah)
7290                     && entry + 64 >= pCap->halKeyCacheSize) {
7291                         HDPRINTF(ah, HAL_DBG_KEYCACHE,
7292                                  "%s: entry %u inappropriate for TKIP\n",
7293                                  __func__, entry);
7294                         return AH_FALSE;
7295                 }
7296                 break;
7297         case HAL_CIPHER_WEP:
7298                 if (k->kv_len < 40 / NBBY) {
7299                         HDPRINTF(ah, HAL_DBG_KEYCACHE,
7300                                  "%s: WEP key length %u too small\n",
7301                                  __func__, k->kv_len);
7302                         return AH_FALSE;
7303                 }
7304                 if (k->kv_len <= 40 / NBBY)
7305                         keyType = AR_KEYTABLE_TYPE_40;
7306                 else if (k->kv_len <= 104 / NBBY)
7307                         keyType = AR_KEYTABLE_TYPE_104;
7308                 else
7309                         keyType = AR_KEYTABLE_TYPE_128;
7310                 break;
7311         case HAL_CIPHER_CLR:
7312                 keyType = AR_KEYTABLE_TYPE_CLR;
7313                 break;
7314         default:
7315                 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7316                          "%s: cipher %u not supported\n", __func__,
7317                          k->kv_type);
7318                 return AH_FALSE;
7319         }
7320
7321         key0 = LE_READ_4(k->kv_val + 0) ^ xorMask;
7322         key1 = (LE_READ_2(k->kv_val + 4) ^ xorMask) & 0xffff;
7323         key2 = LE_READ_4(k->kv_val + 6) ^ xorMask;
7324         key3 = (LE_READ_2(k->kv_val + 10) ^ xorMask) & 0xffff;
7325         key4 = LE_READ_4(k->kv_val + 12) ^ xorMask;
7326         if (k->kv_len <= 104 / NBBY)
7327                 key4 &= 0xff;
7328
7329         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7330                 u_int16_t micentry = entry + 64;
7331
7332                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7333                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7334                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7335                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7336                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7337                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7338                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7339
7340                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7341                         u_int32_t mic0, mic1, mic2, mic3, mic4;
7342
7343                         mic0 = LE_READ_4(k->kv_mic + 0);
7344                         mic2 = LE_READ_4(k->kv_mic + 4);
7345                         mic1 = LE_READ_2(k->kv_txmic + 2) & 0xffff;
7346                         mic3 = LE_READ_2(k->kv_txmic + 0) & 0xffff;
7347                         mic4 = LE_READ_4(k->kv_txmic + 4);
7348                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7349                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7350                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7351                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7352                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7353                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7354                                   AR_KEYTABLE_TYPE_CLR);
7355
7356                 } else {
7357                         u_int32_t mic0, mic2;
7358
7359                         mic0 = LE_READ_4(k->kv_mic + 0);
7360                         mic2 = LE_READ_4(k->kv_mic + 4);
7361                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7362                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7363                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7364                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7365                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7366                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7367                                   AR_KEYTABLE_TYPE_CLR);
7368                 }
7369                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7370                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7371                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7372                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7373         } else {
7374                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7375                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7376                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7377                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7378                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7379                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7380
7381                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7382         }
7383
7384         if (ah->ah_curchan == NULL)
7385                 return AH_TRUE;
7386
7387         return AH_TRUE;
7388 }
7389
7390 enum hal_bool
7391 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, enum hal_bool bIncTrigLevel)
7392 {
7393         struct ath_hal_5416 *ahp = AH5416(ah);
7394         u_int32_t txcfg, curLevel, newLevel;
7395         enum hal_int omask;
7396
7397         if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7398                 return AH_FALSE;
7399
7400         omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~HAL_INT_GLOBAL);
7401
7402         txcfg = REG_READ(ah, AR_TXCFG);
7403         curLevel = MS(txcfg, AR_FTRIG);
7404         newLevel = curLevel;
7405         if (bIncTrigLevel) {
7406                 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7407                         newLevel++;
7408         } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7409                 newLevel--;
7410         if (newLevel != curLevel)
7411                 REG_WRITE(ah, AR_TXCFG,
7412                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7413
7414         ath9k_hw_set_interrupts(ah, omask);
7415
7416         ah->ah_txTrigLevel = newLevel;
7417
7418         return newLevel != curLevel;
7419 }
7420
7421 static enum hal_bool ath9k_hw_set_txq_props(struct ath_hal *ah,
7422                                      struct hal_tx_queue_info *qi,
7423                                      const struct hal_txq_info *qInfo)
7424 {
7425         u_int32_t cw;
7426
7427         if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7428                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
7429                          __func__);
7430                 return AH_FALSE;
7431         }
7432
7433         HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7434
7435         qi->tqi_ver = qInfo->tqi_ver;
7436         qi->tqi_subtype = qInfo->tqi_subtype;
7437         qi->tqi_qflags = qInfo->tqi_qflags;
7438         qi->tqi_priority = qInfo->tqi_priority;
7439         if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
7440                 qi->tqi_aifs = min(qInfo->tqi_aifs, 255U);
7441         else
7442                 qi->tqi_aifs = INIT_AIFS;
7443         if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
7444                 cw = min(qInfo->tqi_cwmin, 1024U);
7445                 qi->tqi_cwmin = 1;
7446                 while (qi->tqi_cwmin < cw)
7447                         qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7448         } else
7449                 qi->tqi_cwmin = qInfo->tqi_cwmin;
7450         if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
7451                 cw = min(qInfo->tqi_cwmax, 1024U);
7452                 qi->tqi_cwmax = 1;
7453                 while (qi->tqi_cwmax < cw)
7454                         qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7455         } else
7456                 qi->tqi_cwmax = INIT_CWMAX;
7457
7458         if (qInfo->tqi_shretry != 0)
7459                 qi->tqi_shretry = min((u_int32_t) qInfo->tqi_shretry, 15U);
7460         else
7461                 qi->tqi_shretry = INIT_SH_RETRY;
7462         if (qInfo->tqi_lgretry != 0)
7463                 qi->tqi_lgretry = min((u_int32_t) qInfo->tqi_lgretry, 15U);
7464         else
7465                 qi->tqi_lgretry = INIT_LG_RETRY;
7466         qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
7467         qi->tqi_cbrOverflowLimit = qInfo->tqi_cbrOverflowLimit;
7468         qi->tqi_burstTime = qInfo->tqi_burstTime;
7469         qi->tqi_readyTime = qInfo->tqi_readyTime;
7470
7471         switch (qInfo->tqi_subtype) {
7472         case HAL_WME_UPSD:
7473                 if (qi->tqi_type == HAL_TX_QUEUE_DATA)
7474                         qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
7475                 break;
7476         default:
7477                 break;
7478         }
7479         return AH_TRUE;
7480 }
7481
7482 enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
7483                                        const struct hal_txq_info *qInfo)
7484 {
7485         struct ath_hal_5416 *ahp = AH5416(ah);
7486         struct hal_capabilities *pCap = &ah->ah_caps;
7487
7488         if (q >= pCap->halTotalQueues) {
7489                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7490                          __func__, q);
7491                 return AH_FALSE;
7492         }
7493         return ath9k_hw_set_txq_props(ah, &ahp->ah_txq[q], qInfo);
7494 }
7495
7496 static enum hal_bool ath9k_hw_get_txq_props(struct ath_hal *ah,
7497                                      struct hal_txq_info *qInfo,
7498                                      const struct hal_tx_queue_info *qi)
7499 {
7500         if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7501                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
7502                          __func__);
7503                 return AH_FALSE;
7504         }
7505
7506         qInfo->tqi_qflags = qi->tqi_qflags;
7507         qInfo->tqi_ver = qi->tqi_ver;
7508         qInfo->tqi_subtype = qi->tqi_subtype;
7509         qInfo->tqi_qflags = qi->tqi_qflags;
7510         qInfo->tqi_priority = qi->tqi_priority;
7511         qInfo->tqi_aifs = qi->tqi_aifs;
7512         qInfo->tqi_cwmin = qi->tqi_cwmin;
7513         qInfo->tqi_cwmax = qi->tqi_cwmax;
7514         qInfo->tqi_shretry = qi->tqi_shretry;
7515         qInfo->tqi_lgretry = qi->tqi_lgretry;
7516         qInfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7517         qInfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7518         qInfo->tqi_burstTime = qi->tqi_burstTime;
7519         qInfo->tqi_readyTime = qi->tqi_readyTime;
7520
7521         return AH_TRUE;
7522 }
7523
7524 enum hal_bool
7525 ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
7526                          struct hal_txq_info *qInfo)
7527 {
7528         struct ath_hal_5416 *ahp = AH5416(ah);
7529         struct hal_capabilities *pCap = &ah->ah_caps;
7530
7531         if (q >= pCap->halTotalQueues) {
7532                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7533                          __func__, q);
7534                 return AH_FALSE;
7535         }
7536         return ath9k_hw_get_txq_props(ah, qInfo, &ahp->ah_txq[q]);
7537 }
7538
7539 int
7540 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
7541                       const struct hal_txq_info *qInfo)
7542 {
7543         struct ath_hal_5416 *ahp = AH5416(ah);
7544         struct hal_tx_queue_info *qi;
7545         struct hal_capabilities *pCap = &ah->ah_caps;
7546         int q;
7547
7548         switch (type) {
7549         case HAL_TX_QUEUE_BEACON:
7550                 q = pCap->halTotalQueues - 1;
7551                 break;
7552         case HAL_TX_QUEUE_CAB:
7553                 q = pCap->halTotalQueues - 2;
7554                 break;
7555         case HAL_TX_QUEUE_PSPOLL:
7556                 q = 1;
7557                 break;
7558         case HAL_TX_QUEUE_UAPSD:
7559                 q = pCap->halTotalQueues - 3;
7560                 break;
7561         case HAL_TX_QUEUE_DATA:
7562                 for (q = 0; q < pCap->halTotalQueues; q++)
7563                         if (ahp->ah_txq[q].tqi_type ==
7564                             HAL_TX_QUEUE_INACTIVE)
7565                                 break;
7566                 if (q == pCap->halTotalQueues) {
7567                         HDPRINTF(ah, HAL_DBG_QUEUE,
7568                                  "%s: no available tx queue\n", __func__);
7569                         return -1;
7570                 }
7571                 break;
7572         default:
7573                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: bad tx queue type %u\n",
7574                          __func__, type);
7575                 return -1;
7576         }
7577
7578         HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7579
7580         qi = &ahp->ah_txq[q];
7581         if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
7582                 HDPRINTF(ah, HAL_DBG_QUEUE,
7583                          "%s: tx queue %u already active\n", __func__, q);
7584                 return -1;
7585         }
7586         memset(qi, 0, sizeof(struct hal_tx_queue_info));
7587         qi->tqi_type = type;
7588         if (qInfo == NULL) {
7589                 qi->tqi_qflags =
7590                         TXQ_FLAG_TXOKINT_ENABLE
7591                         | TXQ_FLAG_TXERRINT_ENABLE
7592                         | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7593                 qi->tqi_aifs = INIT_AIFS;
7594                 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;
7595                 qi->tqi_cwmax = INIT_CWMAX;
7596                 qi->tqi_shretry = INIT_SH_RETRY;
7597                 qi->tqi_lgretry = INIT_LG_RETRY;
7598                 qi->tqi_physCompBuf = 0;
7599         } else {
7600                 qi->tqi_physCompBuf = qInfo->tqi_compBuf;
7601                 (void) ath9k_hw_settxqueueprops(ah, q, qInfo);
7602         }
7603
7604         return q;
7605 }
7606
7607 static void
7608 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7609                             struct hal_tx_queue_info *qi)
7610 {
7611         struct ath_hal_5416 *ahp = AH5416(ah);
7612
7613         HDPRINTF(ah, HAL_DBG_INTERRUPT,
7614                  "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7615                  __func__, ahp->ah_txOkInterruptMask,
7616                  ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7617                  ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7618
7619         REG_WRITE(ah, AR_IMR_S0,
7620                   SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7621                   | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
7622                 );
7623         REG_WRITE(ah, AR_IMR_S1,
7624                   SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7625                   | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
7626                 );
7627         OS_REG_RMW_FIELD(ah, AR_IMR_S2,
7628                          AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7629 }
7630
7631 enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
7632 {
7633         struct ath_hal_5416 *ahp = AH5416(ah);
7634         struct hal_capabilities *pCap = &ah->ah_caps;
7635         struct hal_tx_queue_info *qi;
7636
7637         if (q >= pCap->halTotalQueues) {
7638                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7639                          __func__, q);
7640                 return AH_FALSE;
7641         }
7642         qi = &ahp->ah_txq[q];
7643         if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7644                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
7645                          __func__, q);
7646                 return AH_FALSE;
7647         }
7648
7649         HDPRINTF(ah, HAL_DBG_QUEUE, "%s: release queue %u\n", __func__, q);
7650
7651         qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
7652         ahp->ah_txOkInterruptMask &= ~(1 << q);
7653         ahp->ah_txErrInterruptMask &= ~(1 << q);
7654         ahp->ah_txDescInterruptMask &= ~(1 << q);
7655         ahp->ah_txEolInterruptMask &= ~(1 << q);
7656         ahp->ah_txUrnInterruptMask &= ~(1 << q);
7657         ath9k_hw_set_txq_interrupts(ah, qi);
7658
7659         return AH_TRUE;
7660 }
7661
7662 enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
7663 {
7664         struct ath_hal_5416 *ahp = AH5416(ah);
7665         struct hal_capabilities *pCap = &ah->ah_caps;
7666         struct hal_channel_internal *chan = ah->ah_curchan;
7667         struct hal_tx_queue_info *qi;
7668         u_int32_t cwMin, chanCwMin, value;
7669
7670         if (q >= pCap->halTotalQueues) {
7671                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7672                          __func__, q);
7673                 return AH_FALSE;
7674         }
7675         qi = &ahp->ah_txq[q];
7676         if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7677                 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
7678                          __func__, q);
7679                 return AH_TRUE;
7680         }
7681
7682         HDPRINTF(ah, HAL_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7683
7684         if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
7685                 if (chan && IS_CHAN_B(chan))
7686                         chanCwMin = INIT_CWMIN_11B;
7687                 else
7688                         chanCwMin = INIT_CWMIN;
7689
7690                 for (cwMin = 1; cwMin < chanCwMin;
7691                      cwMin = (cwMin << 1) | 1);
7692         } else
7693                 cwMin = qi->tqi_cwmin;
7694
7695         REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7696                   | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7697                   | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7698
7699         REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7700                   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7701                   | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7702                   | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
7703                 );
7704
7705         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7706         REG_WRITE(ah, AR_DMISC(q),
7707                   AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7708
7709         if (qi->tqi_cbrPeriod) {
7710                 REG_WRITE(ah, AR_QCBRCFG(q),
7711                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7712                           | SM(qi->tqi_cbrOverflowLimit,
7713                                AR_Q_CBRCFG_OVF_THRESH));
7714                 REG_WRITE(ah, AR_QMISC(q),
7715                           REG_READ(ah,
7716                                    AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7717                                         tqi_cbrOverflowLimit
7718                                         ?
7719                                         AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7720                                         :
7721                                         0));
7722         }
7723         if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
7724                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7725                           SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7726                           AR_Q_RDYTIMECFG_EN);
7727         }
7728
7729         REG_WRITE(ah, AR_DCHNTIME(q),
7730                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7731                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7732
7733         if (qi->tqi_burstTime
7734             && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7735                 REG_WRITE(ah, AR_QMISC(q),
7736                           REG_READ(ah,
7737                                    AR_QMISC(q)) |
7738                           AR_Q_MISC_RDYTIME_EXP_POLICY);
7739
7740         }
7741
7742         if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7743                 REG_WRITE(ah, AR_DMISC(q),
7744                           REG_READ(ah, AR_DMISC(q)) |
7745                           AR_D_MISC_POST_FR_BKOFF_DIS);
7746         }
7747         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7748                 REG_WRITE(ah, AR_DMISC(q),
7749                           REG_READ(ah, AR_DMISC(q)) |
7750                           AR_D_MISC_FRAG_BKOFF_EN);
7751         }
7752         switch (qi->tqi_type) {
7753         case HAL_TX_QUEUE_BEACON:
7754                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7755                           | AR_Q_MISC_FSP_DBA_GATED
7756                           | AR_Q_MISC_BEACON_USE
7757                           | AR_Q_MISC_CBR_INCR_DIS1);
7758
7759                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7760                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7761                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7762                           | AR_D_MISC_BEACON_USE
7763                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7764                 break;
7765         case HAL_TX_QUEUE_CAB:
7766                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7767                           | AR_Q_MISC_FSP_DBA_GATED
7768                           | AR_Q_MISC_CBR_INCR_DIS1
7769                           | AR_Q_MISC_CBR_INCR_DIS0);
7770                 value = (qi->tqi_readyTime
7771                          - (ah->ah_config.ath_hal_sw_beacon_response_time -
7772                             ah->ah_config.ath_hal_dma_beacon_response_time)
7773                          -
7774                          ah->ah_config.ath_hal_additional_swba_backoff) *
7775                         1024;
7776                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7777                           value | AR_Q_RDYTIMECFG_EN);
7778                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7779                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7780                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7781                 break;
7782         case HAL_TX_QUEUE_PSPOLL:
7783                 REG_WRITE(ah, AR_QMISC(q),
7784                           REG_READ(ah,
7785                                    AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7786                 break;
7787         case HAL_TX_QUEUE_UAPSD:
7788                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7789                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7790                 break;
7791         default:
7792                 break;
7793         }
7794
7795         if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7796                 REG_WRITE(ah, AR_DMISC(q),
7797                           REG_READ(ah, AR_DMISC(q)) |
7798                           SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7799                              AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7800                           AR_D_MISC_POST_FR_BKOFF_DIS);
7801         }
7802
7803         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7804                 ahp->ah_txOkInterruptMask |= 1 << q;
7805         else
7806                 ahp->ah_txOkInterruptMask &= ~(1 << q);
7807         if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7808                 ahp->ah_txErrInterruptMask |= 1 << q;
7809         else
7810                 ahp->ah_txErrInterruptMask &= ~(1 << q);
7811         if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7812                 ahp->ah_txDescInterruptMask |= 1 << q;
7813         else
7814                 ahp->ah_txDescInterruptMask &= ~(1 << q);
7815         if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7816                 ahp->ah_txEolInterruptMask |= 1 << q;
7817         else
7818                 ahp->ah_txEolInterruptMask &= ~(1 << q);
7819         if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7820                 ahp->ah_txUrnInterruptMask |= 1 << q;
7821         else
7822                 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7823         ath9k_hw_set_txq_interrupts(ah, qi);
7824
7825         return AH_TRUE;
7826 }
7827
7828 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
7829 {
7830         struct ath_hal_5416 *ahp = AH5416(ah);
7831         *txqs &= ahp->ah_intrTxqs;
7832         ahp->ah_intrTxqs &= ~(*txqs);
7833 }
7834
7835 enum hal_bool
7836 ath9k_hw_setupxtxdesc(struct ath_hal *ah, struct ath_desc *ds,
7837                       u_int txRate1, u_int txTries1,
7838                       u_int txRate2, u_int txTries2,
7839                       u_int txRate3, u_int txTries3)
7840 {
7841         struct ar5416_desc *ads = AR5416DESC(ds);
7842
7843         if (txTries1) {
7844                 ads->ds_ctl2 |= AR_DurUpdateEna;
7845                 ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
7846                 ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
7847         }
7848         if (txTries2) {
7849                 ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
7850                 ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
7851         }
7852         if (txTries3) {
7853                 ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
7854                 ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
7855         }
7856         return AH_TRUE;
7857 }
7858
7859 enum hal_bool
7860 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7861                     u_int segLen, enum hal_bool firstSeg,
7862                     enum hal_bool lastSeg, const struct ath_desc *ds0)
7863 {
7864         struct ar5416_desc *ads = AR5416DESC(ds);
7865
7866         if (firstSeg) {
7867                 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7868         } else if (lastSeg) {
7869                 ads->ds_ctl0 = 0;
7870                 ads->ds_ctl1 = segLen;
7871                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7872                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7873         } else {
7874                 ads->ds_ctl0 = 0;
7875                 ads->ds_ctl1 = segLen | AR_TxMore;
7876                 ads->ds_ctl2 = 0;
7877                 ads->ds_ctl3 = 0;
7878         }
7879         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7880         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7881         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7882         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7883         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7884         return AH_TRUE;
7885 }
7886
7887 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7888 {
7889         struct ar5416_desc *ads = AR5416DESC(ds);
7890
7891         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7892         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7893         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7894         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7895         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7896 }
7897
7898 enum hal_status
7899 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7900 {
7901         struct ar5416_desc *ads = AR5416DESC(ds);
7902
7903         if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7904                 return HAL_EINPROGRESS;
7905
7906         ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7907         ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7908         ds->ds_txstat.ts_status = 0;
7909         ds->ds_txstat.ts_flags = 0;
7910
7911         if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7912                 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
7913         if (ads->ds_txstatus1 & AR_Filtered)
7914                 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
7915         if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7916                 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
7917         if (ads->ds_txstatus9 & AR_TxOpExceeded)
7918                 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
7919         if (ads->ds_txstatus1 & AR_TxTimerExpired)
7920                 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
7921
7922         if (ads->ds_txstatus1 & AR_DescCfgErr)
7923                 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
7924         if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7925                 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
7926                 ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
7927         }
7928         if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7929                 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
7930                 ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
7931         }
7932         if (ads->ds_txstatus0 & AR_TxBaStatus) {
7933                 ds->ds_txstat.ts_flags |= HAL_TX_BA;
7934                 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7935                 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7936         }
7937
7938         ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7939         switch (ds->ds_txstat.ts_rateindex) {
7940         case 0:
7941                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7942                 break;
7943         case 1:
7944                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7945                 break;
7946         case 2:
7947                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7948                 break;
7949         case 3:
7950                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7951                 break;
7952         }
7953
7954         ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7955         ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7956         ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7957         ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7958         ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7959         ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7960         ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7961         ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7962         ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7963         ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7964         ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7965         ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7966         ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7967         ds->ds_txstat.ts_antenna = 1;
7968
7969         return HAL_OK;
7970 }
7971
7972 void
7973 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7974                        u_int pktLen, enum hal_pkt_type type, u_int txPower,
7975                        u_int keyIx, enum hal_key_type keyType, u_int flags)
7976 {
7977         struct ar5416_desc *ads = AR5416DESC(ds);
7978         struct ath_hal_5416 *ahp = AH5416(ah);
7979
7980         txPower += ahp->ah_txPowerIndexOffset;
7981         if (txPower > 63)
7982                 txPower = 63;
7983
7984         ads->ds_ctl0 = (pktLen & AR_FrameLen)
7985                 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7986                 | SM(txPower, AR_XmitPower)
7987                 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
7988                 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7989                 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7990                 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7991
7992         ads->ds_ctl1 =
7993                 (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7994                 | SM(type, AR_FrameType)
7995                 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
7996                 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7997                 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7998
7999         ads->ds_ctl6 = SM(keyType, AR_EncrType);
8000
8001         if (AR_SREV_9285(ah)) {
8002
8003                 ads->ds_ctl8 = 0;
8004                 ads->ds_ctl9 = 0;
8005                 ads->ds_ctl10 = 0;
8006                 ads->ds_ctl11 = 0;
8007         }
8008 }
8009
8010 void
8011 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
8012                              struct ath_desc *lastds,
8013                              u_int durUpdateEn, u_int rtsctsRate,
8014                              u_int rtsctsDuration,
8015                              struct hal_11n_rate_series series[],
8016                              u_int nseries, u_int flags)
8017 {
8018         struct ar5416_desc *ads = AR5416DESC(ds);
8019         struct ar5416_desc *last_ads = AR5416DESC(lastds);
8020         u_int32_t ds_ctl0;
8021
8022         (void) nseries;
8023         (void) rtsctsDuration;
8024
8025         if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
8026                 ds_ctl0 = ads->ds_ctl0;
8027
8028                 if (flags & HAL_TXDESC_RTSENA) {
8029                         ds_ctl0 &= ~AR_CTSEnable;
8030                         ds_ctl0 |= AR_RTSEnable;
8031                 } else {
8032                         ds_ctl0 &= ~AR_RTSEnable;
8033                         ds_ctl0 |= AR_CTSEnable;
8034                 }
8035
8036                 ads->ds_ctl0 = ds_ctl0;
8037         } else {
8038                 ads->ds_ctl0 =
8039                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
8040         }
8041
8042         ads->ds_ctl2 = set11nTries(series, 0)
8043                 | set11nTries(series, 1)
8044                 | set11nTries(series, 2)
8045                 | set11nTries(series, 3)
8046                 | (durUpdateEn ? AR_DurUpdateEna : 0)
8047                 | SM(0, AR_BurstDur);
8048
8049         ads->ds_ctl3 = set11nRate(series, 0)
8050                 | set11nRate(series, 1)
8051                 | set11nRate(series, 2)
8052                 | set11nRate(series, 3);
8053
8054         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
8055                 | set11nPktDurRTSCTS(series, 1);
8056
8057         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
8058                 | set11nPktDurRTSCTS(series, 3);
8059
8060         ads->ds_ctl7 = set11nRateFlags(series, 0)
8061                 | set11nRateFlags(series, 1)
8062                 | set11nRateFlags(series, 2)
8063                 | set11nRateFlags(series, 3)
8064                 | SM(rtsctsRate, AR_RTSCTSRate);
8065         last_ads->ds_ctl2 = ads->ds_ctl2;
8066         last_ads->ds_ctl3 = ads->ds_ctl3;
8067 }
8068
8069 void
8070 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
8071                            u_int aggrLen)
8072 {
8073         struct ar5416_desc *ads = AR5416DESC(ds);
8074
8075         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8076
8077         ads->ds_ctl6 &= ~AR_AggrLen;
8078         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8079 }
8080
8081 void
8082 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8083                             u_int numDelims)
8084 {
8085         struct ar5416_desc *ads = AR5416DESC(ds);
8086         unsigned int ctl6;
8087
8088         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8089
8090         ctl6 = ads->ds_ctl6;
8091         ctl6 &= ~AR_PadDelim;
8092         ctl6 |= SM(numDelims, AR_PadDelim);
8093         ads->ds_ctl6 = ctl6;
8094 }
8095
8096 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8097 {
8098         struct ar5416_desc *ads = AR5416DESC(ds);
8099
8100         ads->ds_ctl1 |= AR_IsAggr;
8101         ads->ds_ctl1 &= ~AR_MoreAggr;
8102         ads->ds_ctl6 &= ~AR_PadDelim;
8103 }
8104
8105 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8106 {
8107         struct ar5416_desc *ads = AR5416DESC(ds);
8108
8109         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8110 }
8111
8112 void
8113 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8114                               u_int burstDuration)
8115 {
8116         struct ar5416_desc *ads = AR5416DESC(ds);
8117
8118         ads->ds_ctl2 &= ~AR_BurstDur;
8119         ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8120 }
8121
8122 void
8123 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8124                                 u_int vmf)
8125 {
8126         struct ar5416_desc *ads = AR5416DESC(ds);
8127
8128         if (vmf)
8129                 ads->ds_ctl0 |= AR_VirtMoreFrag;
8130         else
8131                 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8132 }
8133
8134 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp)
8135 {
8136         REG_WRITE(ah, AR_RXDP, rxdp);
8137 }
8138
8139 void ath9k_hw_rxena(struct ath_hal *ah)
8140 {
8141         REG_WRITE(ah, AR_CR, AR_CR_RXE);
8142 }
8143
8144 enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set)
8145 {
8146         if (set) {
8147
8148                 OS_REG_SET_BIT(ah, AR_DIAG_SW,
8149                                (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8150
8151                 if (!ath9k_hw_wait
8152                     (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8153                         u_int32_t reg;
8154
8155                         OS_REG_CLR_BIT(ah, AR_DIAG_SW,
8156                                        (AR_DIAG_RX_DIS |
8157                                         AR_DIAG_RX_ABORT));
8158
8159                         reg = REG_READ(ah, AR_OBS_BUS_1);
8160                         HDPRINTF(ah, HAL_DBG_RX,
8161                                 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8162                                 __func__, reg);
8163
8164                         return AH_FALSE;
8165                 }
8166         } else {
8167                 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
8168                                (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8169         }
8170
8171         return AH_TRUE;
8172 }
8173
8174 void
8175 ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
8176                         u_int32_t filter1)
8177 {
8178         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8179         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8180 }
8181
8182 enum hal_bool
8183 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8184                      u_int32_t size, u_int flags)
8185 {
8186         struct ar5416_desc *ads = AR5416DESC(ds);
8187         struct hal_capabilities *pCap = &ah->ah_caps;
8188
8189         ads->ds_ctl1 = size & AR_BufLen;
8190         if (flags & HAL_RXDESC_INTREQ)
8191                 ads->ds_ctl1 |= AR_RxIntrReq;
8192
8193         ads->ds_rxstatus8 &= ~AR_RxDone;
8194         if (!pCap->halAutoSleepSupport)
8195                 memset(&(ads->u), 0, sizeof(ads->u));
8196         return AH_TRUE;
8197 }
8198
8199 enum hal_status
8200 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8201                     u_int32_t pa, struct ath_desc *nds, u_int64_t tsf)
8202 {
8203         struct ar5416_desc ads;
8204         struct ar5416_desc *adsp = AR5416DESC(ds);
8205
8206         if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8207                 return HAL_EINPROGRESS;
8208
8209         ads.u.rx = adsp->u.rx;
8210
8211         ds->ds_rxstat.rs_status = 0;
8212         ds->ds_rxstat.rs_flags = 0;
8213
8214         ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8215         ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8216
8217         ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8218         ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8219         ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8220         ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8221         ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8222         ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8223         ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8224         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8225                 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8226         else
8227                 ds->ds_rxstat.rs_keyix = HAL_RXKEYIX_INVALID;
8228
8229         ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8230         ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8231
8232         ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8233         ds->ds_rxstat.rs_moreaggr =
8234                 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8235         ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8236         ds->ds_rxstat.rs_flags =
8237                 (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
8238         ds->ds_rxstat.rs_flags |=
8239                 (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
8240
8241         if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8242                 ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_PRE;
8243         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8244                 ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_POST;
8245         if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8246                 ds->ds_rxstat.rs_flags |= HAL_RX_DECRYPT_BUSY;
8247
8248         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8249
8250                 if (ads.ds_rxstatus8 & AR_CRCErr)
8251                         ds->ds_rxstat.rs_status |= HAL_RXERR_CRC;
8252                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8253                         u_int phyerr;
8254
8255                         ds->ds_rxstat.rs_status |= HAL_RXERR_PHY;
8256                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8257                         ds->ds_rxstat.rs_phyerr = phyerr;
8258                 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8259                         ds->ds_rxstat.rs_status |= HAL_RXERR_DECRYPT;
8260                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8261                         ds->ds_rxstat.rs_status |= HAL_RXERR_MIC;
8262         }
8263
8264         return HAL_OK;
8265 }
8266
8267 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8268                                       struct hal_rate_table *rt)
8269 {
8270         int i;
8271
8272         if (rt->rateCodeToIndex[0] != 0)
8273                 return;
8274         for (i = 0; i < 256; i++)
8275                 rt->rateCodeToIndex[i] = (u_int8_t) -1;
8276         for (i = 0; i < rt->rateCount; i++) {
8277                 u_int8_t code = rt->info[i].rateCode;
8278                 u_int8_t cix = rt->info[i].controlRate;
8279
8280                 rt->rateCodeToIndex[code] = i;
8281                 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8282
8283                 rt->info[i].lpAckDuration =
8284                         ath9k_hw_computetxtime(ah, rt,
8285                                                WLAN_CTRL_FRAME_SIZE,
8286                                                cix,
8287                                                AH_FALSE);
8288                 rt->info[i].spAckDuration =
8289                         ath9k_hw_computetxtime(ah, rt,
8290                                                WLAN_CTRL_FRAME_SIZE,
8291                                                cix,
8292                                                AH_TRUE);
8293         }
8294 }
8295
8296 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8297                                                    u_int mode)
8298 {
8299         struct hal_rate_table *rt;
8300         switch (mode) {
8301         case ATH9K_MODE_SEL_11A:
8302                 rt = &ar5416_11a_table;
8303                 break;
8304         case ATH9K_MODE_SEL_11B:
8305                 rt = &ar5416_11b_table;
8306                 break;
8307         case ATH9K_MODE_SEL_11G:
8308                 rt = &ar5416_11g_table;
8309                 break;
8310         case ATH9K_MODE_SEL_11NG_HT20:
8311         case ATH9K_MODE_SEL_11NG_HT40PLUS:
8312         case ATH9K_MODE_SEL_11NG_HT40MINUS:
8313                 rt = &ar5416_11ng_table;
8314                 break;
8315         case ATH9K_MODE_SEL_11NA_HT20:
8316         case ATH9K_MODE_SEL_11NA_HT40PLUS:
8317         case ATH9K_MODE_SEL_11NA_HT40MINUS:
8318                 rt = &ar5416_11na_table;
8319                 break;
8320         default:
8321                 HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8322                          __func__, mode);
8323                 return NULL;
8324         }
8325         ath9k_hw_setup_rate_table(ah, rt);
8326         return rt;
8327 }
8328
8329 static const char *ath9k_hw_devname(u_int16_t devid)
8330 {
8331         switch (devid) {
8332         case AR5416_DEVID_PCI:
8333         case AR5416_DEVID_PCIE:
8334                 return "Atheros 5416";
8335         case AR9160_DEVID_PCI:
8336                 return "Atheros 9160";
8337         case AR9280_DEVID_PCI:
8338         case AR9280_DEVID_PCIE:
8339                 return "Atheros 9280";
8340         }
8341         return NULL;
8342 }
8343
8344 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid)
8345 {
8346         return vendorid == ATHEROS_VENDOR_ID ?
8347                 ath9k_hw_devname(devid) : NULL;
8348 }
8349
8350 struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
8351                                 enum hal_status *error)
8352 {
8353         struct ath_hal *ah = NULL;
8354
8355         switch (devid) {
8356         case AR5416_DEVID_PCI:
8357         case AR5416_DEVID_PCIE:
8358         case AR9160_DEVID_PCI:
8359         case AR9280_DEVID_PCI:
8360         case AR9280_DEVID_PCIE:
8361                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8362                 break;
8363         default:
8364                 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
8365                          "devid=0x%x not supported.\n", devid);
8366                 ah = NULL;
8367                 *error = HAL_ENXIO;
8368                 break;
8369         }
8370         if (ah != NULL) {
8371                 ah->ah_devid = ah->ah_devid;
8372                 ah->ah_subvendorid = ah->ah_subvendorid;
8373                 ah->ah_macVersion = ah->ah_macVersion;
8374                 ah->ah_macRev = ah->ah_macRev;
8375                 ah->ah_phyRev = ah->ah_phyRev;
8376                 ah->ah_analog5GhzRev = ah->ah_analog5GhzRev;
8377                 ah->ah_analog2GhzRev = ah->ah_analog2GhzRev;
8378         }
8379         return ah;
8380 }
8381
8382 u_int16_t
8383 ath9k_hw_computetxtime(struct ath_hal *ah,
8384                        const struct hal_rate_table *rates,
8385                        u_int32_t frameLen, u_int16_t rateix,
8386                        enum hal_bool shortPreamble)
8387 {
8388         u_int32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8389         u_int32_t kbps;
8390
8391         kbps = rates->info[rateix].rateKbps;
8392
8393         if (kbps == 0)
8394                 return 0;
8395         switch (rates->info[rateix].phy) {
8396
8397         case PHY_CCK:
8398                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8399                 if (shortPreamble && rates->info[rateix].shortPreamble)
8400                         phyTime >>= 1;
8401                 numBits = frameLen << 3;
8402                 txTime = CCK_SIFS_TIME + phyTime
8403                         + ((numBits * 1000) / kbps);
8404                 break;
8405         case PHY_OFDM:
8406                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8407                         bitsPerSymbol =
8408                                 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8409
8410                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8411                         numSymbols = howmany(numBits, bitsPerSymbol);
8412                         txTime = OFDM_SIFS_TIME_QUARTER
8413                                 + OFDM_PREAMBLE_TIME_QUARTER
8414                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8415                 } else if (ah->ah_curchan &&
8416                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8417                         bitsPerSymbol =
8418                                 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8419
8420                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8421                         numSymbols = howmany(numBits, bitsPerSymbol);
8422                         txTime = OFDM_SIFS_TIME_HALF +
8423                                 OFDM_PREAMBLE_TIME_HALF
8424                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8425                 } else {
8426                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8427
8428                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8429                         numSymbols = howmany(numBits, bitsPerSymbol);
8430                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8431                                 + (numSymbols * OFDM_SYMBOL_TIME);
8432                 }
8433                 break;
8434
8435         default:
8436                 HDPRINTF(ah, HAL_DBG_PHY_IO,
8437                          "%s: unknown phy %u (rate ix %u)\n", __func__,
8438                          rates->info[rateix].phy, rateix);
8439                 txTime = 0;
8440                 break;
8441         }
8442         return txTime;
8443 }
8444
8445 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
8446 {
8447         if (flags & CHANNEL_2GHZ) {
8448                 if (freq == 2484)
8449                         return 14;
8450                 if (freq < 2484)
8451                         return (freq - 2407) / 5;
8452                 else
8453                         return 15 + ((freq - 2512) / 20);
8454         } else if (flags & CHANNEL_5GHZ) {
8455                 if (ath9k_regd_is_public_safety_sku(ah) &&
8456                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8457                         return ((freq * 10) +
8458                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8459                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8460                         return (freq - 4000) / 5;
8461                 } else {
8462                         return (freq - 5000) / 5;
8463                 }
8464         } else {
8465                 if (freq == 2484)
8466                         return 14;
8467                 if (freq < 2484)
8468                         return (freq - 2407) / 5;
8469                 if (freq < 5000) {
8470                         if (ath9k_regd_is_public_safety_sku(ah)
8471                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8472                                 return ((freq * 10) +
8473                                         (((freq % 5) ==
8474                                           2) ? 5 : 0) - 49400) / 5;
8475                         } else if (freq > 4900) {
8476                                 return (freq - 4000) / 5;
8477                         } else {
8478                                 return 15 + ((freq - 2512) / 20);
8479                         }
8480                 }
8481                 return (freq - 5000) / 5;
8482         }
8483 }
8484
8485 int16_t
8486 ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
8487 {
8488         struct hal_channel_internal *ichan;
8489
8490         ichan = ath9k_regd_check_channel(ah, chan);
8491         if (ichan == NULL) {
8492                 HDPRINTF(ah, HAL_DBG_NF_CAL,
8493                          "%s: invalid channel %u/0x%x; no mapping\n",
8494                          __func__, chan->channel, chan->channelFlags);
8495                 return 0;
8496         }
8497         if (ichan->rawNoiseFloor == 0) {
8498                 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8499                 return NOISE_FLOOR[mode];
8500         } else
8501                 return ichan->rawNoiseFloor;
8502 }
8503
8504 enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
8505 {
8506         struct ath_hal_5416 *ahp = AH5416(ah);
8507
8508         if (setting)
8509                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8510         else
8511                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8512         return AH_TRUE;
8513 }
8514
8515 enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah)
8516 {
8517         struct ath_hal_5416 *ahp = AH5416(ah);
8518
8519         return ahp->ah_hasHwPhyCounters ? AH_TRUE : AH_FALSE;
8520 }
8521
8522 u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q)
8523 {
8524         return REG_READ(ah, AR_QTXDP(q));
8525 }
8526
8527 enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
8528                                 u_int32_t txdp)
8529 {
8530         REG_WRITE(ah, AR_QTXDP(q), txdp);
8531
8532         return AH_TRUE;
8533 }
8534
8535 enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
8536 {
8537         HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8538
8539         REG_WRITE(ah, AR_Q_TXE, 1 << q);
8540
8541         return AH_TRUE;
8542 }
8543
8544 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
8545 {
8546         u_int32_t npend;
8547
8548         npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8549         if (npend == 0) {
8550
8551                 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8552                         npend = 1;
8553         }
8554         return npend;
8555 }
8556
8557 enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
8558 {
8559         u_int wait;
8560
8561         REG_WRITE(ah, AR_Q_TXD, 1 << q);
8562
8563         for (wait = 1000; wait != 0; wait--) {
8564                 if (ath9k_hw_numtxpending(ah, q) == 0)
8565                         break;
8566                 udelay(100);
8567         }
8568
8569         if (ath9k_hw_numtxpending(ah, q)) {
8570                 u_int32_t tsfLow, j;
8571
8572                 HDPRINTF(ah, HAL_DBG_QUEUE,
8573                          "%s: Num of pending TX Frames %d on Q %d\n",
8574                          __func__, ath9k_hw_numtxpending(ah, q), q);
8575
8576                 for (j = 0; j < 2; j++) {
8577                         tsfLow = REG_READ(ah, AR_TSF_L32);
8578                         REG_WRITE(ah, AR_QUIET2,
8579                                   SM(10, AR_QUIET2_QUIET_DUR));
8580                         REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8581                         REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8582                         OS_REG_SET_BIT(ah, AR_TIMER_MODE,
8583                                        AR_QUIET_TIMER_EN);
8584
8585                         if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8586                             (tsfLow >> 10)) {
8587                                 break;
8588                         }
8589                         HDPRINTF(ah, HAL_DBG_QUEUE,
8590                                 "%s: TSF have moved while trying to set "
8591                                 "quiet time TSF: 0x%08x\n",
8592                                 __func__, tsfLow);
8593                 }
8594
8595                 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8596
8597                 udelay(200);
8598                 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8599
8600                 wait = 1000;
8601
8602                 while (ath9k_hw_numtxpending(ah, q)) {
8603                         if ((--wait) == 0) {
8604                                 HDPRINTF(ah, HAL_DBG_TX,
8605                                         "%s: Failed to stop Tx DMA in 100 "
8606                                         "msec after killing last frame\n",
8607                                         __func__);
8608                                 break;
8609                         }
8610                         udelay(100);
8611                 }
8612
8613                 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8614         }
8615
8616         REG_WRITE(ah, AR_Q_TXD, 0);
8617         return wait != 0;
8618 }