2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 /* Implementation of beacon processing. */
22 * Configure parameters for the beacon queue
24 * This function will modify certain transmit queue properties depending on
25 * the operating mode of the station (AP or AdHoc). Parameters are AIFS
26 * settings and channel width min/max
29 static int ath_beaconq_config(struct ath_softc *sc)
31 struct ath_hal *ah = sc->sc_ah;
32 struct hal_txq_info qi;
34 ath9k_hw_gettxqueueprops(ah, sc->sc_bhalq, &qi);
35 if (sc->sc_opmode == HAL_M_HOSTAP) {
36 /* Always burst out beacon and CAB traffic. */
41 /* Adhoc mode; important thing is to use 2x cwmin. */
42 qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs;
43 qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin;
44 qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax;
47 if (!ath9k_hw_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
48 DPRINTF(sc, ATH_DBG_FATAL,
49 "%s: unable to update h/w beacon queue parameters\n",
53 ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
59 * Setup the beacon frame for transmit.
61 * Associates the beacon frame buffer with a transmit descriptor. Will set
62 * up all required antenna switch parameters, rate codes, and channel flags.
63 * Beacons are always sent out at the lowest rate, and are not retried.
66 static void ath_beacon_setup(struct ath_softc *sc,
67 struct ath_vap *avp, struct ath_buf *bf)
69 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
70 struct ath_hal *ah = sc->sc_ah;
73 const struct hal_rate_table *rt;
77 struct hal_11n_rate_series series[4];
79 DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
80 __func__, skb, skb->len);
82 /* setup descriptors */
85 flags = HAL_TXDESC_NOACK;
87 if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
88 ds->ds_link = bf->bf_daddr; /* self-linked */
89 flags |= HAL_TXDESC_VEOL;
90 /* Let hardware handle antenna switching. */
95 * Switch antenna every beacon.
96 * Should only switch every beacon period, not for every
98 * XXX assumes two antenna
100 antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
103 ds->ds_data = bf->bf_buf_addr;
106 * Calculate rate code.
107 * XXX everything at min xmit rate
109 rix = sc->sc_minrateix;
110 rt = sc->sc_currates;
111 rate = rt->info[rix].rateCode;
112 if (sc->sc_flags & ATH_PREAMBLE_SHORT)
113 rate |= rt->info[rix].shortPreamble;
115 ath9k_hw_set11n_txdesc(ah, ds
116 , skb->len + FCS_LEN /* frame length */
117 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
118 , avp->av_btxctl.txpower /* txpower XXX */
119 , HAL_TXKEYIX_INVALID /* no encryption */
120 , HAL_KEY_TYPE_CLEAR /* no encryption */
121 , flags /* no ack, veol for beacons */
124 /* NB: beacon's BufLen must be a multiple of 4 bytes */
125 ath9k_hw_filltxdesc(ah, ds
126 , roundup(skb->len, 4) /* buffer length */
127 , true /* first segment */
128 , true /* last segment */
129 , ds /* first descriptor */
132 memzero(series, sizeof(struct hal_11n_rate_series) * 4);
134 series[0].Rate = rate;
135 series[0].ChSel = sc->sc_tx_chainmask;
136 series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
137 ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
138 ctsrate, ctsduration, series, 4, 0);
141 /* Move everything from the vap's mcast queue to the hardware cab queue.
142 * Caller must hold mcasq lock and cabq lock
145 static void empty_mcastq_into_cabq(struct ath_hal *ah,
146 struct ath_txq *mcastq, struct ath_txq *cabq)
148 struct ath_buf *bfmcast;
150 BUG_ON(list_empty(&mcastq->axq_q));
152 bfmcast = list_first_entry(&mcastq->axq_q, struct ath_buf, list);
154 /* link the descriptors */
156 ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr);
158 *cabq->axq_link = bfmcast->bf_daddr;
160 /* append the private vap mcast list to the cabq */
162 cabq->axq_depth += mcastq->axq_depth;
163 cabq->axq_totalqueued += mcastq->axq_totalqueued;
164 cabq->axq_linkbuf = mcastq->axq_linkbuf;
165 cabq->axq_link = mcastq->axq_link;
166 list_splice_tail_init(&mcastq->axq_q, &cabq->axq_q);
167 mcastq->axq_depth = 0;
168 mcastq->axq_totalqueued = 0;
169 mcastq->axq_linkbuf = NULL;
170 mcastq->axq_link = NULL;
173 /* This is only run at DTIM. We move everything from the vap's mcast queue
174 * to the hardware cab queue. Caller must hold the mcastq lock. */
175 static void trigger_mcastq(struct ath_hal *ah,
176 struct ath_txq *mcastq, struct ath_txq *cabq)
178 spin_lock_bh(&cabq->axq_lock);
180 if (!list_empty(&mcastq->axq_q))
181 empty_mcastq_into_cabq(ah, mcastq, cabq);
183 /* cabq is gated by beacon so it is safe to start here */
184 if (!list_empty(&cabq->axq_q))
185 ath9k_hw_txstart(ah, cabq->axq_qnum);
187 spin_unlock_bh(&cabq->axq_lock);
191 * Generate beacon frame and queue cab data for a vap.
193 * Updates the contents of the beacon frame. It is assumed that the buffer for
194 * the beacon frame has been allocated in the ATH object, and simply needs to
195 * be filled for this cycle. Also, any CAB (crap after beacon?) traffic will
196 * be added to the beacon frame at this point.
198 static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
200 struct ath_hal *ah = sc->sc_ah;
206 int is_beacon_dtim = 0;
208 struct ath_txq *cabq;
209 struct ath_txq *mcastq;
210 avp = sc->sc_vaps[if_id];
212 mcastq = &avp->av_mcastq;
217 if (avp->av_bcbuf == NULL) {
218 DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
219 __func__, avp, avp->av_bcbuf);
223 skb = (struct sk_buff *) bf->bf_mpdu;
226 * Update dynamic beacon contents. If this returns
227 * non-zero then we need to remap the memory because
228 * the beacon frame changed size (probably because
229 * of the TIM bitmap).
233 /* XXX: spin_lock_bh should not be used here, but sparse bitches
234 * otherwise. We should fix sparse :) */
235 spin_lock_bh(&mcastq->axq_lock);
236 mcastq_depth = avp->av_mcastq.axq_depth;
238 if (ath_update_beacon(sc, if_id, &avp->av_boff, skb, mcastq_depth) ==
240 ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
241 get_dma_mem_context(bf, bf_dmacontext));
242 bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,
243 get_dma_mem_context(bf, bf_dmacontext));
245 pci_dma_sync_single_for_cpu(sc->pdev,
252 * if the CABQ traffic from previous DTIM is pending and the current
253 * beacon is also a DTIM.
254 * 1) if there is only one vap let the cab traffic continue.
255 * 2) if there are more than one vap and we are using staggered
256 * beacons, then drain the cabq by dropping all the frames in
257 * the cabq so that the current vaps cab traffic can be scheduled.
259 spin_lock_bh(&cabq->axq_lock);
260 cabq_depth = cabq->axq_depth;
261 spin_unlock_bh(&cabq->axq_lock);
263 is_beacon_dtim = avp->av_boff.bo_tim[4] & 1;
265 if (mcastq_depth && is_beacon_dtim && cabq_depth) {
267 * Unlock the cabq lock as ath_tx_draintxq acquires
268 * the lock again which is a common function and that
269 * acquires txq lock inside.
271 if (sc->sc_nvaps > 1) {
272 ath_tx_draintxq(sc, cabq, false);
273 DPRINTF(sc, ATH_DBG_BEACON,
274 "%s: flush previous cabq traffic\n", __func__);
278 /* Construct tx descriptor. */
279 ath_beacon_setup(sc, avp, bf);
282 * Enable the CAB queue before the beacon queue to
283 * insure cab frames are triggered by this beacon.
286 trigger_mcastq(ah, mcastq, cabq);
288 spin_unlock_bh(&mcastq->axq_lock);
293 * Startup beacon transmission for adhoc mode when they are sent entirely
294 * by the hardware using the self-linked descriptor + veol trick.
297 static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
299 struct ath_hal *ah = sc->sc_ah;
304 avp = sc->sc_vaps[if_id];
307 if (avp->av_bcbuf == NULL) {
308 DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
309 __func__, avp, avp != NULL ? avp->av_bcbuf : NULL);
313 skb = (struct sk_buff *) bf->bf_mpdu;
315 /* Construct tx descriptor. */
316 ath_beacon_setup(sc, avp, bf);
318 /* NB: caller is known to have already stopped tx dma */
319 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
320 ath9k_hw_txstart(ah, sc->sc_bhalq);
321 DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
322 sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
326 * Setup a h/w transmit queue for beacons.
328 * This function allocates an information structure (struct hal_txq_info)
329 * on the stack, sets some specific parameters (zero out channel width
330 * min/max, and enable aifs). The info structure does not need to be
334 int ath_beaconq_setup(struct ath_hal *ah)
336 struct hal_txq_info qi;
338 memzero(&qi, sizeof(qi));
342 /* NB: don't enable any interrupts */
343 return ath9k_hw_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
348 * Allocate and setup an initial beacon frame.
350 * Allocate a beacon state variable for a specific VAP instance created on
351 * the ATH interface. This routine also calculates the beacon "slot" for
352 * staggared beacons in the mBSSID case.
355 int ath_beacon_alloc(struct ath_softc *sc, int if_id)
358 struct ieee80211_hdr *wh;
362 avp = sc->sc_vaps[if_id];
365 /* Allocate a beacon descriptor if we haven't done so. */
366 if (!avp->av_bcbuf) {
368 * Allocate beacon state for hostap/ibss. We know
369 * a buffer is available.
372 avp->av_bcbuf = list_first_entry(&sc->sc_bbuf,
373 struct ath_buf, list);
374 list_del(&avp->av_bcbuf->list);
376 if (sc->sc_opmode == HAL_M_HOSTAP ||
377 !sc->sc_ah->ah_caps.halVEOLSupport) {
380 * Assign the vap to a beacon xmit slot. As
381 * above, this cannot fail to find one.
384 for (slot = 0; slot < ATH_BCBUF; slot++)
385 if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) {
387 * XXX hack, space out slots to better
390 if (slot+1 < ATH_BCBUF &&
391 sc->sc_bslot[slot+1] ==
393 avp->av_bslot = slot+1;
396 avp->av_bslot = slot;
397 /* NB: keep looking for a double slot */
399 BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY);
400 sc->sc_bslot[avp->av_bslot] = if_id;
405 /* release the previous beacon frame , if it already exists. */
407 if (bf->bf_mpdu != NULL) {
408 skb = (struct sk_buff *)bf->bf_mpdu;
409 ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
410 get_dma_mem_context(bf, bf_dmacontext));
411 dev_kfree_skb_any(skb);
416 * NB: the beacon data buffer must be 32-bit aligned;
417 * we assume the wbuf routines will return us something
418 * with this alignment (perhaps should assert).
419 * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and
420 * avp->av_btxctl.shortPreamble
422 skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);
424 DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n",
430 * Calculate a TSF adjustment factor required for
431 * staggered beacons. Note that we assume the format
432 * of the beacon frame leaves the tstamp field immediately
433 * following the header.
435 if (avp->av_bslot > 0) {
440 /* FIXME: Use default value for now: Sujith */
442 intval = ATH_DEFAULT_BINTVAL;
445 * The beacon interval is in TU's; the TSF in usecs.
446 * We figure out how many TU's to add to align the
447 * timestamp then convert to TSF units and handle
448 * byte swapping before writing it in the frame.
449 * The hardware will then add this each time a beacon
450 * frame is sent. Note that we align vap's 1..N
451 * and leave vap 0 untouched. This means vap 0
452 * has a timestamp in one beacon interval while the
453 * others get a timestamp aligned to the next interval.
455 tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF;
456 val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */
458 DPRINTF(sc, ATH_DBG_BEACON,
459 "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n",
461 avp->av_bslot, intval, (unsigned long long)tsfadjust);
463 wh = (struct ieee80211_hdr *)skb->data;
464 memcpy(&wh[1], &val, sizeof(val));
467 bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,
468 get_dma_mem_context(bf, bf_dmacontext));
475 * Reclaim beacon resources and return buffer to the pool.
477 * Checks the VAP to put the beacon frame buffer back to the ATH object
478 * queue, and de-allocates any wbuf frames that were sent as CAB traffic.
481 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
483 if (avp->av_bcbuf != NULL) {
486 if (avp->av_bslot != -1) {
487 sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY;
492 if (bf->bf_mpdu != NULL) {
493 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
494 ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
495 get_dma_mem_context(bf, bf_dmacontext));
496 dev_kfree_skb_any(skb);
499 list_add_tail(&bf->list, &sc->sc_bbuf);
501 avp->av_bcbuf = NULL;
506 * Reclaim beacon resources and return buffer to the pool.
508 * This function will free any wbuf frames that are still attached to the
509 * beacon buffers in the ATH object. Note that this does not de-allocate
510 * any wbuf objects that are in the transmit queue and have not yet returned
514 void ath_beacon_free(struct ath_softc *sc)
518 list_for_each_entry(bf, &sc->sc_bbuf, list) {
519 if (bf->bf_mpdu != NULL) {
520 struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
521 ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
522 get_dma_mem_context(bf, bf_dmacontext));
523 dev_kfree_skb_any(skb);
530 * Tasklet for Sending Beacons
532 * Transmit one or more beacon frames at SWBA. Dynamic updates to the frame
533 * contents are done as needed and the slot time is also adjusted based on
536 * This tasklet is not scheduled, it's called in ISR context.
539 void ath9k_beacon_tasklet(unsigned long data)
541 #define TSF_TO_TU(_h,_l) \
542 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
544 struct ath_softc *sc = (struct ath_softc *)data;
545 struct ath_hal *ah = sc->sc_ah;
546 struct ath_buf *bf = NULL;
549 u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
550 u_int32_t show_cycles = 0;
551 u_int32_t bc = 0; /* beacon count */
556 if (sc->sc_noreset) {
557 show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
564 * Check if the previous beacon has gone out. If
565 * not don't try to post another, skip this period
566 * and wait for the next. Missed beacons indicate
567 * a problem and should not occur. If we miss too
568 * many consecutive beacons reset the device.
570 if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) {
572 /* XXX: doth needs the chanchange IE countdown decremented.
573 * We should consider adding a mac80211 call to indicate
574 * a beacon miss so appropriate action could be taken
577 if (sc->sc_bmisscount < BSTUCK_THRESH) {
578 if (sc->sc_noreset) {
579 DPRINTF(sc, ATH_DBG_BEACON,
580 "%s: missed %u consecutive beacons\n",
581 __func__, sc->sc_bmisscount);
584 * Display cycle counter stats
585 * from HW to aide in debug of
590 "%s: busy times: rx_clear=%d, "
591 "rx_frame=%d, tx_frame=%d\n",
592 __func__, rx_clear, rx_frame,
597 "%s: unable to obtain "
598 "busy times\n", __func__);
601 DPRINTF(sc, ATH_DBG_BEACON,
602 "%s: missed %u consecutive beacons\n",
603 __func__, sc->sc_bmisscount);
605 } else if (sc->sc_bmisscount >= BSTUCK_THRESH) {
606 if (sc->sc_noreset) {
607 if (sc->sc_bmisscount == BSTUCK_THRESH) {
610 "%s: beacon is officially "
611 "stuck\n", __func__);
612 ath9k_hw_dmaRegDump(ah);
615 DPRINTF(sc, ATH_DBG_BEACON,
616 "%s: beacon is officially stuck\n",
618 ath_bstuck_process(sc);
624 if (sc->sc_bmisscount != 0) {
625 if (sc->sc_noreset) {
628 "%s: resume beacon xmit after %u misses\n",
629 __func__, sc->sc_bmisscount);
631 DPRINTF(sc, ATH_DBG_BEACON,
632 "%s: resume beacon xmit after %u misses\n",
633 __func__, sc->sc_bmisscount);
635 sc->sc_bmisscount = 0;
639 * Generate beacon frames. we are sending frames
640 * staggered so calculate the slot for this frame based
641 * on the tsf to safeguard against missing an swba.
644 /* FIXME: Use default value for now - Sujith */
645 intval = ATH_DEFAULT_BINTVAL;
647 tsf = ath9k_hw_gettsf64(ah);
648 tsftu = TSF_TO_TU(tsf>>32, tsf);
649 slot = ((tsftu % intval) * ATH_BCBUF) / intval;
650 if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
651 DPRINTF(sc, ATH_DBG_BEACON,
652 "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
653 __func__, slot, (unsigned long long) tsf, tsftu,
656 if (if_id != ATH_IF_ID_ANY) {
657 bf = ath_beacon_generate(sc, if_id);
659 bfaddr = bf->bf_daddr;
664 * Handle slot time change when a non-ERP station joins/leaves
665 * an 11g network. The 802.11 layer notifies us via callback,
666 * we mark updateslot, then wait one beacon before effecting
667 * the change. This gives associated stations at least one
668 * beacon interval to note the state change.
670 * NB: The slot time change state machine is clocked according
671 * to whether we are bursting or staggering beacons. We
672 * recognize the request to update and record the current
673 * slot then don't transition until that slot is reached
674 * again. If we miss a beacon for that slot then we'll be
675 * slow to transition but we'll be sure at least one beacon
676 * interval has passed. When bursting slot is always left
677 * set to ATH_BCBUF so this check is a noop.
680 if (sc->sc_updateslot == UPDATE) {
681 sc->sc_updateslot = COMMIT; /* commit next beacon */
682 sc->sc_slotupdate = slot;
683 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
684 ath_setslottime(sc); /* commit change to hardware */
688 * Stop any current dma and put the new frame(s) on the queue.
689 * This should never fail since we check above that no frames
690 * are still pending on the queue.
692 if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
693 DPRINTF(sc, ATH_DBG_FATAL,
694 "%s: beacon queue %u did not stop?\n",
695 __func__, sc->sc_bhalq);
696 /* NB: the HAL still stops DMA, so proceed */
699 /* NB: cabq traffic should already be queued and primed */
700 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr);
701 ath9k_hw_txstart(ah, sc->sc_bhalq);
703 sc->ast_be_xmit += bc; /* XXX per-vap? */
709 * Tasklet for Beacon Stuck processing
711 * Processing for Beacon Stuck.
712 * Basically calls the ath_internal_reset function to reset the chip.
715 void ath_bstuck_process(struct ath_softc *sc)
717 DPRINTF(sc, ATH_DBG_BEACON,
718 "%s: stuck beacon; resetting (bmiss count %u)\n",
719 __func__, sc->sc_bmisscount);
720 ath_internal_reset(sc);
724 * Configure the beacon and sleep timers.
726 * When operating as an AP this resets the TSF and sets
727 * up the hardware to notify us when we need to issue beacons.
729 * When operating in station mode this sets up the beacon
730 * timers according to the timestamp of the last received
731 * beacon and the current TSF, configures PCF and DTIM
732 * handling, programs the sleep registers so the hardware
733 * will wakeup in time to receive beacons, and configures
734 * the beacon miss handling so we'll receive a BMISS
735 * interrupt when we stop seeing beacons from the AP
736 * we've associated with.
739 void ath_beacon_config(struct ath_softc *sc, int if_id)
741 #define TSF_TO_TU(_h,_l) \
742 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
743 struct ath_hal *ah = sc->sc_ah;
744 u_int32_t nexttbtt, intval;
745 struct ath_beacon_config conf;
746 enum hal_opmode av_opmode;
748 if (if_id != ATH_IF_ID_ANY)
749 av_opmode = sc->sc_vaps[if_id]->av_opmode;
751 av_opmode = sc->sc_opmode;
753 memzero(&conf, sizeof(struct ath_beacon_config));
755 /* FIXME: Use default values for now - Sujith */
756 /* Query beacon configuration first */
758 * Protocol stack doesn't support dynamic beacon configuration,
759 * use default configurations.
761 conf.beacon_interval = ATH_DEFAULT_BINTVAL;
762 conf.listen_interval = 1;
763 conf.dtim_period = conf.beacon_interval;
765 conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval;
767 /* extract tstamp from last beacon and convert to TU */
768 nexttbtt = TSF_TO_TU(LE_READ_4(conf.u.last_tstamp + 4),
769 LE_READ_4(conf.u.last_tstamp));
770 /* XXX conditionalize multi-bss support? */
771 if (sc->sc_opmode == HAL_M_HOSTAP) {
773 * For multi-bss ap support beacons are either staggered
774 * evenly over N slots or burst together. For the former
775 * arrange for the SWBA to be delivered for each slot.
776 * Slots that are not occupied will generate nothing.
778 /* NB: the beacon interval is kept internally in TU's */
779 intval = conf.beacon_interval & HAL_BEACON_PERIOD;
780 intval /= ATH_BCBUF; /* for staggered beacons */
782 intval = conf.beacon_interval & HAL_BEACON_PERIOD;
785 if (nexttbtt == 0) /* e.g. for ap mode */
787 else if (intval) /* NB: can be 0 for monitor mode */
788 nexttbtt = roundup(nexttbtt, intval);
789 DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
790 __func__, nexttbtt, intval, conf.beacon_interval);
791 /* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
792 if (sc->sc_opmode == HAL_M_STA) {
793 struct hal_beacon_state bs;
796 int dtimperiod, dtimcount, sleepduration;
797 int cfpperiod, cfpcount;
800 * Setup dtim and cfp parameters according to
801 * last beacon we received (which may be none).
803 dtimperiod = conf.dtim_period;
804 if (dtimperiod <= 0) /* NB: 0 if not known */
806 dtimcount = conf.dtim_count;
807 if (dtimcount >= dtimperiod) /* NB: sanity check */
808 dtimcount = 0; /* XXX? */
809 cfpperiod = 1; /* NB: no PCF support yet */
812 sleepduration = conf.listen_interval * intval;
813 if (sleepduration <= 0)
814 sleepduration = intval;
818 * Pull nexttbtt forward to reflect the current
819 * TSF and calculate dtim+cfp state for the result.
821 tsf = ath9k_hw_gettsf64(ah);
822 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
825 if (--dtimcount < 0) {
826 dtimcount = dtimperiod - 1;
828 cfpcount = cfpperiod - 1;
830 } while (nexttbtt < tsftu);
832 memzero(&bs, sizeof(bs));
833 bs.bs_intval = intval;
834 bs.bs_nexttbtt = nexttbtt;
835 bs.bs_dtimperiod = dtimperiod*intval;
836 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
837 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
838 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
839 bs.bs_cfpmaxduration = 0;
841 * Calculate the number of consecutive beacons to miss
842 * before taking a BMISS interrupt. The configuration
843 * is specified in TU so we only need calculate based
844 * on the beacon interval. Note that we clamp the
845 * result to at most 15 beacons.
847 if (sleepduration > intval) {
848 bs.bs_bmissthreshold =
849 conf.listen_interval *
850 ATH_DEFAULT_BMISS_LIMIT / 2;
852 bs.bs_bmissthreshold =
853 howmany(conf.bmiss_timeout, intval);
854 if (bs.bs_bmissthreshold > 15)
855 bs.bs_bmissthreshold = 15;
856 else if (bs.bs_bmissthreshold <= 0)
857 bs.bs_bmissthreshold = 1;
861 * Calculate sleep duration. The configuration is
862 * given in ms. We insure a multiple of the beacon
863 * period is used. Also, if the sleep duration is
864 * greater than the DTIM period then it makes senses
865 * to make it a multiple of that.
870 bs.bs_sleepduration =
871 roundup(IEEE80211_MS_TO_TU(100), sleepduration);
872 if (bs.bs_sleepduration > bs.bs_dtimperiod)
873 bs.bs_sleepduration = bs.bs_dtimperiod;
875 DPRINTF(sc, ATH_DBG_BEACON,
889 , (unsigned long long)tsf, tsftu
894 , bs.bs_bmissthreshold
895 , bs.bs_sleepduration
897 , bs.bs_cfpmaxduration
902 ath9k_hw_set_interrupts(ah, 0);
903 ath9k_hw_set_sta_beacon_timers(ah, &bs);
904 sc->sc_imask |= HAL_INT_BMISS;
905 ath9k_hw_set_interrupts(ah, sc->sc_imask);
909 ath9k_hw_set_interrupts(ah, 0);
910 if (nexttbtt == intval)
911 intval |= HAL_BEACON_RESET_TSF;
912 if (sc->sc_opmode == HAL_M_IBSS) {
914 * Pull nexttbtt forward to reflect the current
918 if (!(intval & HAL_BEACON_RESET_TSF)) {
919 tsf = ath9k_hw_gettsf64(ah);
920 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32),
921 (u_int32_t)tsf) + FUDGE;
924 } while (nexttbtt < tsftu);
927 DPRINTF(sc, ATH_DBG_BEACON,
928 "%s: IBSS nexttbtt %u intval %u (%u)\n",
930 intval & ~HAL_BEACON_RESET_TSF,
931 conf.beacon_interval);
934 * In IBSS mode enable the beacon timers but only
935 * enable SWBA interrupts if we need to manually
936 * prepare beacon frames. Otherwise we use a
937 * self-linked tx descriptor and let the hardware
940 intval |= HAL_BEACON_ENA;
941 if (!ah->ah_caps.halVEOLSupport)
942 sc->sc_imask |= HAL_INT_SWBA;
943 ath_beaconq_config(sc);
944 } else if (sc->sc_opmode == HAL_M_HOSTAP) {
946 * In AP mode we enable the beacon timers and
947 * SWBA interrupts to prepare beacon frames.
949 intval |= HAL_BEACON_ENA;
950 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
951 ath_beaconq_config(sc);
953 ath9k_hw_beaconinit(ah, nexttbtt, intval);
954 sc->sc_bmisscount = 0;
955 ath9k_hw_set_interrupts(ah, sc->sc_imask);
957 * When using a self-linked beacon descriptor in
958 * ibss mode load it once here.
960 if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
961 ath_beacon_start_adhoc(sc, 0);
966 /* Function to collect beacon rssi data and resync beacon if necessary */
968 void ath_beacon_sync(struct ath_softc *sc, int if_id)
971 * Resync beacon timers using the tsf of the
972 * beacon frame we just received.
974 ath_beacon_config(sc, if_id);