ramips: Fix amount of MT7621 pins controlled by spi group
authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 17 Aug 2015 06:15:44 +0000 (06:15 +0000)
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 17 Aug 2015 06:15:44 +0000 (06:15 +0000)
commitf294a464d017861f99eda72b667120cbf3b6eb53
treeaf5fbaa226786a421ee63fee2e8a038ce6d35e58
parent76d38362b817c1c875c3b6114c048d185a88d8f1
ramips: Fix amount of MT7621 pins controlled by spi group

The PINS conntrolled by the SPI bits in the GPIO_MODE register is always
7 and not 8 for nand mode.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46644 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch