kernel: update 3.10 to 3.10.2

[openwrt.git] / target / linux / ramips / patches-3.10 / 0006-MIPS-ralink-add-verbose-pmu-info.patch

diff --git a/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch
index c2d959d..6349bd3 100644 (file)
--- a/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch
+++ b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch
@@ -10,8 +10,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  arch/mips/ralink/mt7620.c |   26 ++++++++++++++++++++++++++
  1 file changed, 26 insertions(+)
 
-diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
-index ccdec5a..62356a0 100644
 --- a/arch/mips/ralink/mt7620.c
 +++ b/arch/mips/ralink/mt7620.c
 @@ -20,6 +20,22 @@
@@ -37,7 +35,7 @@ index ccdec5a..62356a0 100644
  /* does the board have sdram or ddram */
  static int dram_type;
  
-@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_inf
        u32 n1;
        u32 rev;
        u32 cfg0;
@@ -46,7 +44,7 @@ index ccdec5a..62356a0 100644
  
        n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
        n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_inf
                BUG();
        }
        soc_info->mem_base = MT7620_DRAM_BASE;
@@ -59,6 +57,3 @@ index ccdec5a..62356a0 100644
 +      pr_info("Digital PMU set to %s control\n",
 +              (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  }
--- 
-1.7.10.4
-