compatible = "mti,cpu-interrupt-controller";
};
+ aliases {
+ serial0 = &uartlite;
+ };
+
cpuclock: cpuclock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
reg = <0x1fbf8000 0x8000>;
};
- uartlite@c00 {
+ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
sdhci@1E130000 {
compatible = "ralink,mt7620-sdhci";
- reg = <0x1E130000 4000>;
+ reg = <0x1E130000 0x4000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
xhci@1E1C0000 {
status = "okay";
- compatible = "xhci-platform";
- reg = <0x1E1C0000 4000>;
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0x1e1c0000 0x1000
+ 0x1e1d0700 0x0100>;
+
+ clocks = <&sysclock>;
+ clock-names = "sys_ck";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
};
nand@1e003000 {
+ status = "disabled";
+
compatible = "mtk,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
};
ethernet@1e100000 {
- compatible = "ralink,mt7621-eth";
- reg = <0x1e100000 10000>;
+ compatible = "mediatek,mt7621-eth";
+ reg = <0x1e100000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+ mediatek,switch = <&gsw>;
+
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
- gsw@1e110000 {
- compatible = "ralink,mt7620a-gsw";
- reg = <0x1e110000 8000>;
+ gsw: gsw@1e110000 {
+ compatible = "mediatek,mt7621-gsw";
+ reg = <0x1e110000 0x8000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
};