+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,cpu-interrupt-controller";
};
+ aliases {
+ serial0 = &uartlite;
+ };
+
+ cpuclock: cpuclock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+
+ /* FIXME: there should be way to detect this */
+ clock-frequency = <880000000>;
+ };
+
+ sysclock: sysclock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+
+ /* FIXME: there should be way to detect this */
+ clock-frequency = <50000000>;
+ };
+
palmbus@1E000000 {
compatible = "palmbus";
reg = <0x1E000000 0x100000>;
- ranges = <0x0 0x1E000000 0x0FFFFF>;
+ ranges = <0x0 0x1E000000 0x0FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300 0x100>;
};
- uartlite@c00 {
+ cpc@1fbf0000 {
+ compatible = "mtk,mt7621-cpc";
+ reg = <0x1fbf0000 0x8000>;
+ };
+
+ mc@1fbf8000 {
+ compatible = "mtk,mt7621-mc";
+ reg = <0x1fbf8000 0x8000>;
+ };
+
+ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysclock>;
+
interrupt-parent = <&gic>;
- interrupts = <26>;
+ interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
+ clocks = <&sysclock>;
+
resets = <&rstctrl 18>;
reset-names = "spi";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
compatible = "ralink,rt2880-pinmux";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
+
state_default: pinctrl0 {
};
+
spi_pins: spi {
spi {
ralink,group = "spi";
ralink,function = "spi";
};
};
+
i2c_pins: i2c {
i2c {
- lantiq,group = "i2c";
- lantiq,function = "i2c";
+ ralink,group = "i2c";
+ ralink,function = "i2c";
};
};
+
uart1_pins: uart1 {
uart1 {
ralink,group = "uart1";
- ralink,function = "uart";
+ ralink,function = "uart1";
};
};
+
uart2_pins: uart2 {
uart2 {
ralink,group = "uart2";
- ralink,function = "uart";
+ ralink,function = "uart2";
};
};
+
uart3_pins: uart3 {
uart3 {
ralink,group = "uart3";
- ralink,function = "uart";
+ ralink,function = "uart3";
};
};
+
rgmii1_pins: rgmii1 {
rgmii1 {
ralink,group = "rgmii1";
- ralink,function = "rgmii";
+ ralink,function = "rgmii1";
};
};
+
rgmii2_pins: rgmii2 {
rgmii2 {
ralink,group = "rgmii2";
- ralink,function = "rgmii";
+ ralink,function = "rgmii2";
};
};
+
mdio_pins: mdio {
mdio {
ralink,group = "mdio";
ralink,function = "mdio";
};
};
+
pcie_pins: pcie {
pcie {
ralink,group = "pcie";
ralink,function = "pcie rst";
};
};
+
nand_pins: nand {
spi-nand {
ralink,group = "spi";
- ralink,function = "nand";
+ ralink,function = "nand1";
};
+
sdhci-nand {
ralink,group = "sdhci";
- ralink,function = "nand";
+ ralink,function = "nand2";
};
};
+
sdhci_pins: sdhci {
sdhci {
ralink,group = "sdhci";
sdhci@1E130000 {
compatible = "ralink,mt7620-sdhci";
- reg = <0x1E130000 4000>;
+ reg = <0x1E130000 0x4000>;
interrupt-parent = <&gic>;
- interrupts = <20>;
+ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
};
xhci@1E1C0000 {
- status = "disabled";
+ status = "okay";
- compatible = "xhci-platform";
- reg = <0x1E1C0000 4000>;
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0x1e1c0000 0x1000
+ 0x1e1d0700 0x0100>;
+
+ clocks = <&sysclock>;
+ clock-names = "sys_ck";
interrupt-parent = <&gic>;
- interrupts = <22>;
+ interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
};
- gic: gic@1fbc0000 {
- #address-cells = <0>;
- #interrupt-cells = <1>;
+ gic: interrupt-controller@1fbc0000 {
+ compatible = "mti,gic";
+ reg = <0x1fbc0000 0x2000>;
+
interrupt-controller;
- compatible = "ralink,mt7621-gic";
- reg = < 0x1fbc0000 0x80 /* gic */
- 0x1fbf0000 0x8000 /* cpc */
- 0x1fbf8000 0x8000 /* gpmc */
- >;
+ #interrupt-cells = <3>;
+
+ mti,reserved-cpu-vectors = <7>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&cpuclock>;
+ };
};
nand@1e003000 {
+ status = "disabled";
+
compatible = "mtk,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
#address-cells = <1>;
#size-cells = <1>;
-
- partition@0 {
- label = "uboot";
- reg = <0x00000 0x80000>; /* 64 KB */
- };
- partition@80000 {
- label = "uboot_env";
- reg = <0x80000 0x80000>; /* 64 KB */
- };
- partition@100000 {
- label = "factory";
- reg = <0x100000 0x40000>;
- };
- partition@140000 {
- label = "rootfs";
- reg = <0x140000 0xec0000>;
- };
};
ethernet@1e100000 {
- compatible = "ralink,mt7621-eth";
- reg = <0x1e100000 10000>;
+ compatible = "mediatek,mt7621-eth";
+ reg = <0x1e100000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rstctrl 6 &rstctrl 23>;
+ reset-names = "fe", "eth";
+
interrupt-parent = <&gic>;
- interrupts = <3>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+ mediatek,switch = <&gsw>;
mdio-bus {
#address-cells = <1>;
};
};
- gsw@1e110000 {
- compatible = "ralink,mt7620a-gsw";
- reg = <0x1e110000 8000>;
+ gsw: gsw@1e110000 {
+ compatible = "mediatek,mt7621-gsw";
+ reg = <0x1e110000 0x8000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie@1e140000 {
+ compatible = "mediatek,mt7621-pci";
+ reg = <0x1e140000 0x100
+ 0x1e142000 0x100>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+
+ device_type = "pci";
+
+ bus-range = <0 255>;
+ ranges = <
+ 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
+ 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
+ >;
+
interrupt-parent = <&gic>;
- interrupts = <23>;
+ interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
+ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
+ GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "okay";
+
+ pcie0 {
+ reg = <0x0000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ };
+
+ pcie1 {
+ reg = <0x0800 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ };
+
+ pcie2 {
+ reg = <0x1000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ };
};
};
projects / openwrt.git / blobdiff