ramips: introduce serial0 aliases
[openwrt.git] / target / linux / ramips / dts / mt7620a.dtsi
index 37b6560..3c89880 100644 (file)
                compatible = "mti,cpu-interrupt-controller";
        };
 
+       aliases {
+               spi0 = &spi0;
+               spi1 = &spi1;
+               serial0 = &uartlite;
+       };
+
        palmbus@10000000 {
                compatible = "palmbus";
                reg = <0x10000000 0x200000>;
-                ranges = <0x0 0x10000000 0x1FFFFF>;
+               ranges = <0x0 0x10000000 0x1FFFFF>;
 
                #address-cells = <1>;
                #size-cells = <1>;
                        status = "disabled";
                };
 
-               spi@b00 {
+               spi0: spi@b00 {
                        compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
-                       reg = <0xb00 0x100>;
+                       reg = <0xb00 0x40>;
 
                        resets = <&rstctrl 18>;
                        reset-names = "spi";
 
                        #address-cells = <1>;
-                       #size-cells = <1>;
+                       #size-cells = <0>;
 
                        status = "disabled";
 
                        pinctrl-0 = <&spi_pins>;
                };
 
-               uartlite@c00 {
+               spi1: spi@b40 {
+                       compatible = "ralink,rt2880-spi";
+                       reg = <0xb40 0x60>;
+
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       status = "disabled";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi_cs1>;
+               };
+
+               uartlite: uartlite@c00 {
                        compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
 
                compatible = "ralink,rt2880-pinmux";
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
+
                state_default: pinctrl0 {
                };
+
                pcm_i2s_pins: pcm_i2s {
                        pcm_i2s {
                                ralink,group = "uartf";
                                ralink,function = "pcm i2s";
                        };
                };
+
                uartf_gpio_pins: uartf_gpio {
                        uartf_gpio {
                                ralink,group = "uartf";
                                ralink,function = "gpio uartf";
                        };
                };
+
                spi_pins: spi {
                        spi {
                                ralink,group = "spi";
                                ralink,function = "spi";
                        };
                };
+
+               spi_cs1: spi1 {
+                       spi1 {
+                               ralink,group = "spi_cs1";
+                               ralink,function = "spi_cs1";
+                       };
+               };
+
                i2c_pins: i2c {
                        i2c {
-                               lantiq,group = "i2c";
-                               lantiq,function = "i2c";
+                               ralink,group = "i2c";
+                               ralink,function = "i2c";
                        };
                };
+
                uartlite_pins: uartlite {
                        uart {
                                ralink,group = "uartlite";
                                ralink,function = "uartlite";
                        };
                };
+
                mdio_pins: mdio {
                        mdio {
                                ralink,group = "mdio";
                                ralink,function = "mdio";
                        };
                };
+
                ephy_pins: ephy {
                        ephy {
                                ralink,group = "ephy";
                                ralink,function = "ephy";
                        };
                };
+
                wled_pins: wled {
                        wled {
                                ralink,group = "wled";
                                ralink,function = "wled";
                        };
                };
+
                rgmii1_pins: rgmii1 {
                        rgmii1 {
                                ralink,group = "rgmii1";
                                ralink,function = "rgmii1";
                        };
                };
+
                rgmii2_pins: rgmii2 {
                        rgmii2 {
                                ralink,group = "rgmii2";
                                ralink,function = "rgmii2";
                        };
                };
+
+               pcie_pins: pcie {
+                       pcie {
+                               ralink,group = "pcie";
+                               ralink,function = "pcie rst";
+                       };
+               };
        };
 
        rstctrl: rstctrl {
                #reset-cells = <1>;
        };
 
-       usbphy {
-               compatible = "ralink,mt7620a-usbphy";
+       usbphy: usbphy {
+               compatible = "mediatek,mt7620-usbphy";
+               #phy-cells = <1>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
        };
 
        ethernet@10100000 {
-               compatible = "ralink,mt7620a-eth";
+               compatible = "mediatek,mt7620-eth";
                reg = <0x10100000 10000>;
 
                #address-cells = <1>;
                resets = <&rstctrl 21 &rstctrl 23>;
                reset-names = "fe", "esw";
 
+               mediatek,switch = <&gsw>;
+
                port@4 {
-                       compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+                       compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
                        reg = <4>;
 
                        status = "disabled";
                };
 
                port@5 {
-                       compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+                       compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
                        reg = <5>;
 
                        status = "disabled";
                };
        };
 
-       gsw@10110000 {
-               compatible = "ralink,mt7620a-gsw";
+       gsw: gsw@10110000 {
+               compatible = "mediatek,mt7620-gsw";
                reg = <0x10110000 8000>;
 
+               resets = <&rstctrl 23>;
+               reset-names = "esw";
+
                interrupt-parent = <&intc>;
                interrupts = <17>;
        };
 
        sdhci@10130000 {
-               compatible = "ralink,mt7620a-sdhci";
+               compatible = "ralink,mt7620-sdhci";
                reg = <0x10130000 4000>;
 
                interrupt-parent = <&intc>;
        };
 
        ehci@101c0000 {
-               compatible = "ralink,rt3xxx-ehci";
+               compatible = "generic-ehci";
                reg = <0x101c0000 0x1000>;
 
                interrupt-parent = <&intc>;
                interrupts = <18>;
 
+               phys = <&usbphy 1>;
+               phy-names = "usb";
+
                status = "disabled";
        };
 
        ohci@101c1000 {
-               compatible = "ralink,rt3xxx-ohci";
+               compatible = "generic-ohci";
                reg = <0x101c1000 0x1000>;
 
                interrupt-parent = <&intc>;
                interrupts = <18>;
 
+               phys = <&usbphy 1>;
+               phy-names = "usb";
+
                status = "disabled";
        };
 
                interrupt-parent = <&cpuintc>;
                interrupts = <4>;
 
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie_pins>;
+
+               device_type = "pci";
+
+               bus-range = <0 255>;
+               ranges = <
+                       0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
+                       0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
+               >;
+
                status = "disabled";
 
                pcie-bridge {