kernel: update bcma and ssb to master-2012-10-18 from wireless-testing
[openwrt.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
index e427574..10c70ab 100644 (file)
 +}
 --- a/drivers/ssb/driver_mipscore.c
 +++ b/drivers/ssb/driver_mipscore.c
-@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
+ {
+       struct ssb_bus *bus = mcore->dev->bus;
+-      mcore->flash_buswidth = 2;
+-      if (bus->chipco.dev) {
+-              mcore->flash_window = 0x1c000000;
+-              mcore->flash_window_size = 0x02000000;
++      /* When there is no chipcommon on the bus there is 4MB flash */
++      if (!bus->chipco.dev) {
++              mcore->pflash.present = true;
++              mcore->pflash.buswidth = 2;
++              mcore->pflash.window = SSB_FLASH1;
++              mcore->pflash.window_size = SSB_FLASH1_SZ;
++              return;
++      }
++
++      /* There is ChipCommon, so use it to read info about flash */
++      switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
++      case SSB_CHIPCO_FLASHT_STSER:
++      case SSB_CHIPCO_FLASHT_ATSER:
++              pr_err("Serial flash not supported\n");
++              break;
++      case SSB_CHIPCO_FLASHT_PARA:
++              pr_debug("Found parallel flash\n");
++              mcore->pflash.present = true;
++              mcore->pflash.window = SSB_FLASH2;
++              mcore->pflash.window_size = SSB_FLASH2_SZ;
+               if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
+                              & SSB_CHIPCO_CFG_DS16) == 0)
+-                      mcore->flash_buswidth = 1;
+-      } else {
+-              mcore->flash_window = 0x1fc00000;
+-              mcore->flash_window_size = 0x00400000;
++                      mcore->pflash.buswidth = 1;
++              else
++                      mcore->pflash.buswidth = 2;
++              break;
+       }
+ }
+@@ -208,6 +224,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
        struct ssb_bus *bus = mcore->dev->bus;
        u32 pll_type, n, m, rate = 0;
  
  
  /* Vendor-ID values */
  #define SSB_VENDOR_BROADCOM   0x4243
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -504,7 +504,9 @@
+ #define SSB_CHIPCO_FLASHCTL_ST_SE     0x02D8          /* Sector Erase */
+ #define SSB_CHIPCO_FLASHCTL_ST_BE     0x00C7          /* Bulk Erase */
+ #define SSB_CHIPCO_FLASHCTL_ST_DP     0x00B9          /* Deep Power-down */
+-#define SSB_CHIPCO_FLASHCTL_ST_RSIG   0x03AB          /* Read Electronic Signature */
++#define SSB_CHIPCO_FLASHCTL_ST_RES    0x03AB          /* Read Electronic Signature */
++#define SSB_CHIPCO_FLASHCTL_ST_CSA    0x1000          /* Keep chip select asserted */
++#define SSB_CHIPCO_FLASHCTL_ST_SSE    0x0220          /* Sub-sector Erase */
+ /* Status register bits for ST flashes */
+ #define SSB_CHIPCO_FLASHSTA_ST_WIP    0x01            /* Write In Progress */
 --- a/include/linux/ssb/ssb_driver_gige.h
 +++ b/include/linux/ssb/ssb_driver_gige.h
 @@ -2,6 +2,7 @@
  #include <linux/pci.h>
  #include <linux/spinlock.h>
  
+--- a/include/linux/ssb/ssb_driver_mips.h
++++ b/include/linux/ssb/ssb_driver_mips.h
+@@ -13,6 +13,12 @@ struct ssb_serial_port {
+       unsigned int reg_shift;
+ };
++struct ssb_pflash {
++      bool present;
++      u8 buswidth;
++      u32 window;
++      u32 window_size;
++};
+ struct ssb_mipscore {
+       struct ssb_device *dev;
+@@ -20,9 +26,7 @@ struct ssb_mipscore {
+       int nr_serial_ports;
+       struct ssb_serial_port serial_ports[4];
+-      u8 flash_buswidth;
+-      u32 flash_window;
+-      u32 flash_window_size;
++      struct ssb_pflash pflash;
+ };
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
 --- a/include/linux/ssb/ssb_regs.h
 +++ b/include/linux/ssb/ssb_regs.h
 @@ -228,6 +228,7 @@