struct ar8216_priv {
struct switch_dev dev;
+ struct mii_bus *mii_bus;
struct phy_device *phy;
u32 (*read)(struct ar8216_priv *priv, int reg);
void (*write)(struct ar8216_priv *priv, int reg, u32 val);
.name = (_n), \
}
+static const struct ar8xxx_mib_desc ar8216_mibs[] = {
+ MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
+ MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
+ MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
+};
+
static const struct ar8xxx_mib_desc ar8236_mibs[] = {
MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
};
-#define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
+static inline struct ar8216_priv *
+swdev_to_ar8216(struct switch_dev *swdev)
+{
+ return container_of(swdev, struct ar8216_priv, dev);
+}
static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
{
static u32
ar8216_mii_read(struct ar8216_priv *priv, int reg)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
u16 lo, hi;
static void
ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, r3;
u16 lo, hi;
ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
u16 dbg_addr, u16 dbg_data)
{
- struct mii_bus *bus = priv->phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
static void
ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
{
- struct mii_bus *bus = priv->phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
}
static int
-ar8216_mib_capture(struct ar8216_priv *priv)
+ar8216_mib_op(struct ar8216_priv *priv, u32 op)
{
unsigned mib_func;
int ret;
else
mib_func = AR8216_REG_MIB_FUNC;
+ mutex_lock(&priv->reg_mutex);
/* Capture the hardware statistics for all ports */
- ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
- (AR8216_MIB_FUNC_CAPTURE << AR8216_MIB_FUNC_S));
+ ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
+ mutex_unlock(&priv->reg_mutex);
/* Wait for the capturing to complete. */
ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
}
static int
-ar8216_mib_flush(struct ar8216_priv *priv)
+ar8216_mib_capture(struct ar8216_priv *priv)
{
- unsigned mib_func;
- int ret;
-
- lockdep_assert_held(&priv->mib_lock);
-
- if (chip_is_ar8327(priv))
- mib_func = AR8327_REG_MIB_FUNC;
- else
- mib_func = AR8216_REG_MIB_FUNC;
-
- /* Flush hardware statistics for all ports */
- ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
- (AR8216_MIB_FUNC_FLUSH << AR8216_MIB_FUNC_S));
-
- /* Wait for the capturing to complete. */
- ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
- if (ret)
- goto out;
-
- ret = 0;
+ return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
+}
-out:
- return ret;
+static int
+ar8216_mib_flush(struct ar8216_priv *priv)
+{
+ return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
}
static void
u64 *mib_stats;
int i;
+ WARN_ON(port >= priv->dev.ports);
+
lockdep_assert_held(&priv->mib_lock);
if (chip_is_ar8327(priv))
base = AR8327_REG_PORT_STATS_BASE(port);
- else
+ else if (chip_is_ar8236(priv) ||
+ chip_is_ar8316(priv))
base = AR8236_REG_PORT_STATS_BASE(port);
+ else
+ base = AR8216_REG_PORT_STATS_BASE(port);
mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
for (i = 0; i < priv->chip->num_mibs; i++) {
}
static const struct ar8xxx_chip ar8216_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
.hw_init = ar8216_hw_init,
.init_globals = ar8216_init_globals,
.init_port = ar8216_init_port,
.atu_flush = ar8216_atu_flush,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
+
+ .num_mibs = ARRAY_SIZE(ar8216_mibs),
+ .mib_decs = ar8216_mibs,
};
static void
return 0;
/* Initialize the PHYs */
- bus = priv->phy->bus;
+ bus = priv->mii_bus;
for (i = 0; i < 5; i++) {
mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
u32 val, newval;
struct mii_bus *bus;
- val = priv->read(priv, 0x8);
+ val = priv->read(priv, AR8316_REG_POSTRIP);
if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
if (priv->port4_phy) {
if (val == newval)
goto out;
- priv->write(priv, 0x8, newval);
+ priv->write(priv, AR8316_REG_POSTRIP, newval);
/* Initialize the ports */
- bus = priv->phy->bus;
+ bus = priv->mii_bus;
for (i = 0; i < 5; i++) {
if ((i == 4) && priv->port4_phy &&
priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- msleep(1000);
}
+ msleep(1000);
+
out:
priv->initialized = true;
return 0;
case AR8327_PAD_MAC_SGMII:
t = AR8327_PAD_SGMII_EN;
+
+ /*
+ * WAR for the QUalcomm Atheros AP136 board.
+ * It seems that RGMII TX/RX delay settings needs to be
+ * applied for SGMII mode as well, The ethernet is not
+ * reliable without this.
+ */
+ t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
+ t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
+ if (cfg->rxclk_delay_en)
+ t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
+ if (cfg->txclk_delay_en)
+ t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
+
+ if (cfg->sgmii_delay_en)
+ t |= AR8327_PAD_SGMII_DELAY_EN;
+
break;
case AR8327_PAD_MAC2PHY_MII:
priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
}
- bus = priv->phy->bus;
+ bus = priv->mii_bus;
for (i = 0; i < AR8327_NUM_PHYS; i++) {
ar8327_phy_fixup(priv, i);
}
static void
-ar8327_init_cpuport(struct ar8216_priv *priv)
+ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
+ struct ar8327_port_cfg *cfg)
{
- struct ar8327_platform_data *pdata;
- struct ar8327_port_cfg *cfg;
u32 t;
- pdata = priv->phy->dev.platform_data;
- if (!pdata)
- return;
-
- cfg = &pdata->cpuport_cfg;
- if (!cfg->force_link) {
- priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
+ if (!cfg || !cfg->force_link) {
+ priv->write(priv, AR8327_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_AUTO);
return;
}
t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
+
switch (cfg->speed) {
case AR8327_PORT_SPEED_10:
t |= AR8216_PORT_SPEED_10M;
break;
}
- priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
+ priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
}
static void
ar8327_init_port(struct ar8216_priv *priv, int port)
{
+ struct ar8327_platform_data *pdata;
+ struct ar8327_port_cfg *cfg;
u32 t;
- if (port == AR8216_PORT_CPU) {
- ar8327_init_cpuport(priv);
- } else {
- t = AR8216_PORT_STATUS_LINK_AUTO;
- priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
- }
+ pdata = priv->phy->dev.platform_data;
+
+ if (pdata && port == AR8216_PORT_CPU)
+ cfg = &pdata->port0_cfg;
+ else if (pdata && port == 6)
+ cfg = &pdata->port6_cfg;
+ else
+ cfg = NULL;
+
+ ar8327_config_port(priv, port, cfg);
priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
- priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
+ t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
+ t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
+ priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
priv->vlan = !!val->value.i;
return 0;
}
ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
val->value.i = priv->vlan;
return 0;
}
static int
ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
/* make sure no invalid PVIDs get set */
static int
ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
*vlan = priv->pvid[port];
return 0;
}
ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
priv->vlan_id[val->port_vlan] = val->value.i;
return 0;
}
ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
val->value.i = priv->vlan_id[val->port_vlan];
return 0;
}
ar8216_sw_get_port_link(struct switch_dev *dev, int port,
struct switch_port_link *link)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
ar8216_read_port_link(priv, port, link);
return 0;
static int
ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
u8 ports = priv->vlan_table[val->port_vlan];
int i;
static int
ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
u8 *vt = &priv->vlan_table[val->port_vlan];
int i, j;
static int
ar8216_sw_hw_apply(struct switch_dev *dev)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
u8 portmask[AR8X16_MAX_PORTS];
int i, j;
static int
ar8216_sw_reset_switch(struct switch_dev *dev)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
int i;
mutex_lock(&priv->reg_mutex);
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
unsigned int len;
int ret;
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
int port;
int ret;
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
const struct ar8xxx_chip *chip = priv->chip;
u64 *mib_stats;
int port;
goto unlock;
ar8216_mib_fetch_port_stat(priv, port, false);
- mutex_unlock(&priv->mib_lock);
len += snprintf(buf + len, sizeof(priv->buf) - len,
"Port %d MIB counters\n",
u16 id;
int i;
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = priv->read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
u16 t;
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = priv->read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
break;
default:
printk(KERN_DEBUG
- "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
- priv->chip_ver, priv->chip_rev,
- mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
- mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
+ "ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
+ priv->chip_ver, priv->chip_rev);
return -ENODEV;
}
next_port:
priv->mib_next_port++;
- if (priv->mib_next_port > priv->dev.ports)
+ if (priv->mib_next_port >= priv->dev.ports)
priv->mib_next_port = 0;
mutex_unlock(&priv->mib_lock);
if (!priv->mib_stats)
return -ENOMEM;
- mutex_init(&priv->mib_lock);
- INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
-
return 0;
}
}
static void
-ar8xxx_mib_cleanup(struct ar8216_priv *priv)
+ar8xxx_mib_stop(struct ar8216_priv *priv)
{
if (!ar8xxx_has_mib_counters(priv))
return;
cancel_delayed_work(&priv->mib_work);
+}
+
+static struct ar8216_priv *
+ar8xxx_create(void)
+{
+ struct ar8216_priv *priv;
+
+ priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
+ if (priv == NULL)
+ return NULL;
+
+ mutex_init(&priv->reg_mutex);
+ mutex_init(&priv->mib_lock);
+ INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
+
+ return priv;
+}
+
+static void
+ar8xxx_free(struct ar8216_priv *priv)
+{
kfree(priv->mib_stats);
+ kfree(priv);
+}
+
+static struct ar8216_priv *
+ar8xxx_create_mii(struct mii_bus *bus)
+{
+ struct ar8216_priv *priv;
+
+ priv = ar8xxx_create();
+ if (priv) {
+ priv->mii_bus = bus;
+ priv->read = ar8216_mii_read;
+ priv->write = ar8216_mii_write;
+ }
+
+ return priv;
+}
+
+static int
+ar8xxx_probe_switch(struct ar8216_priv *priv)
+{
+ struct switch_dev *swdev;
+ int ret;
+
+ ret = ar8216_id_chip(priv);
+ if (ret)
+ return ret;
+
+ swdev = &priv->dev;
+ swdev->cpu_port = AR8216_PORT_CPU;
+ swdev->ops = &ar8216_sw_ops;
+
+ if (chip_is_ar8316(priv)) {
+ swdev->name = "Atheros AR8316";
+ swdev->vlans = AR8X16_MAX_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
+ } else if (chip_is_ar8236(priv)) {
+ swdev->name = "Atheros AR8236";
+ swdev->vlans = AR8216_NUM_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
+ } else if (chip_is_ar8327(priv)) {
+ swdev->name = "Atheros AR8327";
+ swdev->vlans = AR8X16_MAX_VLANS;
+ swdev->ports = AR8327_NUM_PORTS;
+ } else {
+ swdev->name = "Atheros AR8216";
+ swdev->vlans = AR8216_NUM_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
+ }
+
+ ret = ar8xxx_mib_init(priv);
+ if (ret)
+ return ret;
+
+ return 0;
}
static int
int ret;
if (!priv) {
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
+ priv = ar8xxx_create_mii(pdev->bus);
if (priv == NULL)
return -ENOMEM;
+
+ ret = ar8xxx_probe_switch(priv);
+ if (ret)
+ goto err_free_priv;
}
priv->phy = pdev;
- ret = ar8216_id_chip(priv);
- if (ret)
- goto err_free_priv;
+ if (ar8xxx_has_gige(priv))
+ pdev->supported = SUPPORTED_1000baseT_Full;
+ else
+ pdev->supported = SUPPORTED_100baseT_Full;
+ pdev->advertising = pdev->supported;
if (pdev->addr != 0) {
- if (ar8xxx_has_gige(priv)) {
- pdev->supported |= SUPPORTED_1000baseT_Full;
- pdev->advertising |= ADVERTISED_1000baseT_Full;
- }
-
if (chip_is_ar8316(priv)) {
/* check if we're attaching to the switch twice */
pdev = pdev->bus->phy_map[0];
if (!pdev) {
- kfree(priv);
+ ar8xxx_free(priv);
return 0;
}
/* switch device has not been initialized, reuse priv */
if (!pdev->priv) {
priv->port4_phy = true;
+ priv->dev.ports = (AR8216_NUM_PORTS - 1);
pdev->priv = priv;
return 0;
}
- kfree(priv);
+ ar8xxx_free(priv);
/* switch device has been initialized, reinit */
priv = pdev->priv;
return 0;
}
- kfree(priv);
+ ar8xxx_free(priv);
return 0;
}
- if (ar8xxx_has_gige(priv))
- pdev->supported = SUPPORTED_1000baseT_Full;
- else
- pdev->supported = SUPPORTED_100baseT_Full;
- pdev->advertising = pdev->supported;
-
- mutex_init(&priv->reg_mutex);
- priv->read = ar8216_mii_read;
- priv->write = ar8216_mii_write;
-
pdev->priv = priv;
swdev = &priv->dev;
- swdev->cpu_port = AR8216_PORT_CPU;
- swdev->ops = &ar8216_sw_ops;
- swdev->ports = AR8216_NUM_PORTS;
-
- if (chip_is_ar8316(priv)) {
- swdev->name = "Atheros AR8316";
- swdev->vlans = AR8X16_MAX_VLANS;
-
- if (priv->port4_phy) {
- /* port 5 connected to the other mac, therefore unusable */
- swdev->ports = (AR8216_NUM_PORTS - 1);
- }
- } else if (chip_is_ar8236(priv)) {
- swdev->name = "Atheros AR8236";
- swdev->vlans = AR8216_NUM_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
- } else if (chip_is_ar8327(priv)) {
- swdev->name = "Atheros AR8327";
- swdev->vlans = AR8X16_MAX_VLANS;
- swdev->ports = AR8327_NUM_PORTS;
- } else {
- swdev->name = "Atheros AR8216";
- swdev->vlans = AR8216_NUM_VLANS;
- }
-
- ret = ar8xxx_mib_init(priv);
+ ret = register_switch(swdev, pdev->attached_dev);
if (ret)
goto err_free_priv;
- ret = register_switch(&priv->dev, pdev->attached_dev);
- if (ret)
- goto err_cleanup_mib;
-
printk(KERN_INFO "%s: %s switch driver attached.\n",
pdev->attached_dev->name, swdev->name);
ret = priv->chip->hw_init(priv);
if (ret)
- goto err_cleanup_mib;
+ goto err_unregister_switch;
ret = ar8216_sw_reset_switch(&priv->dev);
if (ret)
- goto err_cleanup_mib;
-
- dev->phy_ptr = priv;
+ goto err_unregister_switch;
/* VID fixup only needed on ar8216 */
- if (chip_is_ar8216(priv) && pdev->addr == 0) {
+ if (chip_is_ar8216(priv)) {
+ dev->phy_ptr = priv;
dev->priv_flags |= IFF_NO_IP_ALIGN;
dev->eth_mangle_rx = ar8216_mangle_rx;
dev->eth_mangle_tx = ar8216_mangle_tx;
return 0;
-err_cleanup_mib:
- ar8xxx_mib_cleanup(priv);
+err_unregister_switch:
+ unregister_switch(&priv->dev);
err_free_priv:
- kfree(priv);
+ ar8xxx_free(priv);
+ pdev->priv = NULL;
return ret;
}
return genphy_config_aneg(phydev);
}
+static const u32 ar8xxx_phy_ids[] = {
+ 0x004dd033,
+ 0x004dd041,
+ 0x004dd042,
+};
+
+static bool
+ar8xxx_phy_match(u32 phy_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
+ if (phy_id == ar8xxx_phy_ids[i])
+ return true;
+
+ return false;
+}
+
+static bool
+ar8xxx_is_possible(struct mii_bus *bus)
+{
+ unsigned i;
+
+ for (i = 0; i < 4; i++) {
+ u32 phy_id;
+
+ phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
+ phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
+ if (!ar8xxx_phy_match(phy_id)) {
+ pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
+ dev_name(&bus->dev), i, phy_id);
+ return false;
+ }
+ }
+
+ return true;
+}
+
static int
ar8216_probe(struct phy_device *pdev)
{
struct ar8216_priv *priv;
int ret;
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
+ /* skip PHYs at unused adresses */
+ if (pdev->addr != 0 && pdev->addr != 4)
+ return -ENODEV;
+
+ if (!ar8xxx_is_possible(pdev->bus))
+ return -ENODEV;
+
+ priv = ar8xxx_create_mii(pdev->bus);
if (priv == NULL)
return -ENOMEM;
priv->phy = pdev;
- ret = ar8216_id_chip(priv);
- kfree(priv);
+ ret = ar8xxx_probe_switch(priv);
+ ar8xxx_free(priv);
return ret;
}
static void
-ar8216_remove(struct phy_device *pdev)
+ar8216_detach(struct phy_device *pdev)
{
- struct ar8216_priv *priv = pdev->priv;
struct net_device *dev = pdev->attached_dev;
- if (!priv)
+ if (!dev)
return;
+ dev->phy_ptr = NULL;
dev->priv_flags &= ~IFF_NO_IP_ALIGN;
dev->eth_mangle_rx = NULL;
dev->eth_mangle_tx = NULL;
+}
+
+static void
+ar8216_remove(struct phy_device *pdev)
+{
+ struct ar8216_priv *priv = pdev->priv;
+
+ if (!priv)
+ return;
+
+ pdev->priv = NULL;
if (pdev->addr == 0)
unregister_switch(&priv->dev);
- ar8xxx_mib_cleanup(priv);
- kfree(priv);
+ ar8xxx_mib_stop(priv);
+ ar8xxx_free(priv);
}
static struct phy_driver ar8216_driver = {
.features = PHY_BASIC_FEATURES,
.probe = ar8216_probe,
.remove = ar8216_remove,
+ .detach = ar8216_detach,
.config_init = &ar8216_config_init,
.config_aneg = &ar8216_config_aneg,
.read_status = &ar8216_read_status,
projects / openwrt.git / blobdiff