generic: ar8216: don't use 0 as default VID on AR8327

[openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c

diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c
index 8f3aded..8dcaf0a 100644 (file)
--- a/target/linux/generic/files/drivers/net/phy/ar8216.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.c
@@ -903,6 +903,20 @@ ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 
        case AR8327_PAD_MAC_SGMII:
                t = AR8327_PAD_SGMII_EN;
+
+               /*
+                * WAR for the QUalcomm Atheros AP136 board.
+                * It seems that RGMII TX/RX delay settings needs to be
+                * applied for SGMII mode as well, The ethernet is not
+                * reliable without this.
+                */
+               t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
+               t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
+               if (cfg->rxclk_delay_en)
+                       t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
+               if (cfg->txclk_delay_en)
+                       t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
+
                break;
 
        case AR8327_PAD_MAC2PHY_MII:
@@ -1060,19 +1074,13 @@ ar8327_init_globals(struct ar8216_priv *priv)
 }
 
 static void
-ar8327_init_cpuport(struct ar8216_priv *priv)
+ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
+                   struct ar8327_port_cfg *cfg)
 {
-       struct ar8327_platform_data *pdata;
-       struct ar8327_port_cfg *cfg;
        u32 t;
 
-       pdata = priv->phy->dev.platform_data;
-       if (!pdata)
-               return;
-
-       cfg = &pdata->cpuport_cfg;
-       if (!cfg->force_link) {
-               priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
+       if (!cfg || !cfg->force_link) {
+               priv->write(priv, AR8327_REG_PORT_STATUS(port),
                            AR8216_PORT_STATUS_LINK_AUTO);
                return;
        }
@@ -1081,6 +1089,7 @@ ar8327_init_cpuport(struct ar8216_priv *priv)
        t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
        t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
        t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
+
        switch (cfg->speed) {
        case AR8327_PORT_SPEED_10:
                t |= AR8216_PORT_SPEED_10M;
@@ -1093,24 +1102,32 @@ ar8327_init_cpuport(struct ar8216_priv *priv)
                break;
        }
 
-       priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
+       priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
 }
 
 static void
 ar8327_init_port(struct ar8216_priv *priv, int port)
 {
+       struct ar8327_platform_data *pdata;
+       struct ar8327_port_cfg *cfg;
        u32 t;
 
-       if (port == AR8216_PORT_CPU) {
-               ar8327_init_cpuport(priv);
-       } else {
-               t = AR8216_PORT_STATUS_LINK_AUTO;
-               priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
-       }
+       pdata = priv->phy->dev.platform_data;
 
+       if (pdata && port == AR8216_PORT_CPU)
+               cfg = &pdata->port0_cfg;
+       else if (pdata && port == 6)
+               cfg = &pdata->port6_cfg;
+       else
+               cfg = NULL;
+
+       ar8327_config_port(priv, port, cfg);
+       
        priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
 
-       priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
+       t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
+       t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
+       priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
 
        t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
        priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);