atheros: parenthesis around complex macroses value

[openwrt.git] / target / linux / atheros / patches-3.10 / 100-board.patch

diff --git a/target/linux/atheros/patches-3.10/100-board.patch b/target/linux/atheros/patches-3.10/100-board.patch
index a0dd618..4f7b072 100644 (file)
--- a/target/linux/atheros/patches-3.10/100-board.patch
+++ b/target/linux/atheros/patches-3.10/100-board.patch
@@ -726,11 +726,11 @@
 +/*
 + * IRQs
 + */
-+#define AR2315_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR2315_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR2315_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR2315_IRQ_LCBUS_PCI    MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR2315_IRQ_WLAN0_POLL   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR2315_IRQ_MISC_INTRS   (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0_INTRS  (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0_INTRS  (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI    (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL   (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
 +
 +/*
 + * Address map
@@ -1309,11 +1309,11 @@
 + * IRQs
 + */
 +
-+#define AR5312_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR5312_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR5312_IRQ_ENET1_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR5312_IRQ_WLAN1_INTRS  MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR5312_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR5312_IRQ_WLAN0_INTRS  (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0_INTRS  (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1_INTRS  (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1_INTRS  (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC_INTRS   (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
 +
 +
 +/* Address Map */
@@ -1403,14 +1403,14 @@
 +#define AR531X_RESET_WDOG       0x00100000  /* last reset was a watchdog */
 +
 +#define AR531X_RESET_WMAC0_BITS \
-+        AR531X_RESET_WLAN0 |\
-+        AR531X_RESET_WARM_WLAN0_MAC |\
-+        AR531X_RESET_WARM_WLAN0_BB
++      (AR531X_RESET_WLAN0 |\
++       AR531X_RESET_WARM_WLAN0_MAC |\
++       AR531X_RESET_WARM_WLAN0_BB)
 +
 +#define AR531X_RESERT_WMAC1_BITS \
-+        AR531X_RESET_WLAN1 |\
-+        AR531X_RESET_WARM_WLAN1_MAC |\
-+        AR531X_RESET_WARM_WLAN1_BB
++      (AR531X_RESET_WLAN1 |\
++       AR531X_RESET_WARM_WLAN1_MAC |\
++       AR531X_RESET_WARM_WLAN1_BB)
 +
 +/* AR5312_CLOCKCTL1 register bit field definitions */
 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK    0x00000030
@@ -2894,25 +2894,25 @@
 +#define AR531X_GPIO_IRQ_BASE          0x30
 +
 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR531X_IRQ_NONE               MIPS_CPU_IRQ_BASE+0
-+#define AR531X_IRQ_CPU_CLOCK  MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
++#define AR531X_IRQ_NONE               (MIPS_CPU_IRQ_BASE+0)
++#define AR531X_IRQ_CPU_CLOCK  (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
 +
 +/* Miscellaneous interrupts, which share IP6 */
-+#define AR531X_MISC_IRQ_NONE          AR531X_MISC_IRQ_BASE+0
-+#define AR531X_MISC_IRQ_TIMER         AR531X_MISC_IRQ_BASE+1
-+#define AR531X_MISC_IRQ_AHB_PROC      AR531X_MISC_IRQ_BASE+2
-+#define AR531X_MISC_IRQ_AHB_DMA               AR531X_MISC_IRQ_BASE+3
-+#define AR531X_MISC_IRQ_GPIO          AR531X_MISC_IRQ_BASE+4
-+#define AR531X_MISC_IRQ_UART0         AR531X_MISC_IRQ_BASE+5
-+#define AR531X_MISC_IRQ_UART0_DMA     AR531X_MISC_IRQ_BASE+6
-+#define AR531X_MISC_IRQ_WATCHDOG      AR531X_MISC_IRQ_BASE+7
-+#define AR531X_MISC_IRQ_LOCAL         AR531X_MISC_IRQ_BASE+8
-+#define AR531X_MISC_IRQ_SPI           AR531X_MISC_IRQ_BASE+9
++#define AR531X_MISC_IRQ_NONE          (AR531X_MISC_IRQ_BASE+0)
++#define AR531X_MISC_IRQ_TIMER         (AR531X_MISC_IRQ_BASE+1)
++#define AR531X_MISC_IRQ_AHB_PROC      (AR531X_MISC_IRQ_BASE+2)
++#define AR531X_MISC_IRQ_AHB_DMA               (AR531X_MISC_IRQ_BASE+3)
++#define AR531X_MISC_IRQ_GPIO          (AR531X_MISC_IRQ_BASE+4)
++#define AR531X_MISC_IRQ_UART0         (AR531X_MISC_IRQ_BASE+5)
++#define AR531X_MISC_IRQ_UART0_DMA     (AR531X_MISC_IRQ_BASE+6)
++#define AR531X_MISC_IRQ_WATCHDOG      (AR531X_MISC_IRQ_BASE+7)
++#define AR531X_MISC_IRQ_LOCAL         (AR531X_MISC_IRQ_BASE+8)
++#define AR531X_MISC_IRQ_SPI           (AR531X_MISC_IRQ_BASE+9)
 +#define AR531X_MISC_IRQ_COUNT         10
 +
 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
-+#define AR531X_GPIO_IRQ_NONE            AR531X_GPIO_IRQ_BASE+0
-+#define AR531X_GPIO_IRQ(n)              AR531X_GPIO_IRQ_BASE+n
++#define AR531X_GPIO_IRQ_NONE            (AR531X_GPIO_IRQ_BASE+0)
++#define AR531X_GPIO_IRQ(n)              (AR531X_GPIO_IRQ_BASE+n)
 +#define AR531X_GPIO_IRQ_COUNT           22
 +
 +static inline u32