ar71xx: Add QCA955X GPIO mux and function definitions

[openwrt.git] / target / linux / ar71xx / patches-4.1 / 620-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index d739ccd..b754589 100644 (file)
--- a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -626,7 +626,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
-@@ -634,12 +747,32 @@
+@@ -634,6 +747,25 @@
  #define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  
@@ -649,9 +649,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
 +
- #define AR71XX_GPIO_COUNT             16
- #define AR7240_GPIO_COUNT             18
- #define AR7241_GPIO_COUNT             20
+ #define QCA955X_GPIO_REG_OUT_FUNC0    0x2c
+ #define QCA955X_GPIO_REG_OUT_FUNC1    0x30
+ #define QCA955X_GPIO_REG_OUT_FUNC2    0x34
+@@ -648,6 +780,7 @@
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
@@ -659,7 +660,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_COUNT            24
  
  /*
-@@ -663,6 +796,24 @@
+@@ -671,6 +804,24 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
@@ -684,7 +685,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
  #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
  #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
-@@ -804,6 +955,16 @@
+@@ -877,6 +1028,16 @@
  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
  
  /*