ar71xx: Bitmain Antminer S1 & S3 cleanup

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-om2p.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
index faeb49a..6b0bdc3 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
@@ -31,7 +31,7 @@
 #define OM2P_GPIO_LED_YELLOW   15
 #define OM2P_GPIO_LED_LAN      16
 #define OM2P_GPIO_LED_WAN      17
-#define OM2P_GPIO_BTN_RESET    11
+#define OM2P_GPIO_BTN_RESET    1
 
 #define OM2P_KEYS_POLL_INTERVAL                20      /* msecs */
 #define OM2P_KEYS_DEBOUNCE_INTERVAL    (3 * OM2P_KEYS_POLL_INTERVAL)
@@ -162,8 +162,8 @@ static void __init om2p_lc_setup(void)
                                        ARRAY_SIZE(om2p_gpio_keys),
                                        om2p_gpio_keys);
 
-       ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0);
-       ath79_init_mac(ath79_eth0_data.mac_addr, mac2, 0);
+       ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+       ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
 
        ath79_register_mdio(0, 0x0);
 
@@ -174,3 +174,52 @@ static void __init om2p_lc_setup(void)
 }
 
 MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
+MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup);
+
+static void __init om2p_hs_setup(void)
+{
+       u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
+       u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
+       u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
+
+       /* make lan / wan leds software controllable */
+       ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
+       ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
+
+       /* enable reset button */
+       ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
+       ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
+
+       om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
+       om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
+
+       ath79_register_m25p80(&om2p_lc_flash_data);
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
+                                om2p_leds_gpio);
+       ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(om2p_gpio_keys),
+                                       om2p_gpio_keys);
+
+       ath79_register_wmac(art, NULL);
+
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
+       ath79_register_mdio(1, 0x0);
+
+       ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+       ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
+
+       /* GMAC0 is connected to the PHY0 of the internal switch */
+       ath79_switch_data.phy4_mii_en = 1;
+       ath79_switch_data.phy_poll_mask = BIT(0);
+       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+       ath79_eth0_data.phy_mask = BIT(0);
+       ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
+       ath79_register_eth(0);
+
+       /* GMAC1 is connected to the internal switch */
+       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+       ath79_register_eth(1);
+}
+
+MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
+MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);