ar71xx: fix MII clock settings for various chips, improves ethernet stability on...

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 557457f..bc88a44 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -199,17 +199,25 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 
        switch (ath79_soc) {
        case ATH79_SOC_AR7240:
+               mdio_data->is_ar7240 = 1;
+               /* fall through */
        case ATH79_SOC_AR7241:
+               mdio_data->builtin_switch = 1;
+               break;
+
        case ATH79_SOC_AR9330:
+               mdio_data->is_ar9330 = 1;
+               /* fall through */
        case ATH79_SOC_AR9331:
-               mdio_data->is_ar7240 = 1;
+               mdio_data->builtin_switch = 1;
                break;
 
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
                if (id == 1)
-                       mdio_data->is_ar7240 = 1;
+                       mdio_data->builtin_switch = 1;
+               mdio_data->is_ar934x = 1;
                break;
 
        default:
@@ -273,16 +281,6 @@ static void ath79_set_speed_ge1(int speed)
        ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 }
 
-static void ar724x_set_speed_ge0(int speed)
-{
-       /* TODO */
-}
-
-static void ar724x_set_speed_ge1(int speed)
-{
-       /* TODO */
-}
-
 static void ar7242_set_speed_ge0(int speed)
 {
        u32 val = ath79_get_eth_pll(0, speed);
@@ -311,24 +309,18 @@ static void ar91xx_set_speed_ge1(int speed)
        ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 }
 
-static void ar933x_set_speed_ge0(int speed)
-{
-       /* TODO */
-}
-
-static void ar933x_set_speed_ge1(int speed)
-{
-       /* TODO */
-}
-
 static void ar934x_set_speed_ge0(int speed)
 {
-       /* TODO */
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(0, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
+       iounmap(base);
 }
 
-static void ar934x_set_speed_ge1(int speed)
+static void ath79_set_speed_dummy(int speed)
 {
-       /* TODO */
 }
 
 static void ath79_ddr_no_flush(void)
@@ -453,9 +445,9 @@ struct ag71xx_switch_platform_data ath79_switch_data;
 #define AR933X_PLL_VAL_100     0x00001099
 #define AR933X_PLL_VAL_10      0x00991099
 
-#define AR934X_PLL_VAL_1000    0x00110000
-#define AR934X_PLL_VAL_100     0x00001099
-#define AR934X_PLL_VAL_10      0x00991099
+#define AR934X_PLL_VAL_1000    0x16000000
+#define AR934X_PLL_VAL_100     0x00000101
+#define AR934X_PLL_VAL_10      0x00001616
 
 static void __init ath79_init_eth_pll_data(unsigned int id)
 {
@@ -703,7 +695,7 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
                                            AR71XX_RESET_GE1_PHY;
                        pdata->ddr_flush = ar724x_ddr_flush_ge1;
-                       pdata->set_speed = ar724x_set_speed_ge1;
+                       pdata->set_speed = ath79_set_speed_dummy;
                }
                pdata->has_gbit = 1;
                pdata->is_ar724x = 1;
@@ -726,17 +718,19 @@ void __init ath79_register_eth(unsigned int id)
                if (id == 0) {
                        pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
                        pdata->ddr_flush = ar724x_ddr_flush_ge0;
-                       pdata->set_speed = ar724x_set_speed_ge0;
+                       pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->phy_mask = BIT(4);
                } else {
                        pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
                        pdata->ddr_flush = ar724x_ddr_flush_ge1;
-                       pdata->set_speed = ar724x_set_speed_ge1;
+                       pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->speed = SPEED_1000;
                        pdata->duplex = DUPLEX_FULL;
                        pdata->switch_data = &ath79_switch_data;
+
+                       ath79_switch_data.phy_poll_mask |= BIT(4);
                }
                pdata->has_gbit = 1;
                pdata->is_ar724x = 1;
@@ -780,18 +774,20 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->reset_bit = AR933X_RESET_GE0_MAC |
                                           AR933X_RESET_GE0_MDIO;
                        pdata->ddr_flush = ar933x_ddr_flush_ge0;
-                       pdata->set_speed = ar933x_set_speed_ge0;
+                       pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->phy_mask = BIT(4);
                } else {
                        pdata->reset_bit = AR933X_RESET_GE1_MAC |
                                           AR933X_RESET_GE1_MDIO;
                        pdata->ddr_flush = ar933x_ddr_flush_ge1;
-                       pdata->set_speed = ar933x_set_speed_ge1;
+                       pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->speed = SPEED_1000;
                        pdata->duplex = DUPLEX_FULL;
                        pdata->switch_data = &ath79_switch_data;
+
+                       ath79_switch_data.phy_poll_mask |= BIT(4);
                }
 
                pdata->has_gbit = 1;
@@ -815,9 +811,13 @@ void __init ath79_register_eth(unsigned int id)
                } else {
                        pdata->reset_bit = AR934X_RESET_GE1_MAC |
                                           AR934X_RESET_GE1_MDIO;
-                       pdata->set_speed = ar934x_set_speed_ge1;
+                       pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->switch_data = &ath79_switch_data;
+
+                       /* reset the built-in switch */
+                       ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
+                       ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
                }
 
                pdata->ddr_flush = ath79_ddr_no_flush;