ar71xx: add a helper function to set RXDV/RXD of ETH_CFG on AR934x

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 21feeb9..ae3db4c 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -197,6 +197,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR7241:
        case ATH79_SOC_AR9330:
        case ATH79_SOC_AR9331:
+       case ATH79_SOC_QCA9533:
                mdio_dev = &ath79_mdio1_device;
                mdio_data = &ath79_mdio1_data;
                break;
@@ -254,6 +255,10 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
                mdio_data->is_ar934x = 1;
                break;
 
+       case ATH79_SOC_QCA9533:
+               mdio_data->builtin_switch = 1;
+               break;
+
        case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
                mdio_data->is_ar934x = 1;
@@ -563,6 +568,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9533:
        case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
                pll_10 = AR934X_PLL_VAL_10;
@@ -620,6 +626,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR7241:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
+               case ATH79_SOC_QCA9533:
                        pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
                        break;
 
@@ -680,6 +687,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR7241:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
+               case ATH79_SOC_QCA9533:
                        pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
                        break;
 
@@ -761,6 +769,50 @@ void __init ath79_setup_ar934x_eth_cfg(u32 mask)
        iounmap(base);
 }
 
+void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
+                                           unsigned int rxdv)
+{
+       void __iomem *base;
+       u32 t;
+
+       rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
+       rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
+
+       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+       t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+              AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+       t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+             rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+       /* flush write */
+       __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+       iounmap(base);
+}
+
+void __init ath79_setup_qca955x_eth_cfg(u32 mask)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+       t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+
+       t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+
+       t |= mask;
+
+       __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+       iounmap(base);
+}
+
 static int ath79_eth_instance __initdata;
 void __init ath79_register_eth(unsigned int id)
 {
@@ -914,13 +966,13 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->set_speed = ath79_set_speed_dummy;
 
                        pdata->speed = SPEED_1000;
+                       pdata->has_gbit = 1;
                        pdata->duplex = DUPLEX_FULL;
                        pdata->switch_data = &ath79_switch_data;
 
                        ath79_switch_data.phy_poll_mask |= BIT(4);
                }
 
-               pdata->has_gbit = 1;
                pdata->is_ar724x = 1;
 
                if (!pdata->fifo_cfg1)
@@ -965,6 +1017,37 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 
+       case ATH79_SOC_QCA9533:
+               if (id == 0) {
+                       pdata->reset_bit = AR933X_RESET_GE0_MAC |
+                                          AR933X_RESET_GE0_MDIO;
+                       pdata->set_speed = ath79_set_speed_dummy;
+
+                       pdata->phy_mask = BIT(4);
+               } else {
+                       pdata->reset_bit = AR933X_RESET_GE1_MAC |
+                                          AR933X_RESET_GE1_MDIO;
+                       pdata->set_speed = ath79_set_speed_dummy;
+
+                       pdata->speed = SPEED_1000;
+                       pdata->duplex = DUPLEX_FULL;
+                       pdata->switch_data = &ath79_switch_data;
+
+                       ath79_switch_data.phy_poll_mask |= BIT(4);
+               }
+
+               pdata->ddr_flush = ath79_ddr_no_flush;
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
        case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
                if (id == 0) {
@@ -1039,6 +1122,7 @@ void __init ath79_register_eth(unsigned int id)
                case ATH79_SOC_AR7241:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
+               case ATH79_SOC_QCA9533:
                        pdata->mii_bus_dev = &ath79_mdio1_device.dev;
                        break;
 
@@ -1055,10 +1139,10 @@ void __init ath79_register_eth(unsigned int id)
 
        /* Reset the device */
        ath79_device_reset_set(pdata->reset_bit);
-       mdelay(100);
+       msleep(100);
 
        ath79_device_reset_clear(pdata->reset_bit);
-       mdelay(100);
+       msleep(100);
 
        platform_device_register(pdev);
        ath79_eth_instance++;