ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 12a376e..2f2825f 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -271,6 +271,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_QCA956X:
                if (id == 1)
                        mdio_data->builtin_switch = 1;
+               mdio_data->is_ar934x = 1;
                break;
 
        default:
@@ -832,14 +833,24 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
 {
        void __iomem *base;
-       u32 t;
+       u32 t, m;
+
+       m = QCA955X_ETH_CFG_RGMII_EN |
+           QCA955X_ETH_CFG_MII_GE0 |
+           QCA955X_ETH_CFG_GMII_GE0 |
+           QCA955X_ETH_CFG_MII_GE0_MASTER |
+           QCA955X_ETH_CFG_MII_GE0_SLAVE |
+           QCA955X_ETH_CFG_GE0_ERR_EN |
+           QCA955X_ETH_CFG_GE0_SGMII |
+           QCA955X_ETH_CFG_RMII_GE0 |
+           QCA955X_ETH_CFG_MII_CNTL_SPEED |
+           QCA955X_ETH_CFG_RMII_GE0_MASTER;
 
        base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 
        t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 
-       t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-
+       t &= ~m;
        t |= mask;
 
        __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
@@ -1123,16 +1134,25 @@ void __init ath79_register_eth(unsigned int id)
                if (id == 0) {
                        pdata->reset_bit = QCA955X_RESET_GE0_MAC |
                                           QCA955X_RESET_GE0_MDIO;
+
                        if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
                                pdata->set_speed = qca956x_set_speed_sgmii;
                        else
-                               /* FIXME */
-                               pdata->set_speed = ath79_set_speed_dummy;
+                               pdata->set_speed = ath79_set_speed_ge0;
                } else {
                        pdata->reset_bit = QCA955X_RESET_GE1_MAC |
                                           QCA955X_RESET_GE1_MDIO;
-                       /* FIXME */
+
                        pdata->set_speed = ath79_set_speed_dummy;
+
+                       pdata->switch_data = &ath79_switch_data;
+
+                       pdata->speed = SPEED_1000;
+                       pdata->duplex = DUPLEX_FULL;
+
+                       /* reset the built-in switch */
+                       ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
+                       ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
                }
 
                pdata->ddr_flush = ath79_ddr_no_flush;
@@ -1196,6 +1216,11 @@ void __init ath79_register_eth(unsigned int id)
                        /* don't assign any MDIO device by default */
                        break;
 
+               case ATH79_SOC_QCA956X:
+                       if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
+                               pdata->mii_bus_dev = &ath79_mdio1_device.dev;
+                       break;
+
                default:
                        pdata->mii_bus_dev = &ath79_mdio0_device.dev;
                        break;