- case NL80211_RADAR_CAC_FINISHED:
- timeout = wdev->cac_start_time +
- msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
- WARN_ON(!time_after_eq(jiffies, timeout));
-- cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
-+ cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
- break;
- case NL80211_RADAR_CAC_ABORTED:
- break;
-@@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
- }
- wdev->cac_started = false;
-
-- nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
-+ nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
- }
- EXPORT_SYMBOL(cfg80211_cac_event);
---- a/net/wireless/nl80211.c
-+++ b/net/wireless/nl80211.c
-@@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
- if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
- nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
- goto nla_put_failure;
-- if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
-- nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
-- goto nla_put_failure;
-- if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
-- nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
-- goto nla_put_failure;
-+ if (chan->flags & IEEE80211_CHAN_NO_IR) {
-+ if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
-+ goto nla_put_failure;
-+ if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
-+ goto nla_put_failure;
-+ }
- if (chan->flags & IEEE80211_CHAN_RADAR) {
- if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
- goto nla_put_failure;
-@@ -1229,7 +1229,7 @@ static int nl80211_send_wiphy(struct cfg
- nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
- goto nla_put_failure;
- if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
-- nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
-+ nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_10_MHZ))
- goto nla_put_failure;
-
- state->split_start++;
-@@ -2170,7 +2170,7 @@ static inline u64 wdev_id(struct wireles
- }
-
- static int nl80211_send_chandef(struct sk_buff *msg,
-- struct cfg80211_chan_def *chandef)
-+ const struct cfg80211_chan_def *chandef)
- {
- WARN_ON(!cfg80211_chandef_valid(chandef));
-
-@@ -5653,7 +5653,7 @@ static int nl80211_start_radar_detection
- if (err == 0)
- return -EINVAL;
-
-- if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
-+ if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
- return -EINVAL;
-
- if (!rdev->ops->start_radar_detection)
-@@ -10882,7 +10882,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
-
- void
- nl80211_radar_notify(struct cfg80211_registered_device *rdev,
-- struct cfg80211_chan_def *chandef,
-+ const struct cfg80211_chan_def *chandef,
- enum nl80211_radar_event event,
- struct net_device *netdev, gfp_t gfp)
- {
---- a/net/wireless/nl80211.h
-+++ b/net/wireless/nl80211.h
-@@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
-
- void
- nl80211_radar_notify(struct cfg80211_registered_device *rdev,
-- struct cfg80211_chan_def *chandef,
-+ const struct cfg80211_chan_def *chandef,
- enum nl80211_radar_event event,
- struct net_device *netdev, gfp_t gfp);
-
---- a/net/wireless/reg.c
-+++ b/net/wireless/reg.c
-@@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
- REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
- /* IEEE 802.11b/g, channels 12..13. */
- REG_RULE(2467-10, 2472+10, 40, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS),
-+ NL80211_RRF_NO_IR),
- /* IEEE 802.11 channel 14 - Only JP enables
- * this and for 802.11b only */
- REG_RULE(2484-10, 2484+10, 20, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS |
-+ NL80211_RRF_NO_IR |
- NL80211_RRF_NO_OFDM),
- /* IEEE 802.11a, channel 36..48 */
- REG_RULE(5180-10, 5240+10, 160, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS),
-+ NL80211_RRF_NO_IR),
-
- /* IEEE 802.11a, channel 52..64 - DFS required */
- REG_RULE(5260-10, 5320+10, 160, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS |
-+ NL80211_RRF_NO_IR |
- NL80211_RRF_DFS),
-
- /* IEEE 802.11a, channel 100..144 - DFS required */
- REG_RULE(5500-10, 5720+10, 160, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS |
-+ NL80211_RRF_NO_IR |
- NL80211_RRF_DFS),
-
- /* IEEE 802.11a, channel 149..165 */
- REG_RULE(5745-10, 5825+10, 80, 6, 20,
-- NL80211_RRF_PASSIVE_SCAN |
-- NL80211_RRF_NO_IBSS),
-+ NL80211_RRF_NO_IR),
-
- /* IEEE 802.11ad (60gHz), channels 1..3 */
- REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
-@@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
- static u32 map_regdom_flags(u32 rd_flags)
- {
- u32 channel_flags = 0;
-- if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
-- channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
-- if (rd_flags & NL80211_RRF_NO_IBSS)
-- channel_flags |= IEEE80211_CHAN_NO_IBSS;
-+ if (rd_flags & NL80211_RRF_NO_IR_ALL)
-+ channel_flags |= IEEE80211_CHAN_NO_IR;
- if (rd_flags & NL80211_RRF_DFS)
- channel_flags |= IEEE80211_CHAN_RADAR;
- if (rd_flags & NL80211_RRF_NO_OFDM)
-@@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
- chan_before.center_freq = chan->center_freq;
- chan_before.flags = chan->flags;
-
-- if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
-- chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
-- channel_changed = true;
-- }
--
-- if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
-- chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
-+ if (chan->flags & IEEE80211_CHAN_NO_IR) {
-+ chan->flags &= ~IEEE80211_CHAN_NO_IR;
- channel_changed = true;
- }
-
---- /dev/null
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
-@@ -0,0 +1,422 @@
-+/*
-+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/export.h>
-+#include "ath9k.h"
-+#include "reg.h"
-+#include "hw-ops.h"
-+
-+const char *ath9k_hw_wow_event_to_string(u32 wow_event)
-+{
-+ if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
-+ return "Magic pattern";
-+ if (wow_event & AH_WOW_USER_PATTERN_EN)
-+ return "User pattern";
-+ if (wow_event & AH_WOW_LINK_CHANGE)
-+ return "Link change";
-+ if (wow_event & AH_WOW_BEACON_MISS)
-+ return "Beacon miss";
-+
-+ return "unknown reason";
-+}
-+EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
-+
-+static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
-+{
-+ struct ath_common *common = ath9k_hw_common(ah);
-+
-+ REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
-+
-+ /* set rx disable bit */
-+ REG_WRITE(ah, AR_CR, AR_CR_RXD);
-+
-+ if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
-+ ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
-+ REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
-+ return;
-+ }
-+
-+ REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
-+}
-+
-+static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
-+{
-+ struct ath_common *common = ath9k_hw_common(ah);
-+ u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
-+ u32 ctl[13] = {0};
-+ u32 data_word[KAL_NUM_DATA_WORDS];
-+ u8 i;
-+ u32 wow_ka_data_word0;
-+
-+ memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
-+ memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
-+
-+ /* set the transmit buffer */
-+ ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
-+ ctl[1] = 0;
-+ ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
-+ ctl[4] = 0;
-+ ctl[7] = (ah->txchainmask) << 2;
-+ ctl[2] = 0xf << 16; /* tx_tries 0 */
-+
-+ for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
-+ REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
-+
-+ REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
-+
-+ data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
-+ (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
-+ data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
-+ (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
-+ data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
-+ (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
-+ data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
-+ (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
-+ data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
-+ (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
-+ data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
-+
-+ if (AR_SREV_9462_20(ah)) {
-+ /* AR9462 2.0 has an extra descriptor word (time based
-+ * discard) compared to other chips */
-+ REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
-+ wow_ka_data_word0 = AR_WOW_TXBUF(13);
-+ } else {
-+ wow_ka_data_word0 = AR_WOW_TXBUF(12);
-+ }
-+
-+ for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
-+ REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
-+
-+}
-+
-+void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
-+ u8 *user_mask, int pattern_count,
-+ int pattern_len)
-+{
-+ int i;
-+ u32 pattern_val, mask_val;
-+ u32 set, clr;
-+
-+ /* FIXME: should check count by querying the hardware capability */
-+ if (pattern_count >= MAX_NUM_PATTERN)
-+ return;
-+
-+ REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
-+
-+ /* set the registers for pattern */
-+ for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
-+ memcpy(&pattern_val, user_pattern, 4);
-+ REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
-+ pattern_val);
-+ user_pattern += 4;
-+ }
-+
-+ /* set the registers for mask */
-+ for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
-+ memcpy(&mask_val, user_mask, 4);
-+ REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
-+ user_mask += 4;
-+ }
-+
-+ /* set the pattern length to be matched
-+ *
-+ * AR_WOW_LENGTH1_REG1
-+ * bit 31:24 pattern 0 length
-+ * bit 23:16 pattern 1 length
-+ * bit 15:8 pattern 2 length
-+ * bit 7:0 pattern 3 length
-+ *
-+ * AR_WOW_LENGTH1_REG2
-+ * bit 31:24 pattern 4 length
-+ * bit 23:16 pattern 5 length
-+ * bit 15:8 pattern 6 length
-+ * bit 7:0 pattern 7 length
-+ *
-+ * the below logic writes out the new
-+ * pattern length for the corresponding
-+ * pattern_count, while masking out the
-+ * other fields
-+ */
-+
-+ ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
-+
-+ if (pattern_count < 4) {
-+ /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
-+ set = (pattern_len & AR_WOW_LENGTH_MAX) <<
-+ AR_WOW_LEN1_SHIFT(pattern_count);
-+ clr = AR_WOW_LENGTH1_MASK(pattern_count);
-+ REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
-+ } else {
-+ /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
-+ set = (pattern_len & AR_WOW_LENGTH_MAX) <<
-+ AR_WOW_LEN2_SHIFT(pattern_count);
-+ clr = AR_WOW_LENGTH2_MASK(pattern_count);
-+ REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
-+ }
-+
-+}
-+EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
-+
-+u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
-+{
-+ u32 wow_status = 0;
-+ u32 val = 0, rval;
-+
-+ /*
-+ * read the WoW status register to know
-+ * the wakeup reason
-+ */
-+ rval = REG_READ(ah, AR_WOW_PATTERN);
-+ val = AR_WOW_STATUS(rval);
-+
-+ /*
-+ * mask only the WoW events that we have enabled. Sometimes
-+ * we have spurious WoW events from the AR_WOW_PATTERN
-+ * register. This mask will clean it up.
-+ */
-+
-+ val &= ah->wow_event_mask;
-+
-+ if (val) {
-+ if (val & AR_WOW_MAGIC_PAT_FOUND)
-+ wow_status |= AH_WOW_MAGIC_PATTERN_EN;
-+ if (AR_WOW_PATTERN_FOUND(val))
-+ wow_status |= AH_WOW_USER_PATTERN_EN;
-+ if (val & AR_WOW_KEEP_ALIVE_FAIL)
-+ wow_status |= AH_WOW_LINK_CHANGE;
-+ if (val & AR_WOW_BEACON_FAIL)
-+ wow_status |= AH_WOW_BEACON_MISS;
-+ }
-+
-+ /*
-+ * set and clear WOW_PME_CLEAR registers for the chip to
-+ * generate next wow signal.
-+ * disable D3 before accessing other registers ?
-+ */
-+
-+ /* do we need to check the bit value 0x01000000 (7-10) ?? */
-+ REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
-+ AR_PMCTRL_PWR_STATE_D1D3);
-+
-+ /*
-+ * clear all events
-+ */
-+ REG_WRITE(ah, AR_WOW_PATTERN,
-+ AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
-+
-+ /*
-+ * restore the beacon threshold to init value
-+ */
-+ REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
-+
-+ /*
-+ * Restore the way the PCI-E reset, Power-On-Reset, external
-+ * PCIE_POR_SHORT pins are tied to its original value.
-+ * Previously just before WoW sleep, we untie the PCI-E
-+ * reset to our Chip's Power On Reset so that any PCI-E
-+ * reset from the bus will not reset our chip
-+ */
-+ if (ah->is_pciexpress)
-+ ath9k_hw_configpcipowersave(ah, false);
-+
-+ ah->wow_event_mask = 0;
-+
-+ return wow_status;
-+}
-+EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
-+
-+void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
-+{
-+ u32 wow_event_mask;
-+ u32 set, clr;
-+
-+ /*
-+ * wow_event_mask is a mask to the AR_WOW_PATTERN register to
-+ * indicate which WoW events we have enabled. The WoW events
-+ * are from the 'pattern_enable' in this function and
-+ * 'pattern_count' of ath9k_hw_wow_apply_pattern()
-+ */
-+ wow_event_mask = ah->wow_event_mask;
-+
-+ /*
-+ * Untie Power-on-Reset from the PCI-E-Reset. When we are in
-+ * WOW sleep, we do want the Reset from the PCI-E to disturb
-+ * our hw state
-+ */
-+ if (ah->is_pciexpress) {
-+ /*
-+ * we need to untie the internal POR (power-on-reset)
-+ * to the external PCI-E reset. We also need to tie
-+ * the PCI-E Phy reset to the PCI-E reset.
-+ */
-+ set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
-+ clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
-+ REG_RMW(ah, AR_WA, set, clr);
-+ }
-+
-+ /*
-+ * set the power states appropriately and enable PME
-+ */
-+ set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
-+ AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
-+
-+ /*
-+ * set and clear WOW_PME_CLEAR registers for the chip
-+ * to generate next wow signal.
-+ */
-+ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
-+ clr = AR_PMCTRL_WOW_PME_CLR;
-+ REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
-+
-+ /*
-+ * Setup for:
-+ * - beacon misses
-+ * - magic pattern
-+ * - keep alive timeout
-+ * - pattern matching
-+ */
-+
-+ /*
-+ * Program default values for pattern backoff, aifs/slot/KAL count,
-+ * beacon miss timeout, KAL timeout, etc.
-+ */
-+ set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
-+ REG_SET_BIT(ah, AR_WOW_PATTERN, set);
-+
-+ set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
-+ AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
-+ AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
-+ REG_SET_BIT(ah, AR_WOW_COUNT, set);
-+
-+ if (pattern_enable & AH_WOW_BEACON_MISS)
-+ set = AR_WOW_BEACON_TIMO;
-+ /* We are not using beacon miss, program a large value */
-+ else
-+ set = AR_WOW_BEACON_TIMO_MAX;
-+
-+ REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
-+
-+ /*
-+ * Keep alive timo in ms except AR9280
-+ */
-+ if (!pattern_enable)
-+ set = AR_WOW_KEEP_ALIVE_NEVER;
-+ else
-+ set = KAL_TIMEOUT * 32;
-+
-+ REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
-+
-+ /*
-+ * Keep alive delay in us. based on 'power on clock',
-+ * therefore in usec
-+ */
-+ set = KAL_DELAY * 1000;
-+ REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
-+
-+ /*
-+ * Create keep alive pattern to respond to beacons
-+ */
-+ ath9k_wow_create_keep_alive_pattern(ah);
-+
-+ /*
-+ * Configure MAC WoW Registers
-+ */
-+ set = 0;
-+ /* Send keep alive timeouts anyway */
-+ clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
-+
-+ if (pattern_enable & AH_WOW_LINK_CHANGE)
-+ wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
-+ else
-+ set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
-+
-+ set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
-+ REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
-+
-+ /*
-+ * we are relying on a bmiss failure. ensure we have
-+ * enough threshold to prevent false positives
-+ */
-+ REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
-+ AR_WOW_BMISSTHRESHOLD);
-+
-+ set = 0;
-+ clr = 0;
-+
-+ if (pattern_enable & AH_WOW_BEACON_MISS) {
-+ set = AR_WOW_BEACON_FAIL_EN;
-+ wow_event_mask |= AR_WOW_BEACON_FAIL;
-+ } else {
-+ clr = AR_WOW_BEACON_FAIL_EN;
-+ }
-+
-+ REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
-+
-+ set = 0;
-+ clr = 0;
-+ /*
-+ * Enable the magic packet registers
-+ */
-+ if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
-+ set = AR_WOW_MAGIC_EN;
-+ wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
-+ } else {
-+ clr = AR_WOW_MAGIC_EN;
-+ }
-+ set |= AR_WOW_MAC_INTR_EN;
-+ REG_RMW(ah, AR_WOW_PATTERN, set, clr);
-+
-+ REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
-+ AR_WOW_PATTERN_SUPPORTED);
-+
-+ /*
-+ * Set the power states appropriately and enable PME
-+ */
-+ clr = 0;
-+ set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
-+ AR_PMCTRL_PWR_PM_CTRL_ENA;
-+
-+ clr = AR_PCIE_PM_CTRL_ENA;
-+ REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
-+
-+ /*
-+ * this is needed to prevent the chip waking up
-+ * the host within 3-4 seconds with certain
-+ * platform/BIOS. The fix is to enable
-+ * D1 & D3 to match original definition and
-+ * also match the OTP value. Anyway this
-+ * is more related to SW WOW.
-+ */
-+ clr = AR_PMCTRL_PWR_STATE_D1D3;
-+ REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
-+
-+ set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
-+ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
-+
-+ REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
-+
-+ /* to bring down WOW power low margin */
-+ set = BIT(13);
-+ REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
-+ /* HW WoW */
-+ clr = BIT(5);
-+ REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
-+
-+ ath9k_hw_set_powermode_wow_sleep(ah);
-+ ah->wow_event_mask = wow_event_mask;
-+}
-+EXPORT_SYMBOL(ath9k_hw_wow_enable);
---- /dev/null
-+++ b/drivers/net/wireless/ath/ath9k/tx99.c
-@@ -0,0 +1,263 @@
-+/*
-+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include "ath9k.h"
-+
-+static void ath9k_tx99_stop(struct ath_softc *sc)
-+{
-+ struct ath_hw *ah = sc->sc_ah;
-+ struct ath_common *common = ath9k_hw_common(ah);
-+
-+ ath_drain_all_txq(sc);
-+ ath_startrecv(sc);
-+
-+ ath9k_hw_set_interrupts(ah);
-+ ath9k_hw_enable_interrupts(ah);
-+
-+ ieee80211_wake_queues(sc->hw);
-+
-+ kfree_skb(sc->tx99_skb);
-+ sc->tx99_skb = NULL;
-+ sc->tx99_state = false;
-+
-+ ath9k_hw_tx99_stop(sc->sc_ah);
-+ ath_dbg(common, XMIT, "TX99 stopped\n");
-+}
-+
-+static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
-+{
-+ static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
-+ 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
-+ 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
-+ 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
-+ 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
-+ 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
-+ 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
-+ 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
-+ u32 len = 1200;
-+ struct ieee80211_hw *hw = sc->hw;
-+ struct ieee80211_hdr *hdr;
-+ struct ieee80211_tx_info *tx_info;
-+ struct sk_buff *skb;
-+
-+ skb = alloc_skb(len, GFP_KERNEL);
-+ if (!skb)
-+ return NULL;
-+
-+ skb_put(skb, len);
-+
-+ memset(skb->data, 0, len);
-+
-+ hdr = (struct ieee80211_hdr *)skb->data;
-+ hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
-+ hdr->duration_id = 0;
-+
-+ memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
-+ memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
-+ memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
-+
-+ hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
-+
-+ tx_info = IEEE80211_SKB_CB(skb);
-+ memset(tx_info, 0, sizeof(*tx_info));
-+ tx_info->band = hw->conf.chandef.chan->band;
-+ tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
-+ tx_info->control.vif = sc->tx99_vif;
-+
-+ memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
-+
-+ return skb;
-+}
-+
-+static void ath9k_tx99_deinit(struct ath_softc *sc)
-+{
-+ ath_reset(sc);
-+
-+ ath9k_ps_wakeup(sc);
-+ ath9k_tx99_stop(sc);
-+ ath9k_ps_restore(sc);
-+}
-+
-+static int ath9k_tx99_init(struct ath_softc *sc)
-+{
-+ struct ieee80211_hw *hw = sc->hw;
-+ struct ath_hw *ah = sc->sc_ah;
-+ struct ath_common *common = ath9k_hw_common(ah);
-+ struct ath_tx_control txctl;
-+ int r;
-+
-+ if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
-+ ath_err(common,
-+ "driver is in invalid state unable to use TX99");
-+ return -EINVAL;
-+ }
-+
-+ sc->tx99_skb = ath9k_build_tx99_skb(sc);
-+ if (!sc->tx99_skb)
-+ return -ENOMEM;
-+
-+ memset(&txctl, 0, sizeof(txctl));
-+ txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
-+
-+ ath_reset(sc);
-+
-+ ath9k_ps_wakeup(sc);
-+
-+ ath9k_hw_disable_interrupts(ah);
-+ atomic_set(&ah->intr_ref_cnt, -1);
-+ ath_drain_all_txq(sc);
-+ ath_stoprecv(sc);
-+
-+ sc->tx99_state = true;
-+
-+ ieee80211_stop_queues(hw);
-+
-+ if (sc->tx99_power == MAX_RATE_POWER + 1)
-+ sc->tx99_power = MAX_RATE_POWER;
-+
-+ ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
-+ r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
-+ if (r) {
-+ ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
-+ return r;
-+ }
-+
-+ ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
-+ sc->tx99_power,
-+ sc->tx99_power / 2);
-+
-+ /* We leave the harware awake as it will be chugging on */
-+
-+ return 0;
-+}
-+
-+static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct ath_softc *sc = file->private_data;
-+ char buf[3];
-+ unsigned int len;
-+
-+ len = sprintf(buf, "%d\n", sc->tx99_state);
-+ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-+}
-+
-+static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct ath_softc *sc = file->private_data;
-+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-+ char buf[32];
-+ bool start;
-+ ssize_t len;
-+ int r;
-+
-+ if (sc->nvifs > 1)
-+ return -EOPNOTSUPP;
-+
-+ len = min(count, sizeof(buf) - 1);
-+ if (copy_from_user(buf, user_buf, len))
-+ return -EFAULT;
-+
-+ if (strtobool(buf, &start))
-+ return -EINVAL;
-+
-+ if (start == sc->tx99_state) {
-+ if (!start)
-+ return count;
-+ ath_dbg(common, XMIT, "Resetting TX99\n");
-+ ath9k_tx99_deinit(sc);
-+ }
-+
-+ if (!start) {
-+ ath9k_tx99_deinit(sc);
-+ return count;
-+ }
-+
-+ r = ath9k_tx99_init(sc);
-+ if (r)
-+ return r;
-+
-+ return count;
-+}
-+
-+static const struct file_operations fops_tx99 = {
-+ .read = read_file_tx99,
-+ .write = write_file_tx99,
-+ .open = simple_open,
-+ .owner = THIS_MODULE,
-+ .llseek = default_llseek,
-+};
-+
-+static ssize_t read_file_tx99_power(struct file *file,
-+ char __user *user_buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct ath_softc *sc = file->private_data;
-+ char buf[32];
-+ unsigned int len;
-+
-+ len = sprintf(buf, "%d (%d dBm)\n",
-+ sc->tx99_power,
-+ sc->tx99_power / 2);
-+
-+ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-+}
-+
-+static ssize_t write_file_tx99_power(struct file *file,
-+ const char __user *user_buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct ath_softc *sc = file->private_data;
-+ int r;
-+ u8 tx_power;
-+
-+ r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
-+ if (r)
-+ return r;
-+
-+ if (tx_power > MAX_RATE_POWER)
-+ return -EINVAL;
-+
-+ sc->tx99_power = tx_power;
-+
-+ ath9k_ps_wakeup(sc);
-+ ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
-+ ath9k_ps_restore(sc);
-+
-+ return count;
-+}
-+
-+static const struct file_operations fops_tx99_power = {
-+ .read = read_file_tx99_power,
-+ .write = write_file_tx99_power,
-+ .open = simple_open,
-+ .owner = THIS_MODULE,
-+ .llseek = default_llseek,
-+};
-+
-+void ath9k_tx99_init_debug(struct ath_softc *sc)
-+{
-+ if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
-+ return;
-+
-+ debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
-+ sc->debug.debugfs_phy, sc,
-+ &fops_tx99);
-+ debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
-+ sc->debug.debugfs_phy, sc,
-+ &fops_tx99_power);
-+}
---- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
-+++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
-@@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
- if (buf == NULL)
- return -ENOMEM;
-
-- if (sc->dfs_detector)
-- dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
--
- len += scnprintf(buf + len, size - len, "DFS support for "
- "macVersion = 0x%x, macRev = 0x%x: %s\n",
- hw_ver->macVersion, hw_ver->macRev,
- (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
- "enabled" : "disabled");
-+
-+ if (!sc->dfs_detector) {
-+ len += scnprintf(buf + len, size - len,
-+ "DFS detector not enabled\n");
-+ goto exit;
-+ }
-+
-+ dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
-+
- len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
- ATH9K_DFS_STAT("pulse events reported ", pulses_total);
- ATH9K_DFS_STAT("invalid pulse events ", pulses_no_dfs);
-@@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
- ATH9K_DFS_POOL_STAT("Seqs. alloc error ", pseq_alloc_error);
- ATH9K_DFS_POOL_STAT("Seqs. in use ", pseq_used);
-
-+exit:
- if (len > size)
- len = size;
-
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-@@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
- else
- ah->enabled_cals &= ~TX_IQ_CAL;
-
-- if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
-- ah->enabled_cals |= TX_CL_CAL;
-- else
-- ah->enabled_cals &= ~TX_CL_CAL;
- }
-+
-+ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
-+ ah->enabled_cals |= TX_CL_CAL;
-+ else
-+ ah->enabled_cals &= ~TX_CL_CAL;
- }
-
- static void ar9003_hw_prog_ini(struct ath_hw *ah,
-@@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
- return ret;
- }
-
-+static void ar9003_doubler_fix(struct ath_hw *ah)
-+{
-+ if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
-+ REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
-+ REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
-+ REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
-+
-+ udelay(200);
-+
-+ REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
-+ REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
-+ REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
-+
-+ udelay(1);
-+
-+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
-+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
-+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
-+ AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
-+
-+ udelay(200);
-+
-+ REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
-+ AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
-+
-+ REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
-+ REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
-+ REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
-+ 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
-+ }
-+}
-+
- static int ar9003_hw_process_ini(struct ath_hw *ah,
- struct ath9k_channel *chan)
- {
-@@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
- modesIndex);
- }
-
-+ ar9003_doubler_fix(ah);
-+
- /*
- * RXGAIN initvals.
- */
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-@@ -656,13 +656,24 @@
- #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
- #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
- #define AR_PHY_65NM_CH0_SYNTH7 0x16098
-+#define AR_PHY_65NM_CH0_SYNTH12 0x160ac
- #define AR_PHY_65NM_CH0_BIAS1 0x160c0
- #define AR_PHY_65NM_CH0_BIAS2 0x160c4
- #define AR_PHY_65NM_CH0_BIAS4 0x160cc
-+#define AR_PHY_65NM_CH0_RXTX2 0x16104
-+#define AR_PHY_65NM_CH1_RXTX2 0x16504
-+#define AR_PHY_65NM_CH2_RXTX2 0x16904
- #define AR_PHY_65NM_CH0_RXTX4 0x1610c
- #define AR_PHY_65NM_CH1_RXTX4 0x1650c
- #define AR_PHY_65NM_CH2_RXTX4 0x1690c
-
-+#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
-+#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19
-+#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
-+#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2
-+#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
-+#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3
-+
- #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
- (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
- #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
---- a/drivers/net/wireless/rt2x00/rt2x00dev.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
-@@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
- static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
- struct ieee80211_vif *vif)
- {
-+ struct ieee80211_tx_control control = {};
- struct rt2x00_dev *rt2x00dev = data;
- struct sk_buff *skb;
-
-@@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
- */
- skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
- while (skb) {
-- rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
-+ rt2x00mac_tx(rt2x00dev->hw, &control, skb);
- skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
- }
- }
---- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-@@ -1040,8 +1040,8 @@ static void ar9003_hw_cl_cal_post_proc(s
- }
- }
-
--static bool ar9003_hw_init_cal(struct ath_hw *ah,
-- struct ath9k_channel *chan)
-+static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
-+ struct ath9k_channel *chan)
- {
- struct ath_common *common = ath9k_hw_common(ah);
- struct ath9k_hw_cal_data *caldata = ah->caldata;
-@@ -1228,13 +1228,109 @@ skip_tx_iqcal:
- return true;
- }
-
-+static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
-+ struct ath9k_channel *chan)
-+{
-+ struct ath_common *common = ath9k_hw_common(ah);
-+ struct ath9k_hw_cal_data *caldata = ah->caldata;
-+ bool txiqcal_done = false;
-+ bool is_reusable = true, status = true;
-+ bool run_agc_cal = false, sep_iq_cal = false;
-+
-+ /* Use chip chainmask only for calibration */
-+ ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
-+
-+ if (ah->enabled_cals & TX_CL_CAL) {
-+ REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-+ run_agc_cal = true;
-+ }
-+
-+ if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
-+ goto skip_tx_iqcal;
-+
-+ /* Do Tx IQ Calibration */
-+ REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
-+ AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
-+ DELPT);
-+
-+ /*
-+ * For AR9485 or later chips, TxIQ cal runs as part of
-+ * AGC calibration. Specifically, AR9550 in SoC chips.
-+ */
-+ if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
-+ txiqcal_done = true;
-+ run_agc_cal = true;
-+ } else {
-+ sep_iq_cal = true;
-+ run_agc_cal = true;
-+ }
-+
-+ /*
-+ * In the SoC family, this will run for AR9300, AR9331 and AR9340.
-+ */
-+ if (sep_iq_cal) {
-+ txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
-+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-+ udelay(5);
-+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-+ }
-+
-+skip_tx_iqcal:
-+ if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
-+ /* Calibrate the AGC */
-+ REG_WRITE(ah, AR_PHY_AGC_CONTROL,
-+ REG_READ(ah, AR_PHY_AGC_CONTROL) |
-+ AR_PHY_AGC_CONTROL_CAL);
-+
-+ /* Poll for offset calibration complete */
-+ status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
-+ AR_PHY_AGC_CONTROL_CAL,
-+ 0, AH_WAIT_TIMEOUT);
-+ }
-+
-+ if (!status) {
-+ ath_dbg(common, CALIBRATE,
-+ "offset calibration failed to complete in %d ms; noisy environment?\n",
-+ AH_WAIT_TIMEOUT / 1000);
-+ return false;
-+ }
-+
-+ if (txiqcal_done)
-+ ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
-+
-+ /* Revert chainmask to runtime parameters */
-+ ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
-+
-+ /* Initialize list pointers */
-+ ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
-+
-+ INIT_CAL(&ah->iq_caldata);
-+ INSERT_CAL(ah, &ah->iq_caldata);
-+ ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
-+
-+ /* Initialize current pointer to first element in list */
-+ ah->cal_list_curr = ah->cal_list;
-+
-+ if (ah->cal_list_curr)
-+ ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
-+
-+ if (caldata)
-+ caldata->CalValid = 0;
-+
-+ return true;
-+}
-+
- void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
- {
- struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
- struct ath_hw_ops *ops = ath9k_hw_ops(ah);
-
-+ if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
-+ priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
-+ else
-+ priv_ops->init_cal = ar9003_hw_init_cal_soc;
-+
- priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
-- priv_ops->init_cal = ar9003_hw_init_cal;
- priv_ops->setup_calibration = ar9003_hw_setup_calibration;
-
- ops->calibrate = ar9003_hw_calibrate;
---- a/drivers/net/wireless/ath/ath9k/common.c
-+++ b/drivers/net/wireless/ath/ath9k/common.c
-@@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
- {
- struct ieee80211_channel *curchan = chandef->chan;
- struct ath9k_channel *channel;
-- u8 chan_idx;
-
-- chan_idx = curchan->hw_value;
-- channel = &ah->channels[chan_idx];
-+ channel = &ah->channels[curchan->hw_value];
- ath9k_cmn_update_ichannel(channel, chandef);
-
- return channel;