+diff -urN linux-2.6.24.3/include/linux/atmel_serial.h avr32-2.6/include/linux/atmel_serial.h
+--- linux-2.6.24.3/include/linux/atmel_serial.h 1970-01-01 01:00:00.000000000 +0100
++++ avr32-2.6/include/linux/atmel_serial.h 2008-04-23 19:33:51.000000000 +0200
+@@ -0,0 +1,127 @@
++/*
++ * include/linux/atmel_serial.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * USART registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef ATMEL_SERIAL_H
++#define ATMEL_SERIAL_H
++
++#define ATMEL_US_CR 0x00 /* Control Register */
++#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
++#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
++#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
++#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
++#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
++#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
++#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
++#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
++#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
++#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
++#define ATMEL_US_SENDA (1 << 12) /* Send Address */
++#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
++#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
++#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
++#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
++#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
++#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
++#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
++
++#define ATMEL_US_MR 0x04 /* Mode Register */
++#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
++#define ATMEL_US_USMODE_NORMAL 0
++#define ATMEL_US_USMODE_RS485 1
++#define ATMEL_US_USMODE_HWHS 2
++#define ATMEL_US_USMODE_MODEM 3
++#define ATMEL_US_USMODE_ISO7816_T0 4
++#define ATMEL_US_USMODE_ISO7816_T1 6
++#define ATMEL_US_USMODE_IRDA 8
++#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
++#define ATMEL_US_USCLKS_MCK (0 << 4)
++#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
++#define ATMEL_US_USCLKS_SCK (3 << 4)
++#define ATMEL_US_CHRL (3 << 6) /* Character Length */
++#define ATMEL_US_CHRL_5 (0 << 6)
++#define ATMEL_US_CHRL_6 (1 << 6)
++#define ATMEL_US_CHRL_7 (2 << 6)
++#define ATMEL_US_CHRL_8 (3 << 6)
++#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
++#define ATMEL_US_PAR (7 << 9) /* Parity Type */
++#define ATMEL_US_PAR_EVEN (0 << 9)
++#define ATMEL_US_PAR_ODD (1 << 9)
++#define ATMEL_US_PAR_SPACE (2 << 9)
++#define ATMEL_US_PAR_MARK (3 << 9)
++#define ATMEL_US_PAR_NONE (4 << 9)
++#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
++#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
++#define ATMEL_US_NBSTOP_1 (0 << 12)
++#define ATMEL_US_NBSTOP_1_5 (1 << 12)
++#define ATMEL_US_NBSTOP_2 (2 << 12)
++#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
++#define ATMEL_US_CHMODE_NORMAL (0 << 14)
++#define ATMEL_US_CHMODE_ECHO (1 << 14)
++#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
++#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
++#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
++#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
++#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
++#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
++#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
++#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
++#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
++#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
++
++#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
++#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
++#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
++#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
++#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
++#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
++#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
++#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
++#define ATMEL_US_PARE (1 << 7) /* Parity Error */
++#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
++#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
++#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
++#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
++#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
++#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
++#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
++#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
++#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
++#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
++#define ATMEL_US_RI (1 << 20) /* RI */
++#define ATMEL_US_DSR (1 << 21) /* DSR */
++#define ATMEL_US_DCD (1 << 22) /* DCD */
++#define ATMEL_US_CTS (1 << 23) /* CTS */
++
++#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
++#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
++#define ATMEL_US_CSR 0x14 /* Channel Status Register */
++#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
++#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
++#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
++
++#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
++#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
++
++#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
++#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
++
++#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
++#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
++
++#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
++#define ATMEL_US_NER 0x44 /* Number of Errors Register */
++#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
++
++#endif
+diff -urN linux-2.6.24.3/include/linux/atmel_tc.h avr32-2.6/include/linux/atmel_tc.h
+--- linux-2.6.24.3/include/linux/atmel_tc.h 1970-01-01 01:00:00.000000000 +0100
++++ avr32-2.6/include/linux/atmel_tc.h 2008-04-23 20:12:46.000000000 +0200
+@@ -0,0 +1,252 @@
++/*
++ * Timer/Counter Unit (TC) registers.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef ATMEL_TC_H
++#define ATMEL_TC_H
++
++#include <linux/compiler.h>
++#include <linux/list.h>
++
++/*
++ * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
++ * three general-purpose 16-bit timers. These timers share one register bank.
++ * Depending on the SOC, each timer may have its own clock and IRQ, or those
++ * may be shared by the whole TC block.
++ *
++ * These TC blocks may have up to nine external pins: TCLK0..2 signals for
++ * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
++ * or triggering. Those pins need to be set up for use with the TC block,
++ * else they will be used as GPIOs or for a different controller.
++ *
++ * Although we expect each TC block to have a platform_device node, those
++ * nodes are not what drivers bind to. Instead, they ask for a specific
++ * TC block, by number ... which is a common approach on systems with many
++ * timers. Then they use clk_get() and platform_get_irq() to get clock and
++ * IRQ resources.
++ */
++
++struct clk;
++
++/**
++ * struct atmel_tc - information about a Timer/Counter Block
++ * @pdev: physical device
++ * @iomem: resource associated with the I/O register
++ * @regs: mapping through which the I/O registers can be accessed
++ * @irq: irq for each of the three channels
++ * @clk: internal clock source for each of the three channels
++ * @node: list node, for tclib internal use
++ *
++ * On some platforms, each TC channel has its own clocks and IRQs,
++ * while on others, all TC channels share the same clock and IRQ.
++ * Drivers should clk_enable() all the clocks they need even though
++ * all the entries in @clk may point to the same physical clock.
++ * Likewise, drivers should request irqs independently for each
++ * channel, but they must use IRQF_SHARED in case some of the entries
++ * in @irq are actually the same IRQ.
++ */
++struct atmel_tc {
++ struct platform_device *pdev;
++ struct resource *iomem;
++ void __iomem *regs;
++ int irq[3];
++ struct clk *clk[3];
++ struct list_head node;
++};
++
++extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
++extern void atmel_tc_free(struct atmel_tc *tc);
++
++/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
++extern const u8 atmel_tc_divisors[5];
++
++
++/*
++ * Two registers have block-wide controls. These are: configuring the three
++ * "external" clocks (or event sources) used by the timer channels; and
++ * synchronizing the timers by resetting them all at once.
++ *
++ * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
++ * signals. Or, it can mean "external to timer", using the TIOA output from
++ * one of the other two timers that's being run in waveform mode.
++ */
++
++#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
++#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
++
++#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
++#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
++#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
++#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
++#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
++#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
++#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
++#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
++#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
++#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
++#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
++#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
++#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
++#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
++#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
++#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
++
++
++/*
++ * Each TC block has three "channels", each with one counter and controls.
++ *
++ * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
++ * when it's not "external") is silicon-specific. AT91 platforms use one
++ * set of definitions; AVR32 platforms use a different set. Don't hard-wire
++ * such knowledge into your code, use the global "atmel_tc_divisors" ...
++ * where index N is the divisor for clock N+1, else zero to indicate it uses
++ * the 32 KiHz clock.
++ *
++ * The timers can be chained in various ways, and operated in "waveform"
++ * generation mode (including PWM) or "capture" mode (to time events). In
++ * both modes, behavior can be configured in many ways.
++ *
++ * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
++ * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
++ * uses them only as inputs.
++ */
++#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
++#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
++
++#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
++#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
++#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
++#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
++
++#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
++
++/* Both modes share some CMR bits */
++#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
++#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
++#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
++#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
++#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
++#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
++#define ATMEL_TC_XC0 (5 << 0)
++#define ATMEL_TC_XC1 (6 << 0)
++#define ATMEL_TC_XC2 (7 << 0)
++#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
++#define ATMEL_TC_BURST (3 << 4) /* clock gating */
++#define ATMEL_TC_GATE_NONE (0 << 4)
++#define ATMEL_TC_GATE_XC0 (1 << 4)
++#define ATMEL_TC_GATE_XC1 (2 << 4)
++#define ATMEL_TC_GATE_XC2 (3 << 4)
++#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
++
++/* CAPTURE mode CMR bits */
++#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
++#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
++#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
++#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
++#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
++#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
++#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
++#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
++#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
++#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
++#define ATMEL_TC_LDRA_NONE (0 << 16)
++#define ATMEL_TC_LDRA_RISING (1 << 16)
++#define ATMEL_TC_LDRA_FALLING (2 << 16)
++#define ATMEL_TC_LDRA_BOTH (3 << 16)
++#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
++#define ATMEL_TC_LDRB_NONE (0 << 18)
++#define ATMEL_TC_LDRB_RISING (1 << 18)
++#define ATMEL_TC_LDRB_FALLING (2 << 18)
++#define ATMEL_TC_LDRB_BOTH (3 << 18)
++
++/* WAVEFORM mode CMR bits */
++#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
++#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
++#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
++#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
++#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
++#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
++#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
++#define ATMEL_TC_EEVT (3 << 10) /* external event source */
++#define ATMEL_TC_EEVT_TIOB (0 << 10)
++#define ATMEL_TC_EEVT_XC0 (1 << 10)
++#define ATMEL_TC_EEVT_XC1 (2 << 10)
++#define ATMEL_TC_EEVT_XC2 (3 << 10)
++#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
++#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
++#define ATMEL_TC_WAVESEL_UP (0 << 13)
++#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
++#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
++#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
++#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
++#define ATMEL_TC_ACPA_NONE (0 << 16)
++#define ATMEL_TC_ACPA_SET (1 << 16)
++#define ATMEL_TC_ACPA_CLEAR (2 << 16)
++#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
++#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
++#define ATMEL_TC_ACPC_NONE (0 << 18)
++#define ATMEL_TC_ACPC_SET (1 << 18)
++#define ATMEL_TC_ACPC_CLEAR (2 << 18)
++#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
++#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
++#define ATMEL_TC_AEEVT_NONE (0 << 20)
++#define ATMEL_TC_AEEVT_SET (1 << 20)
++#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
++#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
++#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
++#define ATMEL_TC_ASWTRG_NONE (0 << 22)
++#define ATMEL_TC_ASWTRG_SET (1 << 22)
++#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
++#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
++#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
++#define ATMEL_TC_BCPB_NONE (0 << 24)
++#define ATMEL_TC_BCPB_SET (1 << 24)
++#define ATMEL_TC_BCPB_CLEAR (2 << 24)
++#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
++#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
++#define ATMEL_TC_BCPC_NONE (0 << 26)
++#define ATMEL_TC_BCPC_SET (1 << 26)
++#define ATMEL_TC_BCPC_CLEAR (2 << 26)
++#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
++#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
++#define ATMEL_TC_BEEVT_NONE (0 << 28)
++#define ATMEL_TC_BEEVT_SET (1 << 28)
++#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
++#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
++#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
++#define ATMEL_TC_BSWTRG_NONE (0 << 30)
++#define ATMEL_TC_BSWTRG_SET (1 << 30)
++#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
++#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
++
++#define ATMEL_TC_CV 0x10 /* counter Value */
++#define ATMEL_TC_RA 0x14 /* register A */
++#define ATMEL_TC_RB 0x18 /* register B */
++#define ATMEL_TC_RC 0x1c /* register C */
++
++#define ATMEL_TC_SR 0x20 /* status (read-only) */
++/* Status-only flags */
++#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
++#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
++#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
++
++#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
++#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
++#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
++
++/* Status and IRQ flags */
++#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
++#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
++#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
++#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
++#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
++#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
++#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
++#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
++
++#endif
+diff -urN linux-2.6.24.3/include/linux/usb/atmel_usba_udc.h avr32-2.6/include/linux/usb/atmel_usba_udc.h
+--- linux-2.6.24.3/include/linux/usb/atmel_usba_udc.h 1970-01-01 01:00:00.000000000 +0100
++++ avr32-2.6/include/linux/usb/atmel_usba_udc.h 2008-04-23 20:12:47.000000000 +0200
+@@ -0,0 +1,22 @@
++/*
++ * Platform data definitions for Atmel USBA gadget driver.
++ */
++#ifndef __LINUX_USB_USBA_H
++#define __LINUX_USB_USBA_H
++
++struct usba_ep_data {
++ char *name;
++ int index;
++ int fifo_size;
++ int nr_banks;
++ int can_dma;
++ int can_isoc;
++};
++
++struct usba_platform_data {
++ int vbus_pin;
++ int num_ep;
++ struct usba_ep_data ep[0];
++};
++
++#endif /* __LINUX_USB_USBA_H */
+diff -urN linux-2.6.24.3/include/video/atmel_lcdc.h avr32-2.6/include/video/atmel_lcdc.h
+--- linux-2.6.24.3/include/video/atmel_lcdc.h 2008-02-26 01:20:20.000000000 +0100
++++ avr32-2.6/include/video/atmel_lcdc.h 2008-04-23 19:33:52.000000000 +0200
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